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  • CLOCK DISTRIBUTION ON STANDING WAVEWITH CMOS ACTIVE INDUCTOR LOADING

    Jing Yang

    A DISSERTATION

    SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTSFOR THE DEGREE OF

    DOCTOR OF PHILOSOPHY

    Department of Electrical and Computer Engineering

    College of Engineering

    Northeastern University

    Boston, Massachusetts

    April 24, 2017

    Doctoral Committee

    Prof. Yong-Bin Kim (Chair)

    Prof. Nian X. Sun

    Prof. Fabrizio Lombardi

    1

  • Abstract

    Global clock distribution design is becoming an increasingly challenge

    task for multi GHz microprocessors. Clock skew and jitter requirement are

    becoming more and more stringent as clock frequency increases. For tradi-

    tional clock distributions, skew and jitter are proportional to latency, which

    is dominated by a series of resistive-capacitance delay and does not scale

    with clock period. Moreover, the resistive-capacitance wire-load consumes a

    significant amount of power.

    As an alternative, resonant clock is applied to reduce dynamic power

    and achieve better control of clock skew and jitter. There are three ap-

    proaches to create resonant clocks, standing wave, traveling wave, and L-C

    tank resonance. Among these approaches, standing wave clock scheme forms

    an energy efficient tank that dissipates power only at the parasitic resistance

    of the network. Furthermore, standing wave resonance has uniform phase

    across the entire clock network, which yields almost zero skew in global clock

    distribution. But its voltage and current vary spatially. To overcome the

    position-dependent amplitude variation and low output swing issue, passive

    inductive loading is proposed, where uniform phase and almost uniform am-

    plitude standing wave is realized.

    In this thesis, we extend the idea of clock distribution with inductive

    loading further by applying CMOS active inductor as inductive loading.

    2

  • Compared to passive inductor design, active inductor can potentially achieve

    tunable design with reduced area overhead and high Q value. Moreover, it is

    compatible with CMOS technology process and easily integrated into chip-

    sets. The thesis first presents a global clock distribution design by generating

    standing wave oscillations along inductively loaded micro-strip lines. Trans-

    mission line modeling is setting up and analyzed. An improved X-tree clock

    topology is employed and cross-coupled pair (CCP) is used to reduce loss

    on transmission line. Then standing wave clock distribution with active in-

    ductor loading is presented. Three types of active inductor loading on a

    standing wave resonant global clock distribution network are proposed. In

    the first case, we design a CMOS single cascoded active inductor with tuned

    capacitor to increase Q value. The design with a 0.6 nH active inductance

    achieves Q of 4630. Applying the active inductor to the entire clock network,

    the clock jitter introduced by the active inductor is 0.39 ps. Clock skew is

    0.39 ps. In the second case, a novel CMOS differential active inductor with

    CCP compensation is proposed. The design has 1.2 nH inductance and Q

    of 327. The clock jitter introduced by active inductor loading is 1ps. Clock

    skew is 0.52 ps. In the last case, a improved CMOS differential cascoded

    active inductor with 1nH inductance and Q 344 is designed. The clock jitter

    introduced by active inductor loading is 0.16 ps. Clock skew is 1.95 ps. All

    the schemes are based on an improved X-tree clock topology and simulated

    in CMOS 28nm technology. The proposed clock distribution schemes greatly

    reduce clock skew, jitter, power consumption and chip area.

    3

  • Acknowledgment

    I am very grateful to many people for their support and collaboration

    through my study in Northeastern University and in my life to date. This

    thesis would not have been possible without them. First and foremost, I

    would like to thank Professor Yong-bin Kim, my research advisor. He first

    raised up my interest in investigating clock distribution using standing wave.

    I was enlightened a lot by Professor Kims wisdom and ways he solves prob-

    lems. Thanks for all the guidance and discussions and challenges as well, all

    of which leads to a better understanding of the academic knowledge through

    these many years of research and my thesis.

    I also would like to thank Professor Nian X. Sun and Professor Fabrizio

    Lombardi for serving as my thesis defense committee. Thanks for the time

    and effort, the valuable suggestions and generous support. My thanks also

    goes to Professor Joseph Ayers, and Professor Kyung Ki Kim for the fantastic

    research topic we made together. I learned a lot from this project.

    I am deeply indebted to all of my group mates in HPVLSI group, par-

    ticularly Inseok Jung, Heungjun Jeon, Jing Lu and Sheng Lin, thanks for

    all the discussion and sharing of knowledge during the research. My lab

    mates, Donny Yi, Daein Kang, Gyunam Jeon and Yongsuk Choi made life in

    HPVLSI lab lots of fun. I really enjoy the accompany and short talks with

    your guys. I would also like to thank Rongrong Fu, Chengcheng Jia and

    4

  • Nasibeh Teimouri for all the lunch conversation and tea time. I appreciate

    Junxiang Chens help for maintaining my desktop while I am remotely doing

    my research.

    Finally, I would like to thank my parents, it is their support and en-

    couragement that I can keep on purchasing the PhD degree. I am so lucky

    to be their daughter: I got a fulfillment of love from my parents, I know I

    always have a strong support on my back and I can reach the loved one when

    in need. I learned the best attitude towards study from them and I know

    how people treat their job if they love it. Thanks for all the chatting that I

    can share my achievements and frustrations. Thanks for the encouragement

    and scarification that I can go for my dream. Thanks for all the snacks and

    gifts that I got warmed even when I was alone overseas. I love you my dear

    parents.

    5

  • Contents

    1 Introduction 15

    1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

    1.2 Summary of Contributions . . . . . . . . . . . . . . . . . . . . 16

    1.3 Outline of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 18

    2 Clock Distribution System 19

    2.1 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . 19

    2.1.1 Clock Skew . . . . . . . . . . . . . . . . . . . . . . . . 19

    2.1.2 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . 20

    2.1.3 Power Consumption . . . . . . . . . . . . . . . . . . . 21

    2.2 Conventional Clock Distribution . . . . . . . . . . . . . . . . . 22

    2.2.1 Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

    2.2.2 Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

    2.2.3 Hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

    2.3 Resonant Clock Distribution . . . . . . . . . . . . . . . . . . . 25

    2.3.1 Traveling Wave Resonant . . . . . . . . . . . . . . . . . 26

    2.3.2 Standing Wave Resonant . . . . . . . . . . . . . . . . . 27

    2.3.3 LC Tank Resonant . . . . . . . . . . . . . . . . . . . . 28

    2.3.4 Oscillator Array . . . . . . . . . . . . . . . . . . . . . . 30

    3 Transmission Line and Modeling 32

    3.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

    6

  • 3.2 RLGC Matrix Extract . . . . . . . . . . . . . . . . . . . . . . 38

    4 Standing Wave Clock Distribution on Lossy Transmission

    Line 40

    4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

    4.2 Negative Resistance Circuit . . . . . . . . . . . . . . . . . . . 41

    4.2.1 Literature Reviews . . . . . . . . . . . . . . . . . . . . 41

    4.2.2 Modified Negative Resistance Circuit . . . . . . . . . . 43

    4.3 Standing Wave Clocking with Short Ended Load . . . . . . . . 45

    4.4 Passive Inductor Loading . . . . . . . . . . . . . . . . . . . . . 51

    5 Active Inductor Loading for Transmission Line 58

    5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

    5.2 Single-Ended Active Inductor . . . . . . . . . . . . . . . . . . 59

    5.2.1 General Active Inductor Structure . . . . . . . . . . . . 59

    5.2.2 Circuit Examples . . . . . . . . . . . . . . . . . . . . . 66

    5.2.3 Improved Single-Ended Active Inductor . . . . . . . . . 71

    5.3 Differential Active Inductor . . . . . . . . . . . . . . . . . . . 76

    5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 76

    5.3.2 Improved Topology . . . . . . . . . . . . . . . . . . . . 78

    5.3.3 Differential Active Inductor with Cross-Coupled Pair

    Compensation . . . . . . . . . . . . . . . . . . . . . . . 81

    5.3.4 Cascoded Differential Active Inductor . . . . . . . . . . 85

    7

  • 6 Standing Wave Clock Distribution with Active Inductor Load-

    ing 91

    6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

    6.2 Standing Wave Clock Distribution with Single-Ended Active

    Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

    6.3 Standing Wave Clock Distribution with Differential Active In-

    ductor(CCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

    6.4 Standing Wave Clock Distribution with Cascoded Differential

    Active Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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