chip ex 2011 faraday
TRANSCRIPT
Integral System-Level Design Integration,
Simulation, Verification & Implementation
May 4, 2011
Market Fact for Increasing Complex System-Level Design
PND/MID Automotive Netbook/Smartbook
The product life cycle of every
generation for most industrial products,
is around and even less than 1 year.
VoIP
STB
Digital-TV
PNDIPC
E-Book
is around and even less than 1 year.
But, it seems twice devices are built into the same
chip area per 18 months
by Moore’s law.
May 4, 2011
Brief of Complex System-Level Design from Spec. to Be a Product
� Firm product spec.
� Get IPs from sources� System-level design (SLD)
integration from IPs by� Product owner self, and� Help from IP sources
� Other time/resource-consuming
efforts for -� Frontend simulation/
verification� Backend Implementation/ � Backend Implementation/
Verification� System-level verification, if
possible� Sign-off & Go-To-
Manufacture� Software support
� OS� Driver (IP/ICE)� Toolchain
� System application bring-up
May 4, 2011
Bottleneck of Increasing Complex System-Level Design
� Survey Market
Requirement
Document. (MRD)
� Gather Product
Requirement
Document. (PRD)
� Refine/Trade-off
2 months
SoC/ASIC
Integration
2 months
SoC/ASIC
Implementation
2 months
Data-in Preparation3 ~ 6 months
Platform integration
~3 months
Spec.
Kickoff Spec Formal Data-InTrial Data-In Tape-Out
� Simulation-oriented
integration
� Get IPs from sources.
� SLD integration from IPs.
� BFM testbench creation
& C models for
� Synthesis-oriented
integration
� Synthesizable target
designs more than
models, such as clock
control, reset control,
� Implementation-
oriented tasks
� Clock/reset tree
control/constraints.
� Chip-level synthesis
design constraints.
� Backend Gate-To-
GDSII tasks
� SLD physical
implementation
� SLD physical
verification -
Ordinary solutions take 12 ~ 16 months from project kickoff to tape-out for complex
SoC designs.
� Refine/Trade-off
MRD & PRD.
� Early System
Architecture
Evaluation.
� Get Product Brief.
� IP Sourcing.
� Etc.
& C models for
integration test. (verify
connection, bus, and so
on)
� DFT integration.
� Iterative verification &
debugging.
� FPGA emulation 1.
� Etc.
control, reset control,
real I/O and so on.
� C patterns, instead of
BFM-only ones.
� Iterative verification &
debugging.
� FPGA emulation 2.
� Etc.
design constraints.
� Pin/Pad assignment &
Chip environment
constraints.
� FloorPlan constraints.
� Pre-layout design data
base & simulation.
� ATPG creation.
� Etc.
verification -
DRC/ERC/LVS
� Verified GSDII for
Go-To-
Manufacture
� Post-layout
design data base
& simulation.
� Sign-off & T/O.
� Etc.
May 4, 2011
Fact of Increasing Complex System-Level Design
Ordinary solutions take 12 ~ 16 months from project kickoff to tape-out for complex SoC designs.
The product life cycle of everygeneration for most industrial products,is around and even less than 1 year.
But, it seems twice devices are built into the same chip area per 18 monthsby Moore’s law.
tape-out for complex SoC designs.
All of us are competing against –
� Design/Verification Complexity
� Time & our Life
May 4, 2011
The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability – 1/5
Pack and maintain each IP as an Abstract Model (SPIRIT) and basic re-use
entity for accumulative knowledge data base.
Bus Controller
(Arbiter,
Decoder)
AHB Bus
FA526MAC
10/100
AHB to PCI
Bridge
SDRAM
Controller
Static
Memory
Controller
LCD
Controller
DMA
Controller
USB2.0
Device
USB2.0
PHY
USB1.1
Host
USB 1.1
PHY
IP Model OutputInputAHB to APB
Bridge
APB Bus
ControllerController
Controller Controller
Power
manage
FF
UARTIrDA
BT
UART
ST
UARTCF
SD/
MMC
SMMCINTCPWM GPIOI2C WDT Timer
SSPSSP
I2S/
AC97
IP Model
Side Band
Signals
Output
Interface
Input
Interface
SPIRIT stands for “Structure for Packaging, Integrating and Re-using IP within Tool flows”.
May 4, 2011
The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability - 2/5
Tables Description Applied Module
$<design>.pin.xml Chip pin-out list table: chip
pin name, IO types
Chip Construction:
pin module creation
Use three Microsoft Excel specification sheets that involve SPIRIT instances of
wanted IPs, to capture the whole SLD every time.
$<design>.dftcfg.xml DFT configuration table:
internal scan, mbist, VSIA,
hard-IP test, IOLT, process
monitor, debug signals
Chip Construction:
DFT module creation
$<design>.resmap.xml Resource table: IP list,
instances, Master/Slave
mapping, interrupt, DMA
Core Construction
May 4, 2011
The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability - 3/5
Three Microsoft Excel specification sheets look as -
May 4, 2011
The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability - 4/5
Then, all things can be looked like -
� Capturing
specification
� Creation on
demand
� Plugging
And, can be done more safe, reliable & accumulative as Plug & Play method
automatically.
� Plugging
� Implementation/V
erification
environment
creation
May 4, 2011
The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability - 5/5
� Automatic SLD RTL design integration
� Rapid DFT integration
� Automatic verification environment generation (Bus, IO, DFT)
� Test-bench creation and pattern-reuse
SoCompilerTM IDE
� Test-bench creation and pattern-reuse
� Static timing analysis environment generation
� Design synthesis environment generation
� Link to existing robust ASIC implementation flow natively
� Link to FPGA emulation platform SoFlexibleTM with FPGA netlist and
constraint
May 4, 2011
Achievement of Reliable Integral SoC Methodology for Complex SLD
2 months
SoC/ASIC
Integration
2 months
SoC/ASIC
Implementation
2 months
Data-in Preparation3 ~ 6 months
Platform integration
~3 months
Spec.
Kickoff Spec Formal Data-InTrial Data-In Tape-Out
Ordinary
Solutions take 12 ~ 16 months from project kickoff to tape-out for complex SoC designs.
1 month 2 months1.5 months3.5 w2.5 w
Platform Delivery Tape-OutSpec Signoff Trial Data-In
Formal Data-InKickoff
Platform Simulation
PlatformSynthesis
Faraday’s reliable integral SoC methodology can take only 6 months to achieve by the accumulative
knowledge and re-usability.
May 4, 2011
Brief of Complex System-Level Design from Spec. to Be a Product (repetition)
� Firm product spec.
� Get IPs from sources� System-level design (SLD)
integration from IPs by� Product owner self, and� Help from IP sources
� Other time/resource-consuming
efforts for -� Frontend simulation/
verification� Backend Implementation/
verification� Backend Implementation/
Verification� System-level verification, if
possible� Sign-off & Go-To-
Manufacture� Software support
� OS� Driver (IP/ICE)� Toolchain
� System application bring-up
May 4, 2011
Ordinary SoC evaluation-purpose-only platform
� Pre-defined system-level design
(SLD), built into the chip and the
evaluation platform.
� May include some S/W or
tool kits for the evaluation.
� Can’t be another targeted SLD
with different system/ bus
architecture, I/O address
SoC chip
architecture, I/O address
mapping, etc.
� Help for –
� IP evaluation.
� Fundamental rough S/W
development.
Overall evaluation platform
May 4, 2011
SoFlexibleTM FPGA emulationplatform EVB
� Integrating the targeted
SLD into the FPGA emulation platform.
� Help for –� Consistent/Solid firm
IPs from soft IPs, instead of any IP
.instead of any IP
modeling efforts.� System-level
function verification.� Fundamental system
architecture evaluation.
� Further exact S/W development.
FPGA
Wanted passive components
May 4, 2011
SoDualWareTM Technology – 1/3
May 4, 2011
SoDualWareTM Technology – 2/3
May 4, 2011
SoDualWareTM Technology – 3/3� Silicon hard IPs in the
realized platform, utilized to support the targeted SLD.
� Help for –� Native IP modeling.
� IP evaluation.
� Peripheral modeling, connecting to real world.world.
� System-level verification.
� Further detailed system architecture evaluation.
� More exact S/W development.
Realized platform
Targeted system-leveldesign
May 4, 2011
Thank you
Faraday distributor in Israel:
Advanced Semiconductor Technology Ltd. (AST)Tel: +972-9-7744278
Email: [email protected]
May 4, 2011