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CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

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CHAPTER 9

MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

Contents

9.1 Introduction

9.2 Multiplexers

9.3 Three-State Buffers

9.4 Decoders and Encoders

9.5 Read-Only Memories

9.6 Programmable Logic Devices

9.7 Complex Programmable Logic Devices

9.8 Field Programmable Gate Arrays

Objectives

1. Explain the function of a multiplexer. Implement a multiplexer using gates.2. Explain the operation of three-state buffers. Determine the resulting output when

three-state buffers outputs are connected together. Use three-state buffers to multiplexsignals onto a bus.

3. Explain the operation of a decoder and encoder. Use a decoder with added gates toimplement a set of logic functions. Implement a decoder or priority encoder using gates.

4. Explain the operation of a read-only memory (ROM). Use a ROM to implement a set oflogic functions.

5. Explain the operation of a programmable logic array (PLA). Use a PLA to implement a set of logic functions. Given a PLA table or an internal connection diagram for a PLA, determine the logic functions realized.

6. Explain the operation of a programmable array logic device (PAL). Determine the programming pattern required to realize a set of logic function with a PAL.

7. Explain the operation of a complex programmable logic device (CPLD) and a field programmable gate array (FPGA).

8. Use Shannon’s expansion theorem to decompose a switching function.

9.1 Introduction

• Multiplexer, Decoder, encoder. Three-state Buffer

• ROMs

• PLD

• PLA

• CPLD

• FPGA

9.2 Multiplexers

Fig 9-1. 2-to-1 Multiplexer and Switch Analog

10' AIIAZ +=

MUX 1-to-2 for theequation logic

9.2 Multiplexers

Fig 9-2. Multiplexer (1)

3210 '''' ABIIABBIAIBAZ +++=

MUX 1-to-4 for theequation logic

9.2 Multiplexers

7654

3210

'''' ''''''''

ABCIIABCCIABICABBCIAIBCACIBAICBAZ

+++++++=

MUX 1-to-8 for theequation logic

Fig 9-2. Multiplexer (2)

9.2 Multiplexers

∑−

=

=12

0

n

kkk ImZ

MUX 1-to-2 for theequation logic n

Fig 9-2. Multiplexer (3)

9.2 Multiplexers

Fig 9-3. Logic Diagram for 8-to-1 MUX

9.2 Multiplexers

Fig 9-4. Quad Multiplexer Used to Select Data

Fig 9-5. Quad Multiplexer with Bus Inputs and Output

9.2 Multiplexers

9.3 Three-State Buffers

Fig 9-6. Gate Circuit with Added Buffer

9.3 Three-State Buffers

Fig 9-7. Three-State Buffer

9.3 Three-State Buffers

Fig 9-8. Four Kinds of Three-State Buffers

ZZ01

0 00 11 01 1

CB A

(a)

ZZ10

0 00 11 01 1

CB A

(b)

01ZZ

0 00 11 01 1

CB A

(c)

10ZZ

0 00 11 01 1

CB A

(d)

We use the Symbol Z to represent high-impedance state

9.3 Three-State Buffers

Fig 9-9. Data Selection Using Three-State Buffers

9.3 Three-State Buffers

Fig 9-10. Circuit with Two Three-State Buffers

XX11

1

X0X0

S20

XXXX

X

X01Z

X01Z

ZS1

X = Unknown

9.3 Three-State Buffers

Fig 9-11. 4-Bit Adder with Four Sources for One Operand

9.3 Three-State Buffers

Fig 9-12. Integrated Circuit with Bi-Directional Input/Output Pin

9.4 Decoders and Encoders

Fig 9-13. 3-to-8 Line Decoder

00000010

y6

00000001

y7

10000000

y0

01000000

y1

00100000

y2

00010000

y3

00001000

y4

00000100

y5

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

a b c

9.4 Decoders and Encoders

Fig 9-14. A 4-to-10 Line Decoder (1)

9.4 Decoders and Encoders

Fig 9-14. A 4-to-10 Line Decoder (2)

1111111011111111

7

1111111101111111

8

Decimal OutputBCD Input

1111110111111111

6

1111111110111111

9

0111111111111111

0

1011111111111111

1

1101111111111111

2

1110111111111111

3

1111011111111111

4

1111101111111111

5

0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

A B C D

(c) Truth Table

9.4 Decoders and Encoders

Fig 9-15. Realization of a Multiple-Output Circuit Using a Decoder

outputs) (inverted 12 to0 ,'

outputs) ed(noninvert 12 to0 ,

−===

−==

niii

nii

iMmyor

imy

)''''(),,,(

421

4211

mmmmmmdcbaf

=++=

)''''(),,,(

974

9742

mmmmmmdcbaf

=++=

9.4 Decoders and Encoders

Fig 9-16. 8-to-3 Priority Encoder

00001XXXX

y3

000001XXX

y4

0000001XX

y5

00000001X

y6

000000001

y7

000001111

a

000110011

b

001010101

c

001XXXXXX

y1

0001XXXXX

y2

01XXXXXXX

y0

011111111

d

9.5 Read-Only Memories

Fig 9-17. An 8-Word x 4-Bit ROM

11001010

F0

01010101

C

00111011

F1

11100010

F2

00110111

F3

00110011

B

00001111

A

(a) Block diagram (b) Truth table for ROM

typical data stored in ROM

(23 words of

4bits each)

9.5 Read-Only Memories

Fig 9-18. Read-Only Memory with n Inputs and m Outputs

100010101110

001110011111

· · · ·· · · ·· · · ·· · · ·

··

· · · ·· · · ·· · · ·· · · ·

m outputVariables

· · · ·· · · ·· · · ·· · · ·

··

· · · ·· · · ·· · · ·· · · ·

110111101010

··

011110000101

00011011

00011011

00000000

11111111

n inputVariables

typical data array stored

in ROM

(2n words of

m bits each)

9.5 Read-Only Memories

Fig 9-19. Basic ROM Structure

9.5 Read-Only Memories

Fig 9-20. An 8-Word x 4-Bit ROM

∑∑∑∑

+==

+==

+==

+==

BACmF

BCBAmF

ACBmF

ACBAmF

)7,6,5,3,2(

''')6,2,1,0(

')7,6,4,3,2(

''')6,4,1,0(

3

2

1

0

9.5 Read-Only Memories

Fig 9-21. Equivalent OR Gate for F0

∑ +== ''')6,4,1,0(0 ACBAmF

9.5 Read-Only Memories

Fig 9-22. Hexadecimal to ASCII Code Converter

ASCII Code for Hex DigitInput

0123456789ABCDEF

0000000000111111

A6

1111111111000000

A5

1111111111000000

A4

0000000011000000

A3

0000111100000111

A2

0011001100011001

A1

HexDigit

0101010101101010

0101010101010101

0011001100110011

0000111100001111

0000000011111111

A0ZYXW

9.5 Read-Only Memories

Fig 9-23. ROM Realization of Code Converter

9.6 Programmable Logic Devices

Fig 9-24. Programmable Logic Array Structure

9.6 Programmable Logic Devices

Fig 9-25. PLA with Three Inputs, Five Product Terms, and Four Outputs

9.6 Programmable Logic Devices

Fig 9-26. AND-OR Array Equivalent to Figure 9-25

9.6 Programmable Logic Devices

Table 9-1. PLA Table for Figure 9-25

OutputsInputs

-0-01

C

11000

F0

01100

F1

10010

F2

00101

F3

0-11-

01--1

A’B’AC’

BBC’AC

BA

ProductTerm

ACBFBCBAF

BACFACBAF

+=+=+=+=

3

2

1

0

''''

'''

9.6 Programmable Logic Devices

Fig 9-27. PLA Realization of Equations (7-23b)

111100

f1

100010

f2

011001

f3

11----

--0111

1100-1

011---

dcba

(a) PLA table

9.6 Programmable Logic Devices

Programmable Array Logic

The symbol of Figure 9-28(a)

logically equal

9.6 Programmable Logic Devices

Connections to the AND gate inputs in a PAL

Programmable Array Logic

9.6 Programmable Logic Devices

Fig 9-28. PAL Segment

9.6 Programmable Logic Devices

Fig 9-29. Implementation of a Full Adder Using a PAL

inininin XYCCXYYCXCYX +++= ''''''

XYYCXC inin ++=

9.7 Complex Programmable Logic Devices

Fig 9-30. Architecture of Xilinx XCR3064XL CPLD(Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc.1999-2003.

All rights reserved.)

9.7 Complex Programmable Logic Devices

Fig 9-31. CPLD Function Block and Macrocell (A Simplified Version of XCR3064XL)

9.8 Field Programmable Gate Arrays

Fig 9-32. Equivalent OR Gate for F0

9.8 Field Programmable Gate Arrays

Fig 9-33. Simplified Configurable Logic Block (CLB)

9.8 Field Programmable Gate Arrays

Fig 9-34. Implementation of a Lookup Table (LUT)

01··1

d

01··1

00··1

00··1

00··1

fcba

abcddabccdabdcabbcdadbcacdbadcbaF +++++++= ''''''''''''''''

9.8 Field Programmable Gate Arrays

Decomposition if switching Functions

10'),,,1(),,,0('),,,( affadcbafdcbfadcbaf +=+=

10')'()'''(')'''()'''('

'''''),,,(

affabdcacdcbdcacbcddcabcdcbdca

acbcdcbadcdcbaf

+=++++=+++++=

+++=

iii

niiiniii

niii

fxfxxxxxxfxxxxxxfx

xxxxxxf

+=+= +−+−

+−

0

11211121

1121

'),...,,1,,...,,(),...,,0,,...,,('

),...,,,,...,,(

9.8 Field Programmable Gate Arrays

Decomposition if switching Functions

10'),,,,1(),,,,0('),,,,( affaedcbafedcbfaedcbaf +=+=

11101

01000

10

'),,,,1,1(),,,,0,1(''),,,,1,0(),,,,0,0(''),,,,,1(),,,,,0('),,,,,(

bGGbfedcbGfedcGbGbGGbfedcbGfedcGbGaGGafedcbaGfedcbGafedcbaG

+=+=+=+=+=+=

11100100 ''''),,,,,( abGGabbGaGbafedcbaG +++=

9.8 Field Programmable Gate Arrays

Fig 9-35. Function Expansion Using a Karnaugh Map

9.8 Field Programmable Gate Arrays

Fig 9-36. Realization of Five- and Six-Variable Functions

with Function Generators