chapter 3 memory management part 2 by u ğ ur halıcı

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CHAPTER 3 MEMORY MANAGEMENT PART 2 by U ur Halc Slide 2 3.3 Paging Logical memory PAGE TABLE Physical memory pageframeAttributes 04 13 21 35 1 In paging, the OS divide the physical memory into frames which are blocks of small and fixed size Slide 3 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 f4 f5 2 In paging, the OS divide the physical memory into frames which are blocks of small and fixed size Slide 4 3.3 Paging Logical memory PAGE TABLE Physical memory pageframeAttributes f0 04 f1 13 f2 21 f3 35 f4 f5 3 OS divides also the logical memory (program) into pages which are blocks of size equal to frame size. Slide 5 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 f4 f5 4 OS divides also the logical memory (program) into pages which are blocks of size equal to frame size. Slide 6 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 f4 f5 5 The OS uses a page table to map program pages to memory frames. Slide 7 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 P0f4 f5 6 The OS uses a page table to map program pages to memory frames. Slide 8 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 P1f3 35 P0f4 f5 7 The OS uses a page table to map program pages to memory frames. Slide 9 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 P2f1 P2 13 f2 P3 21 P1f3 35 P0f4 f5 8 The OS uses a page table to map program pages to memory frames. Slide 10 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 P2f1 P2 13 f2 P3 21 P1f3 35 P0f4 P3f5 9 The OS uses a page table to map program pages to memory frames. Slide 11 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 P2f1 P2 13 f2 P3 21 P1f3 35 P0f4 P3f5 10 Paging permits a program to allocate noncontiguous blocks of memory Slide 12 3.3 Paging Page size (S) is defined by the hardware. Generally page size is chosen as a power of 2 such as 512 words/page or 4096 words/page etc. With this arrangement, the words in the program have an address called as logical address. Every logical address is formed of pair 11 Slide 13 3.3 Paging Logical address: p is page number p = logical address div S d is displacement (offset) d = logical address mod S 12 Slide 14 3.3 Paging When a logical address is generated by the processor, first the frame number f corresponding to page p is determined by using the page table and then the physical address is calculated as (f*S+d) and the memory is accessed. 13 Slide 15 3.3 Paging Logical address Physical address pdfd pageframeattr d d p f pf logical memory physical memory 14 Slide 16 3.3 Paging Example 3.2 Consider the following information to form a physical memory map. Page Size = 8 words d : 3 bits Physical Memory Size = 128 words = 128/8=16 frames f : 4 bits Assume maximum program size is 4 pages p : 2 bits A program of 3 pages where P0 f3; P1 f6; P2 f4 15 Slide 17 Logical memoryPhysical memory Word 0 Word 1 Page 0Word 0 (P0)Word 1 Frame 3 Word 7 PAGE TABE (f3) Word 8PageFrameWord 7 Word 9 Page 103Word 16 (P1)16Word 17 Frame 4 Word 1524 (f4) Word 16Word 23 Word 17 Page 2 (P2) Word 23 Word 8 Word 9 Frame 6 (f6) Word 15 16 Slide 18 3.3 Paging Program Line Word 0 Word 1 Word 7 Word 8 Word 9 Word 15 Word 16 Word 17 Word 23 17 Slide 19 3.3 Paging Program Line Logical Address Word 000 000 Word 100 001 Word 700 111 Word 801 000 Word 901 001 Word 1501 111 Word 1610 000 Word 1710 001 Word 2310 111 18 Slide 20 3.3 Paging Program Line Logical Address Offset Word 000 000000 Word 100 001001 Word 700 111111 Word 801 000000 Word 901 001001 Word 1501 111111 Word 1610 000000 Word 1710 001001 Word 2310 111111 19 Slide 21 3.3 Paging Program Line Logical Address OffsetPage Number Word 000 00000000 Word 100 00100100 Word 700 11111100 Word 801 00000001 Word 901 00100101 Word 1501 11111101 Word 1610 00000010 Word 1710 00100110 Word 2310 11111110 20 Slide 22 3.3 Paging Program Line Logical Address OffsetPage Number Frame Number Word 000 000000000011 Word 100 001001000011 Word 700 111111000011 Word 801 000000010010 Word 901 001001010010 Word 1501 111111010010 Word 1610 000000100000 Word 1710 001001100000 Word 2310 111111100100 21 Slide 23 3.3 Paging Program Line Logical Address OffsetPage Number Frame Number Physical Address Word 000 0000000000110011 000 Word 100 0010010000110011 001 Word 700 1111110000110011 111 Word 801 0000000100100110 000 Word 901 0010010100100110 001 Word 1501 1111110100100110 111 Word 1610 0000001000000100 000 Word 1710 0010011000000100 001 Word 2310 1111111001000100 111 22 Slide 24 3.3 Paging Every access to memory should go through the page table. Therefore, it must be implemented in an efficient way. How to Implement The Page Table? Using fast dedicated registers Keep the page table in main memory Use content-addressable associative registers 23 Slide 25 Using fast dedicated registers Keep page table in fast dedicated registers. Only the OS is able to modify these registers. However, if the page table is large, this method becomes very expensive since requires too many registers. 24 Slide 26 Using fast dedicated registers 25 P