Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-1

Chapter 16: Design for Testability

Department of Electronic Engineering

National Taiwan University of Science and Technology

Prof. Ming-Bo Lin

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-2

Syllabus

ObjectivesFault DetectionTest vector generationTestable circuit designBoundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-3

Objectives

After completing this chapter, you will be able to:Describe various fault modelsUnderstand the fundamentals of fault detectionUnderstand the difficulties of sequential circuit testsUnderstand the basic principles of test vector generationDescribe the basic principles of testable circuit designUnderstand the principle of boundary scan standard (IEEE1149.1)

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-4

Syllabus

ObjectivesFault Detection

Fault modelsFault detectionDifficulty of sequential circuit test

Test vector generationTestable circuit designBoundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-5

Terminology Definition

What is a defect?What is an error?What is a fault?

Chapter 16: Design for Testability

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Fault Models

Stuck-at-0 faultStuck-at-1 faultBridge fault

Chapter 16: Design for Testability

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Fault Models

Stuck-open faultStuck-closed (stuck-on) fault

Chapter 16: Design for Testability

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Fault Models

Fault equivalenceFault collapseFault coverage

Chapter 16: Design for Testability

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Fault Detection

Controllability Observability

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-10

Fault Detection

A testable faultAn untestable fault

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-11

Fault Detection

An example of complete test set

Test vectors are {(0,1), (1,0), (1,1)}

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-12

Difficulty of Sequential Circuit Test

A homing sequenceA preset homing sequence

Chapter 16: Design for Testability

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Difficulty of Sequential Circuit Test

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-14

Difficulty of Sequential Circuit TestA transfer sequence A circuit is strongly connectedSo what are the difficulties of testing sequential circuits?

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-15

Syllabus

ObjectivesFault DetectionTest vector generation

Fault tablesFault simulation Boolean differencesPath sensitization

Testable circuit designBoundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-16

Fault TablesForm a fault table

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-17

Fault Tables

Build a fault detection table

Chapter 16: Design for Testability

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Fault Tables

Find a reduced fault table

The test vectors are: {(0,0,1), (0,1,0), (1,0,0), (1,1,0)}.

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-19

Syllabus

ObjectivesFault DetectionTest vector generation

Fault tablesFault simulationBoolean differencesPath sensitization

Testable circuit designBoundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-20

Fault Simulation

The fault simulation process is repeated until:All faults are coveredAt least an acceptable number of faults are covered, orSome predefined stopping point is reached

Chapter 16: Design for Testability

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Fault Simulation

Types of fault simulationThe row methodThe column method

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-22

Fault Simulation

The row method

Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,1,0)}.

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-23

Fault Simulation

The column method

Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1), (1,1,0)}.

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-24

Syllabus

ObjectivesFault DetectionTest vector generation

Fault tablesFault simulation Boolean differencesPath sensitization

Testable circuit designBoundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-25

Boolean Differences

Boolean difference (Boolean partial derivative)

Not an effective way

)1()0(

),...,,1,,...,(),...,,0,,...,()(01110111

ii

iiniin

ff

xxxxfxxxxfdx

Xdf

⊕=

⊕= −+−−+−

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-26

Boolean Differences

Example:

To test stuck-at-0 fault at net xi

To test stuck-at-1 fault at net xi

1)( =i

i dxXdfx

1)(' =i

i dxXdfx

321)( xxxXf +=

( ) ( ) ( )

( ) ( ) 32332332

33232321

'''

01)(

xxxxxxxx

xxxxxxxdx

Xdf

=+++=

⊕+=+⋅⊕+⋅=

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-27

Boolean Differences

Stuck-at-0 fault at net α is

The test vector set is {(0, 0, 1, 1), (1, f, 1, 0), (f, 1, 1, 0)}.

( ) 43321 ')( xxxxxXf ++=

[ ]

4324314321

3333

3

''''

)1()0(1)(

xxxxxxxxxx

ffxdx

Xdfx

++=

+==

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-28

Boolean Differences

Stuck-at-0 fault at net β is

The test vector set is {(1, φ, 0, φ), (φ, 1, 0, φ)}.

21 xxy +=

433'),( xxyxyXf +=

( )[ ]

( ) 3231321

343343

'''

''),(

xxxxxxx

yxxxxxxydy

yXdfy

+=+=

=+⊕=⋅

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-29

Syllabus

ObjectivesFault DetectionTest vector generation

Fault tablesFault simulation Boolean differencesPath sensitization

Testable circuit designBoundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-30

Basic Operations of Path Sensitization

Fault sensitizationFault propagationLine justification (Consistency operation)

Chapter 16: Design for Testability

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Path Sensitization

Sensitized path

Unsensitized path

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-32

Path Sensitization

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-33

Syllabus

ObjectivesFault DetectionTest vector generationTestable circuit design

Ad hoc testingScan-path methodsBuilt-in self test (BIST)

Boundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-34

Ad hoc Testing

Basic principles are to increase observabilitycontrollability

MethodsProviding more control and test points Using multiplexers to increase the number of internal control and test points Breaking feedback paths Using state registers to reduce the additional of I/O pins required for testing signals

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-35

Ad hoc Testing

An example of exhaustive test

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-36

Syllabus

ObjectivesFault DetectionTest vector generationTestable circuit design

Ad hoc testing Scan-path methodsBuilt-in self test (BIST)

Boundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-37

Scan-Path Methods

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-38

Syllabus

ObjectivesFault DetectionTest vector generationTestable circuit design

Ad hoc testing Scan-path methodsBuilt-in self test (BIST)

Boundary-scan standard

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-39

BIST Principles

Chapter 16: Design for Testability

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Automatic Test Pattern Generation (ATPG)(ALFSR)

Pr-sequence generator

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-41

Automatic Test Pattern Generation (ATPG)

A sample primitive polynomials for n from 1 to 60

Chapter 16: Design for Testability

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Signature Generators

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-43

A Signature Application Example

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-44

A BIBLO Example

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-45

Syllabus

ObjectivesFault DetectionTest vector generationTestable circuit designBoundary-scan standard

IEEE 1149.1 StandardTAP structureBoundary scan cells

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-46

IEEE 1149.1 --- An Application Example

Test the entire board-level module

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-47

The Structure of IEEE 1149.1

Test access port (TAP)Data registersTDO driverInstruction register and decoder TAP controller

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-48

Syllabus

ObjectivesFault DetectionTest vector generationTestable circuit designBoundary-scan standard

IEEE 1149.1 StandardTAP structureBoundary scan cells

Chapter 16: Design for Testability

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The TAP Structure

Test data registers (test DRs)Instruction register and decoderTAP controllerTDO driver

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-50

Control Signals of IEEE 1149.1

Four control signalsTCK (test clock, input) TDI (test data input, input) TDO (test data output, output) TMS (test mode select, input)

One optional reset signalTRST_n (test reset)

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-51

Control Signals of IEEE 1149.1

In the normal modeTRST_n and TCK are held lowTMS is held high

To prevent race conditionsInputs are sampled on the positive edge of TCKOutput toggle on the negative edge

Chapter 16: Design for Testability

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The State Machine of IEEE 1149.1

Chapter 16: Design for Testability

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Instruction and Bypass Registers

Instruction register cellShift registerInstruction register

Bypass register structure

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-54

A TDO Driver

TDO DriverTMS is sampled at the positive edge of TCKTDO is sampled at the negative edge of TCK

Chapter 16: Design for Testability

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-55

Syllabus

ObjectivesFault DetectionTest vector generationTestable circuit designBoundary-scan standard

IEEE 1149.1 StandardTAP structureBoundary scan cells

Chapter 16: Design for Testability

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Boundary Scan Cells

Operation modes of boundary scan cells (BSC)Normal mode Capture modeScan modeUpdate mode

Chapter 16: Design for Testability

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Boundary Scan Cell

Chapter 16: Design for Testability

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Boundary Scan Cells

Chapter 16: Design for Testability

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A Complete Example