chapter 11 timing issues in digital systems boonchuay supmonchai integrated design application...

Chapter 11Chapter 11

Timing Issues in Digital SystemsTiming Issues in Digital Systems

Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory

August 20, 2004; Revised - July 5, 2005

2102-545 Digital ICs2102-545 Digital ICs Timing Issues in Digital Systems

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B.SupmonchaiB.Supmonchai

Goals of This ChapterGoals of This Chapter Introduction to timing issues in digital design

Classification of Digital systems

Impact on performance and functionality Clock SkewClock Skew

Clock JitterClock Jitter

Clock-Distribution Techniques


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Timing ClassificationsTiming Classifications Synchronous systems

All memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal (i.e., a global clock signal)

Functionality is ensure by strict constraints on the clock signal generation and distribution to minimize Clock skewClock skew (spatial variations in clock edges)

Clock jitterClock jitter (temporal variations in clock edges)


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Timing Classifications IITiming Classifications II Asynchronous systems

Self-timed (controlled) systemsSelf-timed (controlled) systems

No need for a globally distributed clock, but have asynchronous circuit overheads (handshaking logic, etc.)

Hybrid systems Mesochronous and Plesiochronous Systems

SynchronizationSynchronization between different clock domains

Interfacing between asynchronous and synchronous domains


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Synchronous System Timing BasicsSynchronous System Timing Basics

Under ideal conditions (i.e., when ttclk1clk1 = = ttclk2clk2)

TT ttc-qc-q + + ttplogicplogic + + ttsusu

ttholdhold ≤ ≤ ttcdlogiccdlogic + + ttcdregcdreg

ttc-qc-q, t, tsusu,,

ttholdhold, t, tcdregcdreg

clkclk ttclk1clk1 ttclk2clk2

D Q

R1R1CombinationalCombinational

LogicLogic D Q

R2R2

InIn

ttc-qc-q, t, tsusu,,

ttholdhold, t, tcdregcdreg

Maximum Clock Period, TMaximum Clock Period, T

ttplogicplogic, t, tcdlogiccdlogic


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Clock UncertaintiesClock Uncertainties

PLLPLL

11clock clock generationgeneration

22 clock driversclock drivers

44 power supplypower supply

33 interconnectinterconnect66 capacitive loadcapacitive load

77 capacitive capacitive couplingcoupling

55 temperaturetemperature

Under real conditions, clock signal can have both spatialspatial and temporaltemporal variations Systematic (Deterministic)Systematic (Deterministic) - easy to model and correct for at

design time

RandomRandom - difficult to model and eliminate


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Clock NonidealitiesClock Nonidealities Clock skew, ttSKSK (Pink Pink + + OrangeOrange)

Spatial variation in temporally equivalent clock edges

Can be either deterministic or random or both

Clock jitter (BlueBlue + OrangeOrange) Temporal variations in consecutive edges of the clock signal

Modulation and random additive noise

Short term (cycle-to-cycle) ttJSJS and long term ttJLJL

Variation of the pulse width Important for level sensitive clocking


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ClkClk

ClkClk

ttSKSK

ttJSJS

Clock Skew and JitterClock Skew and Jitter

Both clock skew and jitter affect the effective cycle time

Only clock skew affects the race margin


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Distribution of Clock SkewDistribution of Clock Skew

Earliest occurrenceEarliest occurrenceof of ClkClk edge edgeNominal – Nominal – /2/2

# of registers# of registers

Clk delayClk delayInsertion delayInsertion delay

Latest occurrenceLatest occurrenceof of ClkClk edge edge

Nominal + Nominal + /2/2

Max Max ClkClk skew skew

NegativeNegative PositivePositive


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Positive Clock SkewPositive Clock Skew

clkclk ttclk1clk1 ttclk2clk2

delaydelayTT

>> 00

+ t+ tholdhold

T + T + t tc-qc-q + t + tplogic plogic + t+ tsusu so T T t tc-qc-q + t + tplogic plogic + t+ tsu su - - ttholdhold + + ≤ t≤ tcdlogiccdlogic + t + tcdregcdreg so ttholdhold ≤ t≤ tcdlogiccdlogic + t + tcdreg cdreg - -

Clock and data flow in the same direction

D Q


LogicLogic D Q

R2R2

InIn

T + T + 1

2

3

4


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Negative Clock SkewNegative Clock Skew

D Q


LogicLogic D Q

R2R2

InIn

clkclkttclk1clk1 ttclk2clk2

delaydelay

TT

<< 0 0

T + T + t tc-qc-q + t + tplogic plogic + t+ tsusu so T T t tc-qc-q + t + tplogic plogic + t+ tsu su - - ttholdhold + + ≤ t≤ tcdlogiccdlogic + t + tcdregcdreg so ttholdhold ≤ t≤ tcdlogiccdlogic + t + tcdreg cdreg - -

2

1 3

4

T + T +

Clock and data flow in opposite direction


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T - 2tT - 2tjitterjitter t tc-qc-q + t + tplogic plogic + t+ tsu su so so T T t tc-qc-q + t + tplogic plogic + t+ tsu su + 2t+ 2tjitterjitter

Jitter directly reduces the performance of a sequential circuitJitter directly reduces the performance of a sequential circuit

Clock JitterClock Jitter Jitter causes TT

to vary on a cycle-by-cycle basis

clkclk ttclkclk

D Q


LogicLogicInIn

TT

-t-tjitterjitter +t+tjitterjitter


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ttclk1clk1 ttclk2clk2

> > 00

-t-tjitterjitter

T T t tc-qc-q + t + tplogic plogic + t+ tsu su - - + 2t + 2tjitterjitter tthold hold ≤ t≤ tcdlogiccdlogic + t + tcdreg cdreg – – – 2t – 2tjitterjitter

Combined Impact of Skew and JitterCombined Impact of Skew and Jitter Constraints on the minimum clock period ( > 0)

D Q


LogicLogic D Q

R2R2

InIn

1

6 12

TTT + T +


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Note on Clock SkewNote on Clock Skew ForFor Positive Clock skewPositive Clock skew: > 0 improvesimproves

performance, but makes ttholdhold harder to meet. If ttholdhold is not met (race conditions), the circuit malfunctions independent of the clock period!

For Negative Clock skewFor Negative Clock skew: < 0 degradesdegrades performance, but ttholdhold is easier to meet (eliminating race conditions)

For Skew with JitterFor Skew with Jitter: > 0 with jitter degrades performance, and makes ttholdhold even harderharder to meet. (The acceptable skew is reduced by jitter.)


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Clock Distribution NetworksClock Distribution Networks Clock skew and jitter can ultimately limit the

performance of a digital system, so designing a clock network that minimizes both is important

In many high-speed processors, a majority of the dynamic power is dissipated in the clock network.

To reduce dynamic power, the clock network must support clock gating (shutting down (disabling the clock) units)


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Clock Distribution Factors Clock Distribution Factors Things to consider

Interconnect material used for routing clock

Shape of network

Clock drivers and buffers used

Load on clock lines

Rise and fall time of clock (may have to consider transmission line effects as well!!)

Skew specifications


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Clock Distribution TechniquesClock Distribution Techniques Balanced paths (H-treeH-tree network, matched RCmatched RC

trees) In the ideal case, can eliminate skew

Could take multiple cycles for the clock signal to propagate to the leaves of the tree

Clock grids Typically used in the final stage of the clock

distribution network

Minimizes absolute delay (not relative delay)


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ClockClock

Clock

Idlecondition

Gatedclock

Insert clock gating atInsert clock gating atmultiple levels in clock multiple levels in clock treetree

Shut off entire subtreeShut off entire subtreeif all gating conditions if all gating conditions are satisfiedare satisfied

If the paths are perfectlyperfectly balanced, clock skew is zero

H-Tree Clock NetworkH-Tree Clock Network


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DEC Alpha 21164 (EV5)DEC Alpha 21164 (EV5) 300 MHz clock (9.3 million transistors on a 16.5x18.1

mm die in 0.5 micron CMOS technology) single phase clock

3.75 nF total clock load Extensive use of dynamic logic

20 W (out of 50W) or 40% in clock distribution network

Two level clock distribution Single 6 stage driver at the center of the chip

Secondary buffers drive the left and right sides of the clock grid in m3 and m4

Total equivalent driver size of 58 cm !!


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Clock Drivers

DEC Alpha 21164DEC Alpha 21164


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Clock Skew in Alpha ProcessorClock Skew in Alpha Processor Absolute

skew smaller than 90 ps

The critical instruction and execution units all see the clock within 65 psThe critical instruction and execution units all see the clock within 65 ps


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Dealing with Clock Skew and JitterDealing with Clock Skew and Jitter To minimize skew, balance clock paths using H-treeH-tree or

matched-treematched-tree clock distribution structures.

If possible, route data and clock in opposite directions Eliminates races at the cost of performance.

The use of gated clocks to help with dynamic power consumption make jitter worse.

Shield clock wires (route power lines – VDD or GND – next to clock lines) to minimize/eliminate coupling with neighboring signal nets.


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Dealing with Clock Skew and Jitter IIDealing with Clock Skew and Jitter II Use dummy fills to reduce skew by reducing variations

in interconnect capacitances due to interlayer dielectric thickness variations.

Beware of temperature and supply rail variations and their effects on skew and jitter. Power supply noise Power supply noise fundamentally limits the performance of clock fundamentally limits the performance of clock networks.networks.

chapter 11 timing issues in digital systems boonchuay supmonchai integrated design application...

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t t plogic

t cdlogic t cdreg t

clk clk t sk t js clock

t cdlogic slide

clock generation

distributed clock

clock drivers

clock edges slide