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Chap. 8 Datapath Units:

Multiplier Design

Prof. An-Yeu Wu

Undergraduate VLSI Design Course

Updated: June 12, 2002

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Several Implementations of

Multipliers

Array Multiplier

2s Complement Array Multiplier Serial Multiplier

CSD Code

String-encoding Multiplier

Modified Booth-encoded Multiplier

Implementation (Chap. 8.2.7.2)

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6-by-6 Multiplication

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Wallace-Tree Multiplication

FA is a ones counter:Take A, B, and Cinputs and encodes

them on SUMandCARRYoutputs.

A 1-bit full adder (FA)provides a 3:2

compression in thenumber of bits.

A+B+C=2C+S

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7-bit Wallace tree addition

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Ex: 66 Wallace Multiplier

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Example

In a 32-bit multiplier, the maximum number of partial

products is 32 and the compressions are

32 22 16 12 8 6 4 3 2

=> There are 9 Full-adder (FA) delays in the array

1. c.f. Array multiplier (Booth-recoded) =16 partialproducts to be summed up.

2. Can be used together with Booth-encoding scheme

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Wallace Tree Multiplier MxNBooth-encoded multiplier (IEEE JSSC, vol.1,no.2,

June 1993)

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A typical delay distribution of the

output of Wallace tree section

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Extension

32-bits Wallace-tree multiplier has 9 FA delays in

the array

Questions:

1. For a 64-bit multiplier, what is the minimum

adder delay?

2. Is there any way to reduce the delay by other

compression scheme?

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Approach:

Using 4:2compression adder

The 4:2 compression

(really 5:3) has three

XOR delays in theSUM path.

c.f.: Four XOR delays

will be present if two

adders are used

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Referenced Paper

A 54x54 regularly structured tree multiplier: IEEE

Journal of Solid-State Circuits (vol. 27, no.9, 1992)

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Chap. 8.2.7.2: Implementation of

Booth-encoded Multiplier

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Implementation: Radix-n Multiplication

Modified Booth-recoding Values

Xi-1 Xi Xi+1 OPERATION NEG ZERO TWO

0 0 0 add0 1 1 0

0 0 1 add2 0 0 1

0 1 0 sub1 1 0 0

0 1 1 add1 0 0 0

1 0 0 sub1 1 0 0

1 0 1 add1 0 0 0

1 1 0 sub2 1 0 1

1 1 1 add0 0 1 0

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16*16 Booth Multiplier

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Array schematic

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Array Floorplaning

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First Rank Schematic

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Booth decoding Schematic

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Booth-Add-16 rank floorplan

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Adder rank schematic

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Booth gate

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Array adder layout

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Carry Propagate Adder

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Homework #6 (Cancelled)

1. Draw the schematic diagram of your design.

2. Verify your design first using C/C++ or Matlabprograms.

3. Write down the Verilog/VHDL code and performsimulation.

4. Verify your Verilog/VHDL codes. That is,check your

simulation results with the C/C++/Matlab results.5. Show your (1) Schematic (2) Source code (3) Simulation

results in your report.

6. Due date: June 28, 2002.