8/8/2019 CH6 Slides

1/43

I/0 BlockConfigurable Logic Block

Interconnect Area

Figure 6-1 Layout of Part of a Programmable Logic Cell Array

8/8/2019 CH6 Slides

2/43

Figure 6-2 Configuration Memory Cell

WRITE

DATA

Q

Q

CONFIGURATION

CONTROL

8/8/2019 CH6 Slides

3/43

M M

EDCB

DATA INDI

A

CLB OUTPUTS

X

0 (INHIBIT)

(GLOBAL RESET)

LOGICVARIABLES

QX

QY

G

F

COMBINATORIALFUNCTION

FDING

1MUX0

RD

D Q

RD

D Q

DIRECTRESET

CLOCK

ENABLE CLOCK EC

K

RD

Y

1 (ENABLE)

Figure 6-3 Xilinx 3000 Series Logic Cell

M M

FDING

1MUX0

M

M

M

M

QX

F

M

G

QY

8/8/2019 CH6 Slides

4/43

Any

Function

of 4

Variables

QX

QY F

AB

C

E

D

QX

QY G

Any

Function

of 5

Variables

F

G

QX

QY

AB

C

E

D

FG

MODE

F

MODE

AnyFunction

of 4

Variables

QX

QY

QX

QY

AB

C

E

D MUX

F

G

FGM

MODE

Any

Function

of 4

Variables

AnyFunction

of 4

Variables

Figure 6-4 Combinatorial Logic Options

8/8/2019 CH6 Slides

5/43

Figure 6-5 Flip-flops with Clock Enable

Q+ = EC D1 + EC' Q

D Q

Reset

CE

FFCLK

D1

EC

1

MUX0

RD

D Q

D1EC

CLK

8/8/2019 CH6 Slides

6/43

8/8/2019 CH6 Slides

7/43

FDING

GQY

F

E

DCB

DATA IN DI

A

CLB OUTPUTS

0 (INHIBIT)

(GLOBAL RESET)

LOGICVARIABLES

QX

QY G

F

COMBINATORIALFUNCTION

1MUX

0

RD

D Q

1MUX

0

RD

D Q

DIRECTRESET

CLOCK

ENABLE CLOCKEC

K

R D

1 (ENABLE)

ci

Ad + Su

ci+1

bi

Su

a i

FDING

QX

Figure 6-7 Signal Paths Within Adder-Subtracter Logic Cell

8/8/2019 CH6 Slides

8/43

OUTINVERT

3-STATEINVERT

OUTPUTSELECT

SLEWRATE

PASSIVEPULL UP

I/O

PAD

TTL orCMOSINPUT

THRESHOLD

(GLOBAL RESET)

CK1

CK2

CK IK

I

Q

DIRECT IN

REGISTERED IN

T

O

3-STATE

OUT

(OUTPUT ENABLE)

Vcc

OUTPUT

BUFFER

PROGRAMCONTROLLEDMULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP

D Q

R

FLIPFLOP

DQ

R

PROGRAM-CONTROLLED MEMORY CELLS

FLIPFLOP

orLATCH

Figure 6-8 Xilinx 3000 Series I/O Block

8/8/2019 CH6 Slides

9/43

CLB CLB CLB

CLB CLBCLB

SwitchMatrix

SwitchMatrix

CLB

SwitchMatrix

CLB CLB

CLB

CLB CLB CLB

CLBCLB

SwitchMatrix

SwitchMatrixSwitchMatrix

Figure 6-9

General-purpose

Interconnects

Figure 6-10

Direct Interconnects

Between Adjacent CLBs

8/8/2019 CH6 Slides

10/43

CLB CLB

CLBCLB

Switch

Matrix

Figure 6-11 Vertical and Horizontal Long Lines

8/8/2019 CH6 Slides

11/43

DA DB DC DN

Z = DAA' + D BB' + DCC' + ... + DNN'

WEAKKEEPERCIRCUIT

A B C N

V cc V cc

DA DB DC DN

Z = DADBDC...DN

Figure 6-12 Uses of Tristate Buffers

(a) Muliplexer implementation

(b) Wired-AND implementation

8/8/2019 CH6 Slides

12/43

D Q

AlternateClock Buffer

XTAL2(IN)

XTAL1

R1

R2

C1 C2Y1

Figure 6-13 Crystal Oscillator

8/8/2019 CH6 Slides

13/43

6.2 Designing with FPGAs

Sophisticated CAD tools are available to assist with the design of systems using programmablegate arrays. One method of designing a digital system with a FPGA uses the following steps:

1. Draw a block diagram of the digital system. Define condition and control signals andconstruct SM charts or state graphs which describe the required sequence of operations.

2. Write a VHDL description of the system. Simulate and debug the VHDL code, and make anynecessary corrections to the design which was developed in step 1.

3. Work out the detailed logic design of the system using gates, flip-flops, registers, counters,adders, etc.

4. Enter a logic diagram of the system into the computer using a schematic capture program.Simulate and debug the logic diagram, and make any necessary corrections to the design ofstep 3.

5. Run a partitioning program. This program will break the logic diagram into pieces which willfit into the configurable logic blocks.

6. Run an automatic place and route program. This will place the logic blocks in appropriateplaces in the FPGA and then route the interconnections between the logic blocks.

7. Run a program which will generate the bit pattern necessary to program the FPGA.

8. Download the bit pattern into the internal configuration memory cells in the FPGA and testthe operation of the FPGA.

8/8/2019 CH6 Slides

14/43

Figure 6-14 EPROM Connection for LCA Initialization

FPGA

EPROM

(containsconfigurationdata)

Address

Data

8/8/2019 CH6 Slides

15/43

From Page 213

Dice Game Controller Equations (From SM Chart of Figure 5-32)

State Assignment:

T0: AB = 00, T1: AB = 01, T2: AB = 10, T3: AB = 11

A+ = A'B' Dn_roll D711 + A'B' Dn_roll D2312 + A'B Dn_roll Eq

+ A'B Dn_roll D7 + A Reset'

B+ = A'B' Dn_roll D711' + A'B Dn_roll' + A'B Eq' + A B Reset'

Win = A B' Lose = A B En_roll = A'

Sp = A'B' Dn_roll D711' D2312'

Q+ = Q' En_roll Rb + Q Rb Roll = Q Rb Dn_roll = Q Rb'

8/8/2019 CH6 Slides

16/43

CLKCE

D

DFF

Q

RDC

CLKCE

D

DFF

Q

RDC

IPAD

SPARESWITCH

VCC

LOC=P16IBUF

IPADLOC=P14

LOC=P12

IPADCQ

CQLQ

GOSC

CLK_IN

ACLK

CLK

CLKGAME_RESETRB

LOSE

WINROLL

D7D711

D2312SPEQ

dice_contoller

ROLL

RB

RB

GAME_RESET

OPAD

LOC=P32

LOC=P33WIN

LOSE

OBUF

OBUF

OPAD

IPADLOC=P11

IBUFcomparator

EQA[3:0]

B[3:0]

Q[3:0]

D[3:0]

Q[3:0]

4bit_register

CLK

CHIP_ENABLE

CLK

D7D711D2312

SUM[3:0]

test logic

A[2:0]

B[2:0]

SUM[3:0]

full_adder3

CLK

SUM[3:0]

COUNT_1to6

COUNT[2:0]

CARRY

CLK

CHIP_ENABLE

CLKCOUNT[2:0]

COUNT_1to6

CHIP_ENABLECARRY

CLK

D2_[2:0]

D1_[2:0]

LOC=

P37

OPAD

D2_

2

OBUF

LOC=

P36

OPAD

D2_

1

OBUF

LOC=P41

OPAD

D2_

0

OBUF

LOC=

P31

OPA

D

D1_

2

OBUF

LOC=

P28

OPA

D

D1_

1

OBUF

LOC=

P29

OPAD

D1_

0

OBUF

Figure 6-15 Dice Game Block Diagram

8/8/2019 CH6 Slides

17/43

CLK

DN_ROLL

D711D2312EO

D7

GAME_RESET

VCC

DFF

D

CE

C RD

Q A

DFF

D

CE

C RD

Q B

WIN

LOSE

SP

EN_ROLL'

Figure 6-16 Dice Game Controller Module

(a) Main controller

8/8/2019 CH6 Slides

18/43

DFF

D

CE

CRD

Q

CLKVCC

EN_ROLL'

RB

ROLL_NEXT

ROLL

DN_ROLL

Figure 6-16 Dice Game Controller Module

(b) Dice roll controller

8/8/2019 CH6 Slides

19/43

COUNT0

COUNT1

COUNT2

CHIP_ENABLE

CLK

MAIN_RESET

COUNT[2:0]

CHIP_ENABLE

CARRY

DFF

D

CE

CRD

Q

DFFD

CE

CRD

Q

DFF

D

CE

CRD

Q2

Q1

Q0

Figure 6-17 Modulo-6 Counter

8/8/2019 CH6 Slides

20/43

M0 R P2 7 $ 1 N

M1RD

P2 4

HA

$ 1 N P 3 0

HB

$ 1 N L OS

$1 N81

WI N P 3 4

HD

GND $ 1N $ 1N

D2_1

P 3 8 P 3 9

HF

P 4 0 $ 1 N

HG

P 4 2 P 4 3

HH

RST

DPGM

P4 6

BCL

P2 3

U5 1 GA D1 _ 1

GC $ 1 N21

D2_2

$4 -$1 N7

GG GH

P4 7

P4 8

P2 2

P2 1 F A D1 _ 2

F C F D Q1 $ 4 -$1 N9

F G F H

U29

P4 9

P2 0

U5 5 EA $ 1 1- ROLL _

ROLL

ED Q0 $ 2 -$1 N28

EG EH

P5 0

P5 1

P1 9

VCC

P1 7 DA RB DC DD Q3 $ 2 -$1 N7

$1 N26

DH

U25

VCC

P5 3

$1 N51

P1 5 CA CB CC $ 1 N23

Q2 $ 1 N27

$1 N24

CH

P5 4

P5 5

$1 N5

U6 1 BA BB $ 1 1- $ 1N17

$1 1- $ 1N29

$1 1- A _NEX

$1 1- $ 1N23

BG BH

U21

P5 6

P1 3

$1 N6

CLK _I N

AB $ 1 1- $ 1N31

$1 1- $ 1N43

$1 1- B _NEX

AF AG AH

P5 7

P5 8

TCL

GAME_ RESE

PWRDN

P9 P8 P7 P6 P5 P4 P3 P2 GND P 6 8 P6 7 P6 6 P6 5 P6 4 P6 3 P6 2

P5 9

P6 1 CCLK

Figure 6-18 Layout and Routing for Dice Game for XC3020

8/8/2019 CH6 Slides

21/43

b

c

d

e

f

b

c

de

f

Z0

Z1

Z

a

Figure 6-19a Realization of General 6-variable Functions

Z(a,b,c,d,e,f) = a'Z(0,b,c,d,e,f) + aZ(1,b,c,d,e,f) = a'Z + aZ0 1

8/8/2019 CH6 Slides

22/43

cd

e

f

g

Y0

Y1

Y2

Y3

Z 0

a

b

Z

a

b

c

d

ef

g

c

d

e

fg

cd

e

f

g

Figure 6-19b Realization of General 7-variable Function

Z(a,b,c,d,e,f,g) = a'b'Z(0,0,c,d,e,f,g)+ a'bZ(0,1,c,d,e,f,g)+ ab'Z(1,0,c,d,e,f,g)

+ abZ(1,1,c,d,e,f,g)

= a'b'Y+ a'bY+ ab'Y+ abY

0

1

2

3

8/8/2019 CH6 Slides

23/43

1HF

GH

1

SDD Q

ECRD

YQ

S/RCONTROL

K(CLOCK)

F1

F2

F3

F4LOGICFUNCTION

OFF1-F4 F

G1

G2

G3

G4LOGICFUNCTION

OF

G1-G4G

DINF

GH

DINFGH

S/RCONTROL

SDD Q

ECRD

XQ

X

Y

C1 C2 C3 C4

ECS/RDINH1

LOGICFUNCTIONOF

F,G,

AND

H1

H

Figure 6-20 Simplified Block Diagram for 4000 Series CLB

8/8/2019 CH6 Slides

24/43

G

CARRY

G

F

CARRY

F

M1

M2

M3

M4

C IN UP COUT

H

S/RD Q

EC

S/RD Q

EC

DINHG

F

DINHG

F

H

F

G

H

C OUT CIN DOWN D IN

F4

F3

F2

F1

H1

G1

G2

G3

G4

Y

YQ

XQ

X

Figure 6-21 XC4000 Dedicated Carry Logic

8/8/2019 CH6 Slides

25/43

Ai+1

Bi+1

A iB iC i

Ci+2

S i+1

S i

Carry Logic

G Function

F Function

C i+1

Figure 6-22

Conceptual Diagram of a Typical Addition (2 Bits/CLB)

8/8/2019 CH6 Slides

26/43

A3

B3

B2A2

C3

A1

B1

B0A0

C2

OvC4

C0

hard-wiredcarries

S3

S2

CLB

CLB

CLB

CLB

S1S0

C0

Figure 6-23 Connections for a 4-bit Adder

8/8/2019 CH6 Slides

27/43

8/8/2019 CH6 Slides

28/43

MTS INV

M

INVERTOUTPUT

M INVERT

M S/R OUTSEL

M

Boundary

Scan

O - captureQ - captureO - update

M MM M

M INVERT

M S/R

M

DELAY

Input Data 1 |1

Input Data 2 |2

FLIP-FLOP/LATCH

GLOBALS/R

Vcc

PAD

SLEW

RATE

PULL

DOWNPULL

UP

EXTEST

TS - capture

TS - update

Boundary

Scan

3 - State TSTS/OE

OUTPUT

Output Data O

Output Clock OK

BoundaryScan

I - capture

I - update

Input Clock IK

INPUT

sd

D Q

rd

sd

D Q

rd

QL

Figure 6-25 4000 Series I/O Block

8/8/2019 CH6 Slides

29/43

Figure 6-26(a) Behavioral Model for XC4000 CLB

library BITLIB;use BITLIB.bit_pack.all;

entity XC4000CLB isport (MEM_BITS : in bit_vector(0 to 51);G_IN, F_IN, C_IN: in bit_vector(4 downto 1);K : in bit; Y,X : out bit; Q : out bit_vector (1 downto 0));

end XC4000CLB;

architecture behavior ofXC4000CLB isalias G_FUNC : bit_vector(0 to 15) is MEM_BITS(0 to 15);alias F_FUNC : bit_vector(0 to 15) is MEM_BITS(16 to 31);

alias H_FUNC : bit_vector(0 to 7) is MEM_BITS(32 to 39);type bv2D is array (1 downto 0) ofbit_vector(1 downto 0);constant FF_SEL : bv2D := (MEM_BITS(40 to 41),MEM_BITS(42 to 43));alias Y_SEL : bit is MEM_BITS(44); alias X_SEL : bit is MEM_BITS(45);alias EDGE_SEL: bit_vector(1 downto 0) is MEM_BITS(46 to 47);alias EC_SEL : bit_vector(1 downto 0) is MEM_BITS(48 to 49);alias SR_SEL : bit_vector(1 downto 0) is MEM_BITS(50 to 51);alias H1 : bit is C_IN(1); alias DIN : bit is C_IN(2);

alias SR : bit is C_IN(3); alias EC : bit is C_IN(4);

-- Timing spec for XC4000, Speed Grade -4constant Tiho : TIME := 6 ns; -- F/G inputs toX/Y outputs via Hconstant Tilo : TIME := 4 ns; -- F/G inputs toX/Y outputsconstant Tcko : TIME := 3 ns; -- Clock K toQ outputsconstant Trio : TIME := 7 ns; -- S/R toQ outputssignal G,F,H : bit;

8/8/2019 CH6 Slides

30/43

Figure 6-26(b) Behavioral Model for XC4000 CLB

beginG

8/8/2019 CH6 Slides

31/43

Table 6-1 Truth Tables for Gand FFunction Generators

G4 G3 G2 G1 G F4 F3 F2 F1 F

K M Q1 Q0 Q1+ St M Q1 Q0 Q0+

0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 1 1

0 0 1 0 0 0 0 1 0 1

0 0 1 1 0 0 0 1 1 0

0 1 0 0 0 0 1 0 0 0

0 1 0 1 1 0 1 0 1 0

0 1 1 0 0 0 1 1 0 1

0 1 1 1 0 0 1 1 1 0

1 0 0 0 0 1 0 0 0 1

1 0 0 1 1 1 0 0 1 1

1 0 1 0 1 1 0 1 0 1

1 0 1 1 0 1 0 1 1 0

1 1 0 0 0 1 1 0 0 1

1 1 0 1 1 1 1 0 1 0

1 1 1 0 1 1 1 1 0 1

1 1 1 1 0 1 1 1 1 0

8/8/2019 CH6 Slides

32/43

Figure 6-27 XC4000 Implementation of Multiplier Control

entity Fig_4_6 isport (St, K, M, CLK : in bit; Ad, Sh, Load, Done : out bit);

end Fig_4_6;

architecture CLBs ofFig_4_6 iscomponent XC4000CLB

port(MEM_BITS : in bit_vector(0 to 51);G_IN, F_IN, C_IN : in bit_vector(4 downto 1);K : in bit; Y,X : out bit; Q : out bit_vector (1 downto 0));

end component;

constant MEM1 : bit_vector (0 to 51) :=

"0000010001100110011000101110101000000000100100110000";constant MEM2 : bit_vector (0 to 51) :=

"0001000100010001000000001000100000000000000000110000";constant MEM3 : bit_vector (0 to 51) :=

"0000000001000100011001100010001000000000000000110000";

signal Q : bit_vector (1 downto 0);signal G_IN1,G_IN2,G_IN3,F_IN1,F_IN2,F_IN3 : bit_vector (3 downto 0);

beginG_IN1

8/8/2019 CH6 Slides

33/43

Figure 6-28 Partial State Graph

T0

T3

T1 T2

X1/Z1X2/Z2

X3/Z1

X4/Z2

One-hot state assignment for flip-flops Q0 Q1 Q2 Q3:

T0: 1000, T1: 0100, T2: 0010, T3: 0001

Q3+ = X1 Q0 + X2 Q1 + X3 Q2 + X4 Q3

Z1 = X1 Q0 + X3 Q2

Z2 = X2 Q1 + X4 Q3

8/8/2019 CH6 Slides

34/43

INPUT/GCLK

INPUT/GCLRn

INPUT/OE1

INPUT/OE2

8 to 16I/O pins

I/OControl

Block

Macrocells

1 to 8

Macrocells

9 to 16

8 to

16

LAB A

36

16

8 to 16

Macrocells

33 to 40

Macrocells

41to 48

8 to16

LAB C

36

16

8 to 16

8 to 16I/O pins

I/OControlBlock

8 to 16

I/O pins

I/O

Control

Block

8 to 16

I/O pins

I/OControlBlock

Macrocells17 to 24

Macrocells

25 to 32

8 to16

LAB B

36

16

8 to 16

Macrocells49 to 56

Macrocells57 to 64

8 to

16

LAB D

36

16

8 to 16

PIA

Figure 6-29 Altera 7000 Series Architecture

for EPM7032, 7064, and 7096 Devices

8/8/2019 CH6 Slides

35/43

Logic Array

Parallel Logic

Expanders

(from othermacrocells)

GlobalClear

GlobalClock

Product-Term

Select

Matrix

36 Signals

from PIA16 Expander

Product Terms

Shared Logic

Expanders

ClearSelect

VCC

Clock/

Enable

SelectENACLRN

PRND Q

to PIA

to I/O

Control

Block

Register

Bypass

Programmable

Register

Figure 6-30

Macrocell for EMP7032, 7064, and 7096 Devices

8/8/2019 CH6 Slides

36/43

MacrocellProduct-termLogic

Product-term Select Matrix

MacrocellProduct-term

Logic

36 Signalsfrom PIA

16 SharedExpanders

Figure 6-31 Sharable Expanders

8/8/2019 CH6 Slides

37/43

Expanders

Preset

Clock

Clear

Product-

Term

Select

Matrix

Preset

Clock

Clear

Product-

TermSelect

Matrix

36 Signalsfrom PIA

16 Shared

Macrocell

Product-term

Logic

Macrocell

Product-termLogic

from Previous

Macrocell

to Next

Macrocell

Figure 6-32 Parallel Expanders

8/8/2019 CH6 Slides

38/43

OE1nOE2n

VCC

GND

OE Control

to PIA

from Macrocell

Figure 6-33 I/O Block for EPM7032, 7064, and 7096

8/8/2019 CH6 Slides

39/43

I/O Element(IOE)

Logic ArrayBlock (LAB)

IOEIOE

IOEIOE

EmbeddedArray

Block (EAB)

Row

Interconnect

Logic Array

IOEIOE

IOEIOE

Embedded

Array

IOE

IOE

IOE

Local Interconnect

IOEIOE

IOEIOE

IOEIOE

IOEIOE

IOEIOE

IOEIOE

Logic Element (LE)

ColumnInterconnect

IOE

IOE

IOE

IOE

IOE

EAB

EAB

LogicArray

Figure 6-34 FLEX 10K Device Block Diagram

8/8/2019 CH6 Slides

40/43

Figure 6-35 FLEX 10K Logic Array Block

28

Carry-In &Cascade-In

LE1

LE8

LE2

LE3

LE4

LE5

LE6

LE7

ColumnInterconnect

Row Interconnect

LAB LocalInterconnect

Column-to-RowInterconnect

Carry-Out &Cascade-Out

16

24LAB ControlSignals

6

Dedicated Inputs &Global Signals

16

4

8

4

4

4

4

4

4

4

4

4

42 8

8/8/2019 CH6 Slides

41/43

to LAB LocalInterconnect

LABCTRL3

LABCTRL4

DATA1

DATA2

DATA3

DATA4

LABCTRL1

LABCTRL2

Carry-In

ClockSelect

Carry-Out

Look-UpTable(LUT)

Clear/PresetLogic

CarryChain

CascadeChain

Cascade-In

Cascade-Out

to FastTrackInterconnect

ProgrammableRegister

PRn

CLRn

D Q

ENA

Register Bypass

Device-WideClear

Figure 6-36 FLEX 10K Logic Element

8/8/2019 CH6 Slides

42/43

d[3..0]

LE1

LUT

d[7..4]LE2

LUT

[(4n-1)..(4n-4)]LEn

LUT

d[3..0] LUT

d[7..4] LUT

d[(4n-1)..(4n-4)] LUT

LE1

LE2

LEn

AND Cascade Chain OR Cascade Chain

Figure 6-37 Cascade Chain Operation

Figure 6 38 FLEX 10K Embedded Array Block

8/8/2019 CH6 Slides

43/43

D

D Q

Columninterconnect

Row Interconnect

RAM/ROM

256 x 8512 x 4

1,024 x 22,048 x 1

WE

Address

DataIn

8, 4, 2, 1

EAB L l I

Dedicated Inputs &Global Signals

6

D Q

D Q

D QDataOut

24

Device-WideClear

8, 9, 10, 11

2, 4, 8, 16

2, 4, 8, 16

Figure 6-38 FLEX 10K Embedded Array Block