DATA ACQUISITION SYSTEMS

(Ch2)

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• The data Acquisition system (DAS) is used to acquire physical (non electrical) or electrical data and store this data on a computer or recorder, or use it to control industrial circuits.

• Usually the collection of data is done in real time.

• The block diagram of DAS, shown in next slide: – Collects data of N channels,

– Converts them to a digital form, then

– Records them on a computer, or recorder, or

– Uses them to control an industrial circuit.

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• The Transducer converts the non-electrical (Physical) data such as Displacement, Velocity, Pressure, Temperature, Light, etc to a corresponding electrical signal.

• The output of transducers is usually in a form, which cannot be processed by the other circuits of the DAS because of their weakness, non-linearity, or noise.

• Therefore the signal conditioning circuits must be used to improve these generated signals.

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Transducers

• The term signal conditioning means to make any necessary changes on the analog input signal before applying it to the A/D converter, some of the most frequently performed types of signal conditioning are:

Buffering

Filtering

Signal level change

Signal Conversion

Linearization

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Signal–Conditioning Circuits

Buffering

• It is used to provide current capability of the output signal of the transducer by transformation of the very high output impedance of the traducer to low impedance.

• This can be simply performed using unity gain voltage amplifier, as shown in the next slide

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Filtering • It is used to reject the interference signals, power Line

interference (50Hz or 60Hz), or any other unwanted signal from the output signal of the transducer.

• Passive filters usually reduce the useful signal as they eliminate the superimposed noises (interference).

• Active filter using op-amps with gain and feedback is employed, they introduce some gain to the useful signal.

• The filter performance is expressed by its reduction ratio of the rejected signal in decibel (RdB) :

RdB = 20 log (V0 / Vi) • Where V0 and Vi are the rejected output and input

voltages of the filter respectively (see example 2-1).

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Signal level change

• The level of the output signal of the transducer may require to be amplified or attenuated.

• This process is done using of signal level change circuit, it consists of:

– Attenuator (Resistive divider), or

– Amplifier circuits

– Usually both attenuation and amplification can be performed in many electronic test instruments.

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Signal Conversion • Most of transducers changes one electrical parameter

(R,L, or C) according to its non electrical input quantity.

• This change of the electrical parameter is converted to an electrical signal (for example voltage or current) by the signal conversion circuit.

• For example the change of the thermistor resistance RT in the wheatstone bridge is converted to the voltage VAB .

• Initially the bridge is balanced (VAB = 0) with the nominal value of RT.

• When temperature changes, RT is changed, the bridge is unbalanced, and VAB is proportional to the change of RT.

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Linearization • If the Characteristics of a transducer is not linear,

then connect its output to a circuit whose Characteristics is the inverse function of the transducer Characteristics.

• That will give a linear output voltage Vout, for example if the characteristics of a transducer is exponential function (V=V0e θT) where : – V = transducer output voltage at temperature T – V0 = Transducer output voltage at reference

temperature ( 0 C ) – e = base of the natural logarithm system (2.718) . – = Constant – T = Temperature in degrees Celsius [ C ].

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• If this exponential output voltage (V) is connected to the input of an amplifier whose gain varies with its input in a logarithmic expression – Vout = K Ln V

– Where K = a calibration constant

– Vout = amplifier output voltage

– V = amplifier input voltage = transducer output voltage

– Vout = K Ln (V0e T)

– Vout = K Ln V0 + k T

• Therefore Vout is a linear function of T (although V is not linear Function of T) . – (KLnV0) is an offset voltage.

– (K) is a scale Factor,

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Transducer Output Signal

Linearised Signal (Amplifier Output)

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• It is an electronic circuit with one or more input channels, and one output channel.

• The multiplexer (Mux) is used in DAS so that only one analog-to-digital converter (A/D) is used for all input channels using time-sharing between them.

• The Mux at any time connects one of its input channels to its output channel according to its selecting inputs, which is generated by the program sequencer or driven by the control signal driver.

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Multiplexer

The number of Mux input channels (N) depends on its selecting inputs (x) by the Formula: N ≤ 2x e.g. 8-input Mux requires 3-selecting inputs (8 = 23).

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• The analog input of the A/D converter must be stable (constant) during the conversion time.

• Therefore the analog input is sampled and kept constant during the conversion time by sample and hold circuit.

• This circuit is a part of the A/D or it is a Separated circuit.

• Its block diagram and the waveforms are shown in the next slide.

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Sample and Hold circuits (S & H)

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• Amplifiers A1 & A2 interfaces the S&H to its input analog voltage (Vi) and to its output circuit (A/D)

• A sample of Vi is taken by the normally opened (NO) electronic switch S, which is controlled by the sample control pulse VS.

• When the sample control pulse is applied to the switch driver, S is closed.

• The input voltage Vi quickly charges the low leakage condenser (C).

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• This charge is maintained constant when the switch opens (time between pulses) until the next sample control pulse arrives.

• Both A1 & A2 have high input impedance and low output impedance so that they does not load their input circuit and allow high current to their output circuit.

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• Most of A/Ds uses digital–to-analog converter (D/A) to accomplish its function.

• Therefore the D/A will be explained firstly.

• The D/A converter main types are:

– Voltage summing amplifier with binary weighted resistor network, and

– R-2R ladder D/A

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Digital to Analog Converters (D/A)

Voltage-Summing Amplifier D/A

• It converts its input binary signal (V0 , V1,…., Vn-1) to a corresponding analog voltage level Vout.

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Four-bit D/A

• If : R1 = R0/2, R2 = R0/4 , R3= R0/8, ……… Rn-1 = R0 /(2n-1)

Then:

Vout = -[V0(RF/R0) + V1(RF/R1) + V2(RF/R2) + V3(RF/R3)]

= - RF/R0 (V0 + 2 V1+ 4V2 + 8 V3)

where V0 is LSB and V3 is MSB

The general form:

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• The smallest change at the output is due to the LSB changing from logic 0 to logic 1 or vice versa

• This change is called the resolution (Res) of the converter and is expressed as :

Res = Vout max / (2n – 1)

where :

oVout max is the maximum output analog voltage

on is the number of binary bits

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• The disadvantages of the summing amplifier D/A are :

(1) Several different values of precision resistors (R0, R1,.., Rn-1) are required.

(2) Each binary input sees a different load since each input resistor is different in value

• These two major disadvantages are overcome by the R-2R ladder D/A .

• See Example 2-3

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R-2R Ladder D/A

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• The R-2R ladder D/A converter is a resistive network that uses only two different values of resistance.

• A 4- bit binary input R-2R ladder network is shown below:

• The analysis of the network, by use of Thevenin’s theorem or other analytical tool, shows that:

o The resistance from any node to ground or to an input terminal is 2R

o Each binary input sees a constant load value

• The relation between the binary inputs and the analog output of the 4-bit R-2R ladder network is shown below:

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Bit (V0) LSB V1 V2 V3 MSB

Vout V0/ 16 V1/ 8 V2/ 4 V3/2

• The output value for the 4-bit R-2R ladder:

Vout = 1/16 [V0 + 2 V1 + 4 V2 + 8V3]

• The general form:

Vout = V0/2n + V 1/2n-1 + …….. + Vn-1/21

= 1/2n [20 V0 + 21 V1 + 22 V2 + …….. + 2n-1 Vn-1]

• See Example 2-5

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Analog–to–Digital Converters (A/D)

• The most frequently used A/D converters are :

– Simultaneous Method of A/D Conversion

– Ramp-Type A/D Converter

– Successive–Approximation A/D Converter

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Simultaneous Method of A/D Conversion

• The Simultaneous, Parallel, or Flash method of A/D conversion is very rapid, but it requires high number of comparators, the required number of

comparators equals to 2N -1 (where N is the number of digital output bits)

• Also its required to define 2N ranges of analog input voltage to represent N output digital bits

• The logic diagram of a 2-bit simultaneous A/D converter is shown in the next slide

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The logic diagram of a 2-bit simultaneous A/D converter

• The voltage comparator is essentially a 1-bit A/D converter, as the input signal is analog but the output behaves digitally o If the non-inverting input is greater than or equal to the

inverting input, the output will be “High”

o If the non-inverting input is less than the inverting input, the output will be “Low”

• The Reset line forces the outputs of the A/D to be zero whatever of its other inputs.

• The Read Line enables the output of A/D.

• The detailed operation is shown in next table, where The ‘X’ means don’t care state.

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Ramp-type A/D converter

• It requires only one comparator

• Its conversion time is not constant, but depends on the amplitude of its analog input.

• It takes long time to convert high amplitudes and short time to convert small amplitudes.

• The block diagram of a 4-bit ramp A/D is shown in the next slide

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Stair step Reference Voltage

0000

• The output of the comparator is high level if the analog input (Vi) is higher than the output of D/A (VDAC).

• This permits the counter to count the clock pulses generated by the clock generator during this time.

• Thus the digital output is increased and VDAC is increased consequently.

• If VDAC reaches Vi , the output of the comparator becomes zero level.

• At this time the clock pulses do not reach the input of the counter, consequently the digital output remains constant.

• The conversion sequence is shown in the next slide.

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Conversion Sequence

• It is seen that conversion time is not constant but linearly proportional to the level of the analog input Vi

• The maximum conversion time equals to 2N clock periods (2N clock period), where N is the number of digital output bits.

• The average conversion time is one-half the maximum conversion time since the staircase (VDAC) increases linearly.

• The rate of conversion at maximum conversion time(minimum conversion rate) is determined by the greatest time required for conversion and is equal to 1/(maximum conversion time) = 1/(2N clock period).

• See example 2-7

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Successive Approximation A/D Converter

• This is the most widely used A/D , because its conversion time is constant and equals to N clock periods only (where N is the number of its output digital bits).

• Also, it uses only one comparator.

• The block diagram of 4-bit successive approximation A/D is shown in the next slide.

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1 0 0 0

• At the rising edge of the first clock pulse SAR sets its MSB to 1 (its other lower weight bits = 0).

• Then the output of D/A (VDAC) is compared with the analog input (Vi).

• At the falling edge of this clock pulse, if Vi ≥ VDAC, SAR maintains MSB = 1, otherwise it resets this MSB to 0 since it will not required in the digital representation of the analog input (Vi).

• At the Second clock pulse SAR repeats the previous process for (MSB-1) instead of MSB.

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• And so on this process is repeated for each subsequent lower weight bits, one bit in one clock cycle.

• Therefore in order to convert its analog input Vi

(whatever its amplitude) to the corresponding output digital word, SAR takes number of clock cycles equals to the number of its output digital word bits.

• The conversion sequence is shown in the next slide.

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See Example 2-8

Thanks

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