ceng3420 lab3-2:lc-3bdatapathbyu/ceng3420/2019spring/slides/lab3-2.pdf · ceng3420...
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CENG3420Lab 3-2: LC-3b Datapath
Bei Yu
Department of Computer Science and EngineeringThe Chinese University of Hong Kong
Spring 2018
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Overview
Introduction
Lab3-2 Assignment
Golden Results
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Overview
Introduction
Lab3-2 Assignment
Golden Results
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The Slides are self-contained? NO!
Do please refer to following document:I LC-3b-datapath.pdfI LC-3b-ISA.pdf
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LC-3b Datapath
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ReadAddress Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
ReadData 1
ReadData 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
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LC-3b Datapath
I Five major drivers: MARMUX, PC, ALU, SHF, MDRI It is the means of data transfer between units
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LC-3b Datapath
Driver MARMUXI int inputOfGateMARMUX;
I Controlled by MARMUXI from IR[7:0] or adder (defined in
inputOfMARMUXFromAdder)I IR[7:0] is through LSHF1 (left shift 1 bit) & ZEXT
(zero extended)I Implementation of inputOfMARMUXFromAdder
has been provided
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LC-3b Datapath
Driver PCI int inputOfGatePC;
I Provided from PC
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LC-3b Datapath Driver ALUI int inputOfGateALU
I SR2MUX is controlled by IR[5:5] (refer to ANDinstruction)
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LC-3b Datapath Driver SHFI int inputOfGateSHF
I Implementation has been provided
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LC-3b Datapath
Driver MDRI DATA_SIZE: if 0 then byte base; if 1 then word base.I If byte base, should check MAR[0]
I If 0: MDR[7:0]I If 1: MDR[15:8]
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Help on GateALU
I Input 1: SR1 (please refer to Figure C.6 (b))I Input 2: SR2MUX, select the second source operand (see instructions AND XOR
NOT)
/* input of GateALU */inputOfGateALU = blockALU(
GetALUK(CURRENT_LATCHES.MICROINSTRUCTION),CURRENT_LATCHES.REGS[blockSR1MUX(GetSR1MUX(CURRENT_LATCHES.
MICROINSTRUCTION), CURRENT_LATCHES.IR)],blockSR2MUX(xxx)
);
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Overview
Introduction
Lab3-2 Assignment
Golden Results
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Lab3-2 Assignment
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Overview
Introduction
Lab3-2 Assignment
Golden Results
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Assignment Package
I lc3bsim3-2.c, lc3bsim3-2.h: codes to work onI libems3-2.a: libraryI ucode3: FSMI Makefile
I bench: folder with benchmarks
Run the simulator:
1. make, then binary “lc3bsim3-2” is generated2. ./lc3bsim3-2 ucode3 bench/toupper.cod
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Golden Results – case toupper.cod
1. run 6
Simulating for 6 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 2MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 3MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 4MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case toupper.cod (cont.)
2. rdump
Current register/bus values :-------------------------------------Cycle Count : 6PC : 0x3002IR : 0x0000STATE_NUMBER : 0x0023
BUS : 0x0000MDR : 0xe00fMAR : 0x3000CCs: N = 0 Z = 1 P = 0Registers:0: 0x00001: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case toupper.cod (cont.)
3. Go on run 1
Simulating for 1 cycles...
MemCycleCnt = 1MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case toupper.cod (cont.)
4. rdump
Current register/bus values :-------------------------------------Cycle Count : 7PC : 0x3002IR : 0xe00fSTATE_NUMBER : 0x0020
BUS : 0xe00fMDR : 0xe00fMAR : 0x3000CCs: N = 0 Z = 1 P = 0Registers:0: 0x00001: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case toupper.cod (cont.)
5. Go on run 5
Simulating for 5 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case toupper.cod (cont.)
6. rdump
Current register/bus values :-------------------------------------Cycle Count : 12PC : 0x3004IR : 0xe00fSTATE_NUMBER : 0x0021
BUS : 0x0000MDR : 0x0000MAR : 0x3002CCs: N = 0 Z = 1 P = 0Registers:0: 0x30201: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod
1. run 7
Simulating for 7 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 2MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 3MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 4MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
2. rdump
Current register/bus values :-------------------------------------Cycle Count : 7PC : 0x3002IR : 0xe005STATE_NUMBER : 0x0020
BUS : 0xe005MDR : 0xe005MAR : 0x3000CCs: N = 0 Z = 1 P = 0Registers:0: 0x00001: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
3. Go on run 2
Simulating for 2 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
4. rdump
Current register/bus values :-------------------------------------Cycle Count : 9PC : 0x3002IR : 0xe005STATE_NUMBER : 0x0012
BUS : 0x300cMDR : 0xe005MAR : 0x3000CCs: N = 0 Z = 1 P = 0Registers:0: 0x300c1: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
5. Go on run 7
Simulating for 7 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 2MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 3MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 4MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
6. rdump
Current register/bus values :-------------------------------------Cycle Count : 16PC : 0x3004IR : 0x6200STATE_NUMBER : 0x0020
BUS : 0x6200MDR : 0x6200MAR : 0x3002CCs: N = 0 Z = 1 P = 0Registers:0: 0x300c1: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
7. Go on run 7
Simulating for 7 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 2MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 3MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 4MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
8. rdump
Current register/bus values :-------------------------------------Cycle Count : 23PC : 0x3004IR : 0x6200STATE_NUMBER : 0x001b
BUS : 0x0000MDR : 0x000aMAR : 0x300cCCs: N = 0 Z = 1 P = 0Registers:0: 0x300c1: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
9. Go on run 1
Simulating for 1 cycles...
MemCycleCnt = 1MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
10. rdump
Current register/bus values :-------------------------------------Cycle Count : 24PC : 0x3004IR : 0x6200STATE_NUMBER : 0x0012
BUS : 0x000aMDR : 0x000aMAR : 0x300cCCs: N = 0 Z = 0 P = 1Registers:0: 0x300c1: 0x000a2: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
11. Go on run 1
Simulating for 1 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
12. rdump
Current register/bus values :-------------------------------------Cycle Count : 25PC : 0x3006IR : 0x6200STATE_NUMBER : 0x0021
BUS : 0x3004MDR : 0x000aMAR : 0x3004CCs: N = 0 Z = 0 P = 1Registers:0: 0x300c1: 0x000a2: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
13. Go on run 1
Simulating for 1 cycles...
MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
14. rdump
Current register/bus values :-------------------------------------Cycle Count : 26PC : 0x3006IR : 0x6200STATE_NUMBER : 0x0021
BUS : 0x0000MDR : 0x0000MAR : 0x3004CCs: N = 0 Z = 0 P = 1Registers:0: 0x300c1: 0x000a2: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
15. Go on run 4
Simulating for 4 cycles...
MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 2MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 3MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 4MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
16. rdump
Current register/bus values :-------------------------------------Cycle Count : 30PC : 0x3006IR : 0x6200STATE_NUMBER : 0x0023
BUS : 0x0000MDR : 0x127fMAR : 0x3004CCs: N = 0 Z = 0 P = 1Registers:0: 0x300c1: 0x000a2: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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Golden Results – case count10.cod (cont.)
17. Go on run 3
Simulating for 3 cycles...
MemCycleCnt = 1MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
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Golden Results – case count10.cod (cont.)
18. rdump
Current register/bus values :-------------------------------------Cycle Count : 33PC : 0x3006IR : 0x127fSTATE_NUMBER : 0x0012
BUS : 0x0009MDR : 0x127fMAR : 0x3004CCs: N = 0 Z = 0 P = 1Registers:0: 0x300c1: 0x00092: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
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