carrier board design guide - via technologies,...

1.02-06172016-151000

Carrier Board Design Guide for COM Express Modules (COM.0 R2.0)

ii

Tested To ComplyWith FCC StandardsFOR HOME OR OFFICE USE

CopyrightCopyrightCopyrightCopyright Copyright © 2011-2016 VIA Technologies Incorporated. All rights reserved.

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VIA Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.

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This equipment has been tested and found to comply with the limits for a class B digital device, pursuant to part 15 of the FCC rules.

These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a

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COM Express (COM.0 R2.0COM Express (COM.0 R2.0COM Express (COM.0 R2.0COM Express (COM.0 R2.0) Carrier Board Design Guide) Carrier Board Design Guide) Carrier Board Design Guide) Carrier Board Design Guide

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Revision History

RevisionRevisionRevisionRevision DateDateDateDate DescriptionDescriptionDescriptionDescription

0.10 8/11/2011 Initial internal draft release.

0.20 10/27/2011 Added note on section 4.3.

Updated figure 17 and figure 18 captions.

0.21 2/8/2012 Updated legal page: Copyright year.

Added HDMI registered trademark.

0.30 8/2/2013 Removed VCP interface section.

Updated pinlists table of Connector C-D.

Updated differential trace width, spacing, impedance and accumulated

trace length of PCIe in tables 4-4, 4-6, 4-9 and 4-11.

Changed PCIe rev. 1.0 and rev. 2.0 to PCIe Gen1 and Gen2 in table 4-6.

Updated differential trace width, spacing, and impedance of SATA in

table 4-48.

Updated accumulated trace length of USB 2.0 and 3.0 in tables 4-53 and

4-56.

Updated differential trace width, spacing, and impedance of USB 3.0 in

table 4-57.

Updated Note on pages 17, 24, 28, 66 and 73

Added COMe-9X90 information and COMEDB4 schematics.

Updated the naming of COME8X80 and COME8X90 to COMe-8X80 and

COMe-8X90 respectively.

Updated copyright year and disclaimer notice.

1.0 11/21/2014 Modified the design format of the whole document.

Updated Legal page.

- updated Trademarks and Copyright section

Updated section 1.2

- changed from “Acronyms and Abbreviations” to “Acronyms and

Definitions”

Updated section 3.3.2.2

- changed font color of signal names for DVP pins from blue to red

Updated Table 15

- changed the value of Accumulated Trace Length

Fixed typo errors.

Updated back cover page

- corrected Europe email address

Added document bookmarks

1.01 8/25/2015 Updated the back cover page

- removed Korea address and contact information

1.02 6/17/2016 Updated the back cover page

-removed Europe address

Updated the logo

Modified bookmarks and style settings


iv

Table of Contents

Revision HistoryRevision HistoryRevision HistoryRevision History ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ iiiiiiiiiiii

Table of ContentsTable of ContentsTable of ContentsTable of Contents ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ iviviviv

List of FiguresList of FiguresList of FiguresList of Figures ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ vivivivi

List of TablesList of TablesList of TablesList of Tables .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... viiiviiiviiiviii

1.1.1.1. IntroductionIntroductionIntroductionIntroduction ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ 1111

1.1. Document Overview......................................................................................................................... 1

1.2. Acronyms and Definitions ............................................................................................................... 2

1.3. Illustrations and Schematics ............................................................................................................ 3

2.2.2.2. General Carrier Board RecommendationsGeneral Carrier Board RecommendationsGeneral Carrier Board RecommendationsGeneral Carrier Board Recommendations ............................................................................................................................................................................................................................................................................................................................ 4444

2.1. PCB Stackup example ....................................................................................................................... 4

2.1.1. Microstrip versus Stripline designs ....................................................................................................... 4

2.2. General Layout and Routing Rules ................................................................................................ 6

2.2.1. Routing Styles and Topology ................................................................................................................. 6

2.2.2. General Trace Attribute Recommendations ....................................................................................... 7

2.2.3. General Clock Routing Considerations ................................................................................................ 7

3.3.3.3. COM Express Mechanical SpecificationCOM Express Mechanical SpecificationCOM Express Mechanical SpecificationCOM Express Mechanical Specification ............................................................................................................................................................................................................................................................................................................................................ 9999

3.1. COM Express Module Form Factors ........................................................................................... 10

3.2. Dimensions of the COM Express Connectors ........................................................................... 11

3.3. Pinout of COM Express Interface ................................................................................................. 12

3.3.1. Type 10 Pinout Connector .................................................................................................................... 12

3.3.2. Type 6 Pinout Connector ...................................................................................................................... 15

4.4.4.4. Interface Layout and Routing RecommendationsInterface Layout and Routing RecommendationsInterface Layout and Routing RecommendationsInterface Layout and Routing Recommendations .................................................................................................................................................................................................................................................................... 21212121

4.1. PCI Express x1 Interface ................................................................................................................. 21

4.1.1. PCIe x1 Signal Definition ....................................................................................................................... 21

4.1.2. PCIe x1 Reference Schematics ............................................................................................................. 22

4.2. PCI Express Graphics (PEG x4) Interface ................................................................................... 28

4.2.1. PEG x4 Signal Definition ........................................................................................................................ 28

4.2.2. PEG x4 Reference Schematics .............................................................................................................. 29

4.3. Digital Display Interface ................................................................................................................. 32

4.3.1. Digital Display Interface Signal Definition......................................................................................... 32

4.3.2. DDI Reference Schematics .................................................................................................................... 33

4.4. VGA Interface ................................................................................................................................... 37

4.4.1. VGA Signal Definition ............................................................................................................................ 37

4.4.2. VGA Reference Schematics .................................................................................................................. 37

4.5. LVDS Interface .................................................................................................................................. 40

4.5.1. LVDS Signal Definition ........................................................................................................................... 40

4.5.2. LVDS Reference Schematics ................................................................................................................. 41

4.6. Digital Video Port (DVP) Interface .............................................................................................. 45

4.6.1. DVP Signal Definition ............................................................................................................................. 45

4.6.2. DVP Reference Schematics ................................................................................................................... 46

4.6.3. Digital Video Port Layout and Routing Recommendation ............................................................. 48

4.7. Low Pin Count Interface ................................................................................................................. 50

4.7.1. LPC Signal Definition .............................................................................................................................. 50

4.7.2. LPC Reference Schematics .................................................................................................................... 50

4.8. Serial COM Interface ...................................................................................................................... 54

4.8.1. Serial COM Signal Definition ............................................................................................................... 54

4.8.2. Serial COM Reference Schematics ...................................................................................................... 54


v

4.9. General Purpose I2C Bus Interface ............................................................................................... 56

4.9.1. General Purpose I2C Signal Definition ............................................................................................... 56

4.9.2. General Purpose I²C Reference Schematics ...................................................................................... 56

4.10. PCI Interface (Type 2 Only) .......................................................................................................... 57

4.10.1. PCI Signal Definition ............................................................................................................................... 57

4.10.2. PCI Reference Schematics ..................................................................................................................... 58

4.11. IDE Interface (Type 2 Only) .......................................................................................................... 61

4.11.1. IDE Signal Definition............................................................................................................................... 61

4.11.2. IDE Reference Schematics ..................................................................................................................... 62

4.12. SATA Interface ................................................................................................................................. 67

4.12.1. SATA Signal Definition .......................................................................................................................... 67

4.12.2. SATA Reference Schematics................................................................................................................. 67

4.13. USB 2.0 and USB 3.0 Interface ...................................................................................................... 70

4.13.1. USB 2.0 and USB 3.0 Signal Definition ............................................................................................... 70

4.13.2. USB 2.0 and USB 3.0 Reference Schematics ..................................................................................... 71

4.14. Audio Interface ................................................................................................................................ 77

4.14.1. Audio Signal Definition.......................................................................................................................... 77

4.14.2. Audio Reference Schematics ................................................................................................................ 77

4.15. System Management Bus (SMBus) Interface .............................................................................. 80

4.15.1. System Management Bus Signal Definition ....................................................................................... 80

4.16. LAN Interface ................................................................................................................................... 81

4.16.1. LAN Signal Definition ............................................................................................................................. 81

4.16.2. LAN Reference Schematics ................................................................................................................... 81

4.16.3. LAN Layout and Routing Recommendations .................................................................................... 84

Appendix A. Video CombinatioAppendix A. Video CombinatioAppendix A. Video CombinatioAppendix A. Video Combinations and Display Device Supportns and Display Device Supportns and Display Device Supportns and Display Device Support........................................................................................................................................................................................ 85858585

Appendix B. COMEDB4, COMEDB2 and COMEDB1 Reference SchematicsAppendix B. COMEDB4, COMEDB2 and COMEDB1 Reference SchematicsAppendix B. COMEDB4, COMEDB2 and COMEDB1 Reference SchematicsAppendix B. COMEDB4, COMEDB2 and COMEDB1 Reference Schematics .................................................................................................... 86868686


vi

List of Figures

Figure 1: Conventions pertaining to illustration and schematics ............................................................................... 3

Figure 2: Six-layer microstrip PCB stackup example .................................................................................................... 4

Figure 3: Six-layer stripline PCB stackup example ....................................................................................................... 4

Figure 4: Point-to-point and multi-drop examples ...................................................................................................... 6

Figure 5: Daisy-chain example .......................................................................................................................................... 6

Figure 6: Alternate multi-drop example ......................................................................................................................... 6

Figure 7: Suggested clock trace spacing ......................................................................................................................... 7

Figure 8: Clock trace layout in relation to the ground plane .................................................................................... 8

Figure 9: Series termination for multiple clock loads ................................................................................................. 8

Figure 10: COM Express connector placement on Carrier Board PCB .................................................................... 9

Figure 11: COM Express Form Factors comparisons ................................................................................................. 10

Figure 12: COM Express connector dimensions ........................................................................................................ 11

Figure 13: Orientation of COM Express connectors on a COM Express module ............................................. 11

Figure 14: PCI Express Clock Buffer .............................................................................................................................. 22

Figure 15: PCI Express x1 Mode Slot ............................................................................................................................ 22

Figure 16: PCI Express x1 Mode Topology Example ................................................................................................ 23

Figure 17: Mini PCI Express Card Socket ..................................................................................................................... 25

Figure 18: Mini PCI Express x1 Mode Topology Example....................................................................................... 25

Figure 19: PCI Express (x1 mode) Trace Spacing ...................................................................................................... 26

Figure 20: PEG x4 Slot (PE16) Example ....................................................................................................................... 29

Figure 21: PEG x4 Topology Example ......................................................................................................................... 30

Figure 22: PEG x4 Trace Spacing ................................................................................................................................... 31

Figure 23: DDI Interface Implementation Example ................................................................................................... 33

Figure 24: HDMI® Interface Connector Diagram ........................................................................................................ 34

Figure 25: DisplayPort Interface Connector Diagram ................................................................................................ 34

Figure 26: VGA Interface Connector Example ........................................................................................................... 37

Figure 27: VGA Interface Sample Diagram .................................................................................................................. 38

Figure 28: Recommended RGB Trace Properties ....................................................................................................... 39

Figure 29: LVDS Connector Example ........................................................................................................................... 41

Figure 30: LVDS Panel Power ......................................................................................................................................... 41

Figure 31: LVDS Backlight ............................................................................................................................................... 42

Figure 32: LVDS Interface Sample Diagram ................................................................................................................ 42

Figure 33: DVP Slot Example ......................................................................................................................................... 46

Figure 34: DVP Slot Interface Diagram ......................................................................................................................... 46

Figure 35: Digital TV-out Interface using External TV Encoder Implementation ............................................... 47

Figure 36: Digital Panel Interface using External DVI Transmitter Implementation ........................................... 47

Figure 37: TTL Panel Interface using External TTL Panel Implementation ........................................................... 48

Figure 38: LPC Flash ROM Interface .............................................................................................................................. 50

Figure 39: LPC Super I/O Example ................................................................................................................................ 51

Figure 40: LPC COM Interfaces ...................................................................................................................................... 51

Figure 41: LPC Topology Example ................................................................................................................................ 52

Figure 42: Serial COM port Interface Example .......................................................................................................... 54

Figure 43: Serial COM port Interface Topology Example ....................................................................................... 54

Figure 44: EEPROM Circuitry Reference Example ...................................................................................................... 56

Figure 45: PCI Connector Example ............................................................................................................................... 58

Figure 46: PCI Interface Topology Example ............................................................................................................... 59

Figure 47: IDE Connector ................................................................................................................................................ 62

Figure 48: CF Card Socket ............................................................................................................................................... 62

Figure 49: IDE Devices Layout Guidelines ................................................................................................................... 63

Figure 50: IDE Cable Detection with 40-Conductor Ribbon Cable ...................................................................... 64

Figure 51: IDE Cable Detection with 80-Conductor Ribbon Cable ...................................................................... 65

Figure 52: SATA Connectors .......................................................................................................................................... 67

Figure 53: SATA Trace Spacing ...................................................................................................................................... 68

Figure 54: USB 2.0 (port 0 and port 1) Interface ....................................................................................................... 71

Figure 55: USB 3.0 (port 0 and port 1) Interface ....................................................................................................... 72

Figure 56: USB 2.0 Differential Signal Layout Recommendations .......................................................................... 73


vii

Figure 57: USB 3.0 Differential Signal Layout Recommendations .......................................................................... 73

Figure 58: USB Differential Signal Routing Example ................................................................................................. 73

Figure 59: USB 2.0 and 3.0 Trace Spacing ................................................................................................................... 74

Figure 60: HD Audio Codec Implementation Example ........................................................................................... 77

Figure 61: Single On-Board High Definition Audio Codec Implementation Example ..................................... 78

Figure 62: Fully On-Board High Definition Audio Codec Implementation Example ........................................ 78

Figure 63: SMBus Interface Example ............................................................................................................................. 80

Figure 64: LAN Implementation Example ................................................................................................................... 81

Figure 65: 10/100 Ethernet Layout Recommendation (integrated magnetic module) ...................................... 82

Figure 66: 10/100 Ethernet Layout Recommendation (external magnetic module) .......................................... 82

Figure 67: Gigabit Ethernet Layout Recommendations (integrated magnetic module) .................................... 83

Figure 68: Gigabit Ethernet Layout Recommendations (external magnetic module) ....................................... 83


viii

List of Tables

Table 1: Acronyms and Definitions .................................................................................................................................. 2

Table 2: General Six layer microstrip PCB stackup ...................................................................................................... 5

Table 3: PCB Stack-Up Detail ............................................................................................................................................ 5

Table 4: Recommended Trace Width and Spacing ..................................................................................................... 7

Table 5: Four x1 Lane PCI Express Signal Descriptions ........................................................................................... 21

Table 6: PCI Express Signal Groups PE1 to PE4 slot ................................................................................................ 23

Table 7: Mini-PCI Express socket pinout definition ................................................................................................... 25

Table 8: PCI Express Trace Properties .......................................................................................................................... 26

Table 9: PCI Express Interface Routing Topology and Signal Type ...................................................................... 26

Table 10: PCI Express Interface Layout Guidelines ................................................................................................... 27

Table 11: PEG x4 Signal Descriptions .......................................................................................................................... 28

Table 12: PEG x4 Signal Group ..................................................................................................................................... 30

Table 13: PEG x4 Interface Trace Properties .............................................................................................................. 31

Table 14: PEG x4 Interface Routing Topology and Signal Type ............................................................................ 31

Table 15: PEG x4 Interface Layout Guidelines ........................................................................................................... 31

Table 16: Digital Display Interface Signal Descriptions ........................................................................................... 33

Table 17: DDI Interface Termination Option and Routing Topology ................................................................... 35

Table 18: DDI Interface Trace Properties .................................................................................................................... 35

Table 19: DDI Interface Layout Guidelines ................................................................................................................. 36

Table 20: VGA Signal Descriptions .............................................................................................................................. 37

Table 21: VGA Interface Trace Properties ................................................................................................................... 39

Table 22: VGA Interface Termination Option and Routing Topology ................................................................. 39

Table 23: VGA Interface Layout Guidelines ............................................................................................................... 39

Table 24: LVDS Signal Descriptions ............................................................................................................................. 40

Table 25: LVDS Interface Termination Option and Routing Topology ................................................................ 43

Table 26: LVDS Interface Trace Properties ................................................................................................................. 43

Table 27: LVDS Interface Layout Guidelines .............................................................................................................. 44

Table 28: DVP Signal Descriptions ............................................................................................................................... 45

Table 29: DVP Interface Termination Option and Routing Topology .................................................................. 48

Table 30: DVP Interface Trace Properties ................................................................................................................... 49

Table 31: DVP Interface Layout Guidelines ................................................................................................................ 49

Table 32: LPC Signal Descriptions ................................................................................................................................ 50

Table 33: LPC Interface Topology, Signal Type and Layout Guidelines .............................................................. 52

Table 34: LPC Interface Trace Properties .................................................................................................................... 53

Table 35: Serial COM Signal Descriptions .................................................................................................................. 54

Table 36: Serial COM Interface Topology, Signal Type and Layout Guidelines................................................ 55

Table 37: Serial COM Interface Trace Properties ...................................................................................................... 55

Table 38: General Purpose I2C Signal Descriptions .................................................................................................. 56

Table 39: General Purpose I2C Interface Topology, Signal Type and Layout Guidelines ................................ 56

Table 40: General Purpose I2C Interface Trace Properties ...................................................................................... 56

Table 41: PCI Signal Descriptions ................................................................................................................................. 58

Table 42: PCI slot connection ........................................................................................................................................ 59

Table 43: PCI Interface Routing Requirements ........................................................................................................... 60

Table 44: PCI Interface Layout Guidelines .................................................................................................................. 60

Table 45: PCI Interface Trace Properties ..................................................................................................................... 60

Table 46: IDE Signal Descriptions ................................................................................................................................. 61

Table 47: IDE Supporting Modes, Transfer Rate and Cable Type ......................................................................... 64

Table 48: IDE Interface Signal Type and Routing Topology ................................................................................... 65

Table 49: IDE Interface Trace Properties ..................................................................................................................... 65

Table 50: IDE Interface Layout Guidelines .................................................................................................................. 66

Table 51: SATA Signal Descriptions ............................................................................................................................. 67

Table 52: SATA Trace Properties .................................................................................................................................. 68

Table 53: SATA Routing, Topology and Layout Guidelines ................................................................................... 69

Table 54: USB 2.0 Signal Descriptions ......................................................................................................................... 70

Table 55: USB 3.0 Signal Descriptions ......................................................................................................................... 71

Table 56: USB 2.0 Interface Routing Topology and Signal Type ........................................................................... 74


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Table 57: USB 2.0 Interface Layout Guidelines .......................................................................................................... 74

Table 58: USB 2.0 Trace Properties .............................................................................................................................. 75

Table 59: USB 3.0 Interface Routing Topology and Signal Type ........................................................................... 75

Table 60: USB 3.0 Interface Layout Guidelines .......................................................................................................... 75

Table 61: USB 3.0 Trace Properties .............................................................................................................................. 76

Table 62: Audio Interface Signal Descriptions ........................................................................................................... 77

Table 63: Trace Properties for Audio Interface .......................................................................................................... 79

Table 64: Topology and Layout Guidelines for Audio Interface ........................................................................... 79

Table 65: SMBus Interface Signal Descriptions .......................................................................................................... 80

Table 66: Trace Properties for SMBus Interface ......................................................................................................... 80

Table 67: Topology and Layout Guidelines for SMBus Interface .......................................................................... 80

Table 68: LAN Signal Descriptions ............................................................................................................................... 81

Table 69: Trace Properties for LAN Interface ............................................................................................................. 84

Table 70: Topology and Layout Routing Guidelines for LAN Interface ............................................................... 84


1

1.1.1.1. IntroductionIntroductionIntroductionIntroduction This document provides layout and routing design guidelines to developers of COM Express carrier

boards that support the features of VIA COMe-8X80, COMe-8X90 and COMe-9X90 COM Express

modules. This guideline provides all the major underlying interfaces related to COM.0 R2.0. While, there

are a total of seven different Type of COM Express defined in the COM.0 R2.0, this document discusses

only Type 10, Type 2 and Type 6 implementations

This document is not intended to be a specification. All information in the document is believed to be

accurate as of the publication date. However, no guarantees are given regarding the accuracy of this

document.

1.1. Document Overview A brief description of each chapter is given below.

Chapter 1: Chapter 1: Chapter 1: Chapter 1: IntroductionIntroductionIntroductionIntroduction Chapter 1 briefly introduces the structure of the design guide document.

Chapter 2: Chapter 2: Chapter 2: Chapter 2: General carrier board recommendationsGeneral carrier board recommendationsGeneral carrier board recommendationsGeneral carrier board recommendations

General design schemes and recommended layout rules are shown in chapter 2. This chapter contains

board descriptions and general layout and routing guidelines for a COM Express Carrier Board. These

design recommendations should be used when designing a system.

Chapter 3: Chapter 3: Chapter 3: Chapter 3: COM Express Mechanical SpecificationCOM Express Mechanical SpecificationCOM Express Mechanical SpecificationCOM Express Mechanical Specification Detailed information about the COM Express connector placement and dimensions are described in

chapter 3.

Chapter 4: Chapter 4: Chapter 4: Chapter 4: Interface layout and routing recommendations Interface layout and routing recommendations Interface layout and routing recommendations Interface layout and routing recommendations Detailed layout and routing guidelines for each interface are described in chapter 4.

Appendix A: Appendix A: Appendix A: Appendix A: VVVVideo combinations and display device supportideo combinations and display device supportideo combinations and display device supportideo combinations and display device support Appendix A contains the combination of video and display device support using COM.0 R1.0 module.

Appendix B: Appendix B: Appendix B: Appendix B: COMEDB4, COMEDB2 and COMEDB1 reference schematicsCOMEDB4, COMEDB2 and COMEDB1 reference schematicsCOMEDB4, COMEDB2 and COMEDB1 reference schematicsCOMEDB4, COMEDB2 and COMEDB1 reference schematics Appendix B contains the schematics for the carrier board reference design. These schematics (COMEDB4,

COMEDB2 and COMEDB1) can be used as one example on how to design a COM Express carrier board

that provides optimal performance when used with VIA COM Express COMe-9X90 module (COM.0 R2.0),

COMe-8X90 module (COM.0 R2.0) and COMe-8X80 module (COM.0 R1.0). The reference designs are

only for reference and not to be copied.


2

1.2. Acronyms and Definitions

TermTermTermTerm DescriptionDescriptionDescriptionDescription

AC’97 Audio Codec ‘97

CF card CompactFlash card

DMA Direct Memory Access

DAC Digital Analog Converter

DDC Display Data Channel

DDI Digital Display Interface

DVI Digital Visual Interface

DVP Digital Video Port

EEPROM Electrically Erasable Programmable Read-Only Memory

EMI Electromagnetic Interference

GBE Gigabit Ethernet

HDA High Definition Audio

HDMI High-Definition Multimedia Interface

I2C Inter-Integrated Circuit

IDE Integrated Drive Electronics

IEEE Institute of Electrical and Electronics Engineers

LAN Local Area Network

LCD Liquid Crystal Display

LPC Low Pin Count

LVDS Low-Voltage Differential Signaling

NC No Connection

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCIe Peripheral Component Interconnect Express

PEGx4 PCI Express Graphics x4 Lane

RGB Red, Green and Blue analog signals

RJ-45 Registered Jack-45

ROM Read-Only Memory

SATA Serial Advanced Technology Attachment

SMBus System Management Bus

TTL Transistor-Transistor Logic

USB Universal Serial Bus

VGA Video Graphics Array

Table Table Table Table 1111: : : : Acronyms and DefinitionsAcronyms and DefinitionsAcronyms and DefinitionsAcronyms and Definitions


3

1.3. Illustrations and Schematics Illustrations and schematics depicted in this document may show the directional flow of signals.

Directional flow is indicated by the pointed ends of the polygonal shapes. See Figure 1.

Figure Figure Figure Figure 1111: : : : Conventions pertaining to illustration and schematicsConventions pertaining to illustration and schematicsConventions pertaining to illustration and schematicsConventions pertaining to illustration and schematics


4

2.2.2.2. General Carrier Board RecommendationsGeneral Carrier Board RecommendationsGeneral Carrier Board RecommendationsGeneral Carrier Board Recommendations This section contains general guidelines for the printed circuit board (PCB) stackup and the layout of

traces. General guidelines for routing style, topology, and trace attribute recommendations are also

discussed.

2.1. PCB Stackup example Figure 2 illustrates an example of a PCB with a six-layer stackup. The stackup consists of three signal layers

and three reference (power and ground) layers. The three signal layers are referred to as the component

layer, inner layer and solder layer. The example below also shows the PCB stackup in a microstrip design.

Figure Figure Figure Figure 2222: : : : SixSixSixSix----layer milayer milayer milayer microstrip PCB stackup examplecrostrip PCB stackup examplecrostrip PCB stackup examplecrostrip PCB stackup example

2.1.1. Microstrip versus Stripline designs Carrier board designers can choose between two basic categories of PCB design: microstrip and stripline.

Microstrip designs have the outer signal layers exposed. Stripline designs have the outermost signal layers

shielded by reference layers.

Figure Figure Figure Figure 3333: : : : SixSixSixSix----layer stripline PCB stackup examplelayer stripline PCB stackup examplelayer stripline PCB stackup examplelayer stripline PCB stackup example

The choice of microstrip or stripline design depends on the application for which the carrier board is

being designed. If the carrier board is being designed for locations where sensitivity to electromagnetic

interference (EMI) is an issue, a stripline design is recommended for reducing EMI and noise coupling. For

applications where the tolerance for EMI levels is greater, a microstrip design is recommended to reduce

costs. Due to the inherent nature of stripline PCB stacks, broad-side coupling is possible.


5

Layer DescriptionLayer DescriptionLayer DescriptionLayer Description Thickness ValueThickness ValueThickness ValueThickness Value Spacing (mil)Spacing (mil)Spacing (mil)Spacing (mil)

Component Layer 0.5 oz. Copper + Planting

~62 mil

Prepeg 2.4 ~3.5 mil thickness

Ground Layer 1.0 oz. Copper


Inner Layer ~52.3 mil thickness


Power Layer 1.0 oz. Copper


Ground Layer 1.0 oz. Copper

Prepeg 2.4 ~ 3.5 mil thickness

Solder Layer 0.5 oz. Copper + Planting

Table Table Table Table 2222: : : : General Six layer microstrip PCB stackupGeneral Six layer microstrip PCB stackupGeneral Six layer microstrip PCB stackupGeneral Six layer microstrip PCB stackup

DescriptionDescriptionDescriptionDescription ValueValueValueValue NotesNotesNotesNotes

Dielectric constant (Ɛr) of Prepeg 3.6 ~ 4.2 @ 1 GHz

Board Impedance 55Ω ± 10% For all signal layers

Table Table Table Table 3333: : : : PCB StackPCB StackPCB StackPCB Stack----Up DetailUp DetailUp DetailUp Detail

NoteNoteNoteNotessss::::

1. It is not recommended to have any signal routings on either power layer or the ground layer. If a signal must

be routed on the power layer, then it should be routed as short as possible.

2. Signal routing on the ground layer is not allowed.

3. Lower trace impedance providing better signal quality is preferred over higher trace impedance for clock

signals.


6

2.2. General Layout and Routing Rules This section provides general layout rules and routing guidelines for designing COM Express Carrier

Boards.

2.2.1. Routing Styles and Topology Topology is the physical connectivity of a net or a group of nets. There are two types of topologies for a

motherboard layout: point-to-point and multi-drop. An example of these topologies is shown in Figure 4.

ASIC

Multi-Drop

Point-to-Point

ASIC

or

Connector

ASIC

ASIC

or

Connector

Figure Figure Figure Figure 4444: : : : PointPointPointPoint----totototo----point and multipoint and multipoint and multipoint and multi----drop examplesdrop examplesdrop examplesdrop examples

High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising

edge caused by the high impedance of the output buffer in the high state. In order to maintain better

signal quality, transmission stubs should be kept as short as possible (less than 1.5”). Therefore, daisy

chain style routing is strongly recommended for these signals. Figure 5 below shows an example of daisy

chain routing.

trace segment

ASIC

or

Connector

ASIC

ASIC

or

Connector

ASIC

short stub

Figure Figure Figure Figure 5555: : : : DaisyDaisyDaisyDaisy----chain examplechain examplechain examplechain example

If daisy chain routing is not allowed in some circumstances, different routings may be considered. An

alternative topology is shown in Figure 6. In this case, the branch point is somewhere between both ends.

It may be near the source or near the loads. Being close to the load side is best. The separated traces

should be equal in length.

equal length

ASIC

or

Connector

ASIC

ASIC

or

Connector

somewhere

in the middle

Figure Figure Figure Figure 6666: : : : Alternate multiAlternate multiAlternate multiAlternate multi----drop exampledrop exampledrop exampledrop example


7

2.2.2. General Trace Attribute Recommendations A 5 mil trace width and 10 mil spacing are generally advised for most signal traces on a COM Express

carrier board layout. To reduce trace inductance the minimum power trace width is recommended to be

30 mil.

As a quick reference, the overall recommended trace width and spacing for different trace types are listed

in Table 4, and the recommended trace width and spacing for each signal group is shown in Chapter 4.

Trace TypeTrace TypeTrace TypeTrace Type Trace Width (mil)Trace Width (mil)Trace Width (mil)Trace Width (mil) Spacing (mil)Spacing (mil)Spacing (mil)Spacing (mil)

Regular Signal 5 or wider 10 or wider

Interface or Bus Reference Voltage Signal 20 or wider 20 or wider

Power 30 or wider 20 or wider

Table Table Table Table 4444: : : : Recommended Trace Width and SpacingRecommended Trace Width and SpacingRecommended Trace Width and SpacingRecommended Trace Width and Spacing

General rules for minimizing crosstalk in high-speed bus designs are listed below:

Maximize the distance between traces. Maintain 10 mil minimum spaces between traces wherever

possible.

Maximize the distance (30 mil minimum) between two adjacent routing areas of different signal

groups wherever possible.

Avoid parallelism between traces on adjacent layers.

Select a board stack-up that minimizes coupling between adjacent traces.

2.2.3. General Clock Routing Considerations Clock routing guidelines are listed below:

The recommended clock trace width is 5 mil.

The minimum space between one clock trace and adjacent clock traces is 20 mil. The minimum

space from one segment of a clock trace to other segments of the same clock trace is at least two

times of the clock width. That is, more space is needed from one clock trace to others or its own

trace to avoid signal coupling (see Figure 7).

Clock traces should be parallel to their reference ground planes. That is, a clock trace should be

right beneath or on top of its reference ground plane (see Figure 8).

Series terminations (damping resistors) are needed for all clock signals (typically 0 Ω to 47 Ω).

When two loads are driven by one clock signal, the series termination layout is shown in Figure 9.

When multiple loads (more than two) are applied, a clock buffer solution is preferred.

Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels

(typically 20 mil to 50 mil wide) is preferred.

No clock traces on the internal layer if a six-layer board is used.

clock

segment

clock

synthesizer

clock trace

20 mil

at least two times

of the width of the

clock segment

FigureFigureFigureFigure 7777: : : : Suggested clock trace spacingSuggested clock trace spacingSuggested clock trace spacingSuggested clock trace spacing


8

another ground plane

clock trace

relative ground plane

Recommended

another ground plane

clock trace

relative ground plane

NOT recommended

Figure Figure Figure Figure 8888: : : : Clock trace layout in relation to the ground planeClock trace layout in relation to the ground planeClock trace layout in relation to the ground planeClock trace layout in relation to the ground plane

in equal length

clock source

damping resistors

in equal length

clock load

clock load

Figure Figure Figure Figure 9999: : : : Series termination for multiple clock loadsSeries termination for multiple clock loadsSeries termination for multiple clock loadsSeries termination for multiple clock loads


9

3.3.3.3. COM Express MecCOM Express MecCOM Express MecCOM Express Mechanical Specificationhanical Specificationhanical Specificationhanical Specification Carrier boards for VIA COM Express modules must follow the placement defined in the COM Express

specification. Figure 10 is a depiction of the top view of a carrier board PCB with an appropriate amount

of space reserved for the COM Express module. The placement of the COM Express connectors must be

exact to ensure that COM Express modules can be properly fitted.

To increase the thermal performance, a buffer of 5 mm around the perimeter of the area designated for

the COM Express module is recommended as a keepout zone.

Figure Figure Figure Figure 10101010: : : : COM Express connector placement on Carrier Board PCBCOM Express connector placement on Carrier Board PCBCOM Express connector placement on Carrier Board PCBCOM Express connector placement on Carrier Board PCB


10

3.1. COM Express Module Form Factors The VIA COM Express Module specifies three different types of form factors are shown below.

Compact module:Compact module:Compact module:Compact module: 95 mm x 95 mm

Basic module:Basic module:Basic module:Basic module: 95 mm x 125 mm

Extended module:Extended module:Extended module:Extended module: 110 mm x 155 mm

Figure Figure Figure Figure 11111111: : : : COM Express Form Factors comparisonsCOM Express Form Factors comparisonsCOM Express Form Factors comparisonsCOM Express Form Factors comparisons


11

3.2. Dimensions of the COM Express Connectors The COM Express connectors comprises of up to two 220-pin connectors. Each connector is said to have

two rows.

3.3±0.05

1.65±0.05

ø0.9±0.15

0.3±0.03

0.5 pitch

ø1.5±0.15

57.7±0.05

54.5

59.5±0.05

1.75

3.6±0.05

1.75

Pin A1/C1 on receptacle

Pin B1/D1 on plug

Pin B1/D1 on receptacle

Pin A1/C1 on plug

(units are in mm)

Figure Figure Figure Figure 12121212: : : : COM Express connector dimensionsCOM Express connector dimensionsCOM Express connector dimensionsCOM Express connector dimensions

The connectors on the bottom of the COM Express module should have the rows in the reverse order of

the rows on the carrier board. Figure 13 shows an example of how the rows should be oriented on the

COM Express module.

Figure Figure Figure Figure 13131313: : : : Orientation of COM Express connectors on a COM ExpreOrientation of COM Express connectors on a COM ExpreOrientation of COM Express connectors on a COM ExpreOrientation of COM Express connectors on a COM Express moduless moduless moduless module


12

3.3. Pinout of COM Express Interface The pinout tables show the pinout of the COM Express interface as implemented in VIA COM Express

modules. The pinout table in section 3.3.1.1 is intended for Type 10 only while the pinout table in section

3.3.2.1 is meant for Type 6 and Type 2.

3.3.1. Type 10 Pinout Connector

3.3.1.1.3.3.1.1.3.3.1.1.3.3.1.1. Connector AConnector AConnector AConnector A----BBBB

PinPinPinPin Pinout Name (Row A)Pinout Name (Row A)Pinout Name (Row A)Pinout Name (Row A) PinPinPinPin Pinout Name (Row B)Pinout Name (Row B)Pinout Name (Row B)Pinout Name (Row B)

A1 GND (FIXED) B1 GND (FIXED)

A2 GBE0_MDI3- B2 GBE0_ACT#

A3 GBE0_MDI3+ B3 LPC_FRAME#

A4 GBE0_LINK100# B4 LPC_AD0


A6 GBE0_MDI2- B6 LPC_AD2

A7 GBE0_MDI2+ B7 LPC_AD3

A8 NC B8 LPC_DRQ0#

A9 GBE0_MDI1- B9 LPC_DRQ1#

A10 GBE0_MDI1+ B10 LPC_CLK


A12 GBE0_MDI0- B12 PWRBTN#

A13 GBE0_MDI0+ B13 SMB_CK

A14 GBE0_CTREF B14 SMB_DAT

A15 SUS_S3# B15 SMB_ALERT#

A16 SATA0_TX+ B16 SATA1_TX+

A17 SATA0_TX- B17 SATA1_TX-

A18 SUS_S4# B18 NC

A19 SATA0_RX+ B19 SATA1_RX+

A20 SATA0_RX- B20 SATA1_RX-


A22 RSVD B22 RSVD

A23 RSVD B23 RSVD

A24 SUS_S5# B24 PWR_OK

A25 RSVD B25 RSVD

A26 RSVD B26 RSVD

A27 BATLOW# B27 WDT

A28 (S)ATA_ACT# B28 AC/HAD_SDIN2

A29 AC/HDA_SYNC B29 AC/HAD_SDIN1

A30 AC/HDA_RST# B30 AC/HAD_SDIN0


A32 AC/HDA_BITCLK B32 SPKR

A33 AC/HDA_SDOUT B33 I2C_CK

A34 -BIOS_DIS0 B34 I2C_DAT

A35 THRMTRIP# B35 THRM#

A36 USB6- B36 USB7-

A37 USB6+ B37 USB7+

A38 USB_6_7_OC# B38 USB_4_5_OC#

A39 USB4- B39 USB5-

A40 USB4+ B40 USB5+


A42 USB2- B42 USB3-

A43 USB2+ B43 USB3+

A44 USB_2_3_OC# B44 USB_0_1_OC#

A45 USB0- B45 USB1-

A46 USB0+ B46 USB1+

A47 VCC_RTC B47 EXCD1_PERST#


13

A48 EXCD0_PERST# B48 NC

A49 NC B49 SYS_RESET#

A50 LPC_SERIRQ B50 CB_RESET#


A52 RSVD B52 RSVD

A53 RSVD B53 RSVD

A54 GPI0 B54 GPO1

A55 RSVD B55 RSVD

A56 RSVD B56 RSVD

A57 GND B57 GPO2

A58 PCIE_TX3+ B58 PCIE_RX3+

A59 PCIE_TX3- B59 PCIE_RX3-




A63 GPI1 B63 GPO3



A66 GND B66 WAKE0#

A67 GPI2 B67 WAKE1#




A71 LVDS_A0+ B71 DDI0_PAIR0+

A72 LVDS_A0- B72 DDI0_PAIR0-





A77 LVDS_VDD_EN B77 DDI0_PAIR4+

A78 LVDS_A3+ B78 DDI0_PAIR4-

A79 LVDS_A3- B79 LVDS_BKLT_EN


A81 LVDS_A_CK+ B81 DDI0_PAIR3+

A82 LVDS_A_CK- B82 DDI0_PAIR3-

A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL

A84 LVDS_I2C_DAT B84 VCC_5V_SBY

A85 GPI3 B85 VCC_5V_SBY

A86 RSVD B86 VCC_5V_SBY

A87 RSVD B87 VCC_5V_SBY

A88 PCIE_CK_REF+ B88 BIOS_DIS1#

A89 PCIE_CK_REF- B89 DDI0_HPD


A91 SPI_POWER B91 DDI0_PAIR5+

A92 SPI_MISO B92 DDI0_PAIR5-

A93 GPO0 B93 DDI0_PAIR6+

A94 SPI_CLK B94 DDI0_PAIR6-

A95 SPI_MOSI B95 DDI0_DDC_AUX_SEL

A96 NC B96 RSVD

A97 NC B97 SPI_CS#

A98 SER0_TX B98 DDI0_CTRLCLK_AUX+

A99 SER0_RX B99 DDI0_CTRLCLK_AUX+


A101 SER1_TX B101 FAN_PWNOUT

A102 SER1_RX B102 FAN_TACHIN

A103 NC B103 NC

A104 VCC_12V B104 VCC_12V


14








15

3.3.2. Type 6 Pinout Connector The signal names in gray indicate signals that are relevant to Type 2.

3.3.2.1.3.3.2.1.3.3.2.1.3.3.2.1. Connector AConnector AConnector AConnector A----BBBB

PinPinPinPin Pinout Name (Row A)Pinout Name (Row A)Pinout Name (Row A)Pinout Name (Row A) PinPinPinPin Pinout Name (Row B)Pinout Name (Row B)Pinout Name (Row B)Pinout Name (Row B)


A2 GBE0_MDI3- B2 GBE0_ACT#

A3 GBE0_MDI3+ B3 LPC_FRAME#



A6 GBE0_MDI2- B6 LPC_AD2

A7 GBE0_MDI2+ B7 LPC_AD3

A8 NC B8 LPC_DRQ0#

A9 GBE0_MDI1- B9 LPC_DRQ1#

A10 GBE0_MDI1+ B10 LPC_CLK


A12 GBE0_MDI0- B12 PWRBTN#

A13 GBE0_MDI0+ B13 SMB_CK

A14 GBE0_CTREF B14 SMB_DAT

A15 SUS_S3# B15 SMB_ALERT#

A16 SATA0_TX+ B16 SATA1_TX+

A17 SATA0_TX- B17 SATA1_TX-

A18 SUS_S4# / NC B18 NC

A19 SATA0_RX+ B19 SATA1_RX+

A20 SATA0_RX- B20 SATA1_RX-


A22 NC / SATA2_TX+ B22 NC / SATA3_TX+

A23 NC / SATA2_TX- B23 NC / SATA3_TX-

A24 SUS_S5# B24 PWR_OK

A25 NC / SATA2_RX+ B25 NC / SATA3_RX+

A26 NC / SATA2_RX- B26 NC / SATA3_RX-

A27 BATLOW# / NC B27 WDT

A28 (S)ATA_ACT# / ATA_ACT# B28 AC/HAD_SDIN2 / NC

A29 AC/HDA_SYNC / AC_SYNC B29 AC/HAD_SDIN1 / NC

A30 AC/HDA_RST# / AC_RST# B30 AC/HAD_SDIN0 / AC_SDIN0


A32 AC/HDA_BITCLK / AC_BITCLK B32 SPKR

A33 AC/HDA_SDOUT / AC_SDOUT B33 I2C_CK

A34 -BIOS_DIS0 B34 I2C_DAT

A35 THRMTRIP# / NC B35 THRM# / NC

A36 USB6- / NC B36 USB7- / NC

A37 USB6+ / NC B37 USB7+ / NC

A38 USB_6_7_OC# / NC B38 USB_4_5_OC#

A39 USB4- B39 USB5-

A40 USB4+ B40 USB5+


A42 USB2- B42 USB3-

A43 USB2+ B43 USB3+

A44 USB_2_3_OC# B44 USB_0_1_OC#

A45 USB0- B45 USB1-

A46 USB0+ B46 USB1+

A47 VCC_RTC B47 EXCD1_PERST#

A48 EXCD0_PERST# B48 NC

A49 NC B49 SYS_RESET#

A50 LPC_SERIRQ B50 CB_RESET#


16


A52 NC B52 NC

A53 NC B53 NC

A54 GPI0 B54 GPO1

A55 NC B55 NC

A56 NC B56 NC

A57 GND B57 GPO2

A58 NC B58 NC

A59 NC B59 NC


A61 NC B61 NC

A62 NC B62 NC

A63 GPI1 B63 GPO3



A66 GND B66 WAKE0#

A67 GPI2 B67 WAKE1#




A71 LVDS_A0+ B71 NC / LVDS_B0+

A72 LVDS_A0- B72 NC / LVDS_B0-





A77 LVDS_VDD_EN B77 NC / LVDS_B3+

A78 LVDS_A3+ B78 NC / LVDS_B3-

A79 LVDS_A3- B79 LVDS_BKLT_EN


A81 LVDS_A_CK+ B81 NC / LVDS_B_CK+

A82 LVDS_A_CK- B82 NC / LVDS_B_CK-

A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL

A84 LVDS_I2C_DAT B84 VCC_5V_SBY

A85 GPI3 B85 VCC_5V_SBY

A86 RSVD / KBD_RST# B86 VCC_5V_SBY

A87 RSVD / KBD_A20GATE B87 VCC_5V_SBY

A88 PCIE_CK_REF+ B88 BIOS_DIS1#

A89 PCIE_CK_REF- B89 VGA_RED


A91 SPI_POWER / SPI_VCC B91 VGA_GRN

A92 SPI_MISO / SPI_DI B92 VGA_BLU

A93 GPO0 B93 VGA_HSYNC

A94 SPI_CLK B94 VGA_VSYNC

A95 SPI_MOSI / SPI_DO B95 VGA_I2C_CK

A96 NC / GND B96 VGA_I2C_DAT

A97 NC B97 SPI_CS# / -SPI_SS0

A98 SER0_TX / RSVD B98 RSVD

A99 SER0_RX / RSVD B99 RSVD


A101 SER1_TX / RSVD B101 FAN_PWNOUT / RSVD

A102 SER1_RX / RSVD B102 FAN_TACHIN / RSVD

A103 NC / RSVD B103 NC / RSVD






17





18

3.3.2.2.3.3.2.2.3.3.2.2.3.3.2.2. Connector CConnector CConnector CConnector C----DDDD

The signal names in red are meant for DVP pins which are defined and proprietary of VIA Technologies.

PinPinPinPin Pinout Name (Row C)Pinout Name (Row C)Pinout Name (Row C)Pinout Name (Row C) PinPinPinPin Pinout Name (Row D)Pinout Name (Row D)Pinout Name (Row D)Pinout Name (Row D)

C1 GND (FIXED) D1 GND (FIXED)

C2 GND / IDE_D7 D2 GND / IDE_D5

C3 USB_SSRX0- / IDE_D6 D3 USB_SSTX0- / IDE_D10

C4 USB_SSRX0+ / IDE_D3 D4 USB_SSTX0+ / IDE_D11

C5 GND / IDE_D15 D5 GND / IDE_D12

C6 USB_SSRX1- / IDE_D8 D6 USB_SSTX1- / IDE_D4

C7 USB_SSRX1+ / IDE_D9 D7 USB_SSTX1+ / IDE_D0

C8 GND / IDE_D2 D8 GND / IDE_REQ

C9 USB_SSRX2- / IDE_D13 D9 USB_SSTX2- / IDE_IOW#

C10 USB_SSRX2+ / IDE_D1 D10 USB_SSTX2+ / IDE_ACK#


C12 USB_SSRX3- / IDE_D14 D12 USB_SSTX3- / IDE_IRQ

C13 USB_SSRX3+ / IDE_IORDY D13 USB_SSTX3+ / IDE_A0

C14 GND / IDE_IOR# D14 GND / IDE_A1

C15 NC / PCI_PME# D15 NC / IDE_A2

C16 NC / PCI_GNT2# D16 NC / IDE_CS1#

C17 RSVD / PCI_REQ2# D17 RSVD / IDE_CS3#

C18 RSVD / PCI_GNT1# D18 RSVD / IDE_RESET#

C19 NC / PCI_REQ1# D19 NC / PCI_GNT3#

C20 NC / PCI_GNT0# D20 NC / IDE_REQ3#


C22 NC / PCI_REQ0# D22 NC / PCI_AD1

C23 NC / PCI RESET# D23 NC / PCI_AD3

C24 NC / PCI_AD0 D24 RSVD / PCI_AD5

C25 NC / PCI_AD2 D25 RSVD / PCI_AD7

C26 NC / PCI_AD4 D26 NC / PCI_C/BE0#

C27 RSVD / PCI_AD6 D27 NC / PCI_AD9

C28 RSVD / PCI_AD8 D28 RSVD / PCI_AD11

C29 NC / PCI_AD10 D29 NC / PCI_AD13

C30 NC / PCI_AD12 D30 NC / PCI_AD15


C32 DDI2_CTRLCLK_AUX+ / PCI_AD14 D32 NC / PCI_PAR

C33 DDI2_CTRLDATA_AUX- / PCI_C/BE1# D33 NC / PCI_SERR#

C34 DDI2_DDC_AUX_SEL / PCI_PERR# D34 NC / PCI_STOP#

C35 RSVD / NC D35 RSVD / PCI_TRDY#

C36 DDI3_CTRLCLK_AUX+ / PCI_DEVSEL# D36 NC / PCI_FRAME#

C37 DDI3_CTRLDATA_AUX- / PCI_IRDY# D37 NC / AD16

C38 NC / PCI_C/BE2# D38 RSVD / PCI_AD18

C39 DDI3_PAIR0+ / PCI_AD17 D39 DDI2_PAIR0+ / PCI_AD20

C40 DDI3_PAIR0- / PCI_AD19 D40 DDI2_PAIR0- / AD22


C42 DDI3_PAIR1+ / PCI_AD21 D42 DDI2_PAIR1+ / PCI_AD24

C43 DDI3_PAIR1- / PCI_AD23 D43 DDI2_PAIR1- / PCI_AD26

C44 DDI3_HPD / PCI_C/BE3# D44 DDI2_HPD / PCI_AD28

C45 RSVD / PCI_AD25 D45 RSVD / PCI_AD30

C46 DDI3_PAIR2+ / PCI_AD27 D46 DDI2_PAIR2+ / PCI_IRQC#

C47 DDI3_PAIR2- / PCI_AD29 D47 DDI2_PAIR2- / PCI_IRQD#

C48 RSVD / PCI_AD31 D48 RSVD / NC

C49 DDI3_PAIR3+ / PCI_IRQA# D49 DDI2_PAIR3+ / NC

C50 DDI3_PAIR3- / PCI_IRQB# D50 DDI2_PAIR3- / PCI_CLK



19

C52 PEG_RX0+ D52 PEG_TX0+

C53 PEG_RX0- D53 PEG_TX0-

C54 NC D54 NC



C57 NC D57 TYPE2#






C63 RSVD D63 RSVD

C64 RSVD D64 RSVD

C65 NC D65 NC

C66 NC D66 NC

C67 RSVD D67 GND

C68 NC D68 NC

C69 NC D69 NC


C71 NC D71 NC

C72 NC D72 NC

C73 GND / NC D73 GND / NC

C74 NC D74 NC

C75 NC D75 NC

C76 GND D76 GND

C77 RSVD D77 IDE_CBLID#

C78 DVP1_D0 D78 DVP1_D1





C83 RSVD D83 RSVD

C84 GND D84 GND



C87 GND D87 GND




C91 DVP1_DE D91 DVP1_TVCLKR

C92 DVP1_VS D92 NC

C93 GND D93 GND

C94 DVP1_HS D94 DVP1_CLK

C95 DVP1_TVFLD D95 NC

C96 GND D96 GND

C97 RSVD D97 RSVD / DVP1_DET

C98 DVP1_SPD D98 DVP1_VDD_EN

C99 DVP1_SPCLK D99 DVP1_BKLT_EN


C101 NC D101 BLT_CK

C102 NC D102 NC

C103 GND D103 GND

C104 VCC_12V D104 VCC_12V






20



Notes:Notes:Notes:Notes:

1. The DVP is VIA’s defined interface and not specified in the COM Express standard specification.

2. The VIA COMe-9X90 COM Express module does not support DVP interface.


21

4.4.4.4. Interface Layout and RoutingInterface Layout and RoutingInterface Layout and RoutingInterface Layout and Routing

RecommendationsRecommendationsRecommendationsRecommendations The information presented in this chapter includes the signal descriptions, reference schematic examples,

topology examples, and detailed layout and routing guidelines for each bus interface. The information

provided is intended for designing COM Express carrier boards that are compliant with VIA COM Express

modules.

4.1. PCI Express x1 Interface VIA COM Express (COM.0 R2.0) modules can support up to four PCI Express lanes. The four lanes can be

grouped into four x1 mode configurations. Each of these modes consists of two differential signal pairs:

the receive data pair and the transmit data pair.

This section will help the developer to create a robust PCI Express x1 interface design on the carrier

board. However, the carrier board designer should do an appropriate analysis and simulation to verify that

the design fulfills PCI Express specification requirements.

4.1.1. PCIe x1 Signal Definition The general purpose PCI Express interfaces are defined by the PICMG COM Express specification on

connector A-B.

Signal NameSignal NameSignal NameSignal Name Pin #Pin #Pin #Pin # I/OI/OI/OI/O DescriptionDescriptionDescriptionDescription TypeTypeTypeType

PCIE_RX0+ B68 I Receive input differential pair. Channel 0

10, 6 and 2 PCIE_RX0- B69

PCIE_TX0+ A68 O Transmit output differential pair. Channel 0

PCIE_TX0- A69


10, 6 and 2 PCIE_RX1- B65


PCIE_TX1- A65


10 PCIE_RX2- B62


PCIE_TX2- A62


10 PCIE_RX3- B59


PCIE_TX3- A59

PCIE_CK_REF+ A88 O PCIe and PEG lanes reference Clock 10, 6 and 2

PCIE_CK_REF- A89

EXCD0_PERST# A48 O PCIe Card0: Reset, Active Low 10, 6 and 2

EXCD1_PERST# B47 I PCIe Card1: Reset, Active Low 10, 6 and 2

CB_RESET# B50 O Reset output from Module to Carrier Board 10, 6 and 2

WAKE0# B66 I PCIe wake up signal 10, 6 and 2

PCI_RESET# C23 O PCI reset output 2

Table Table Table Table 5555: : : : Four x1 Lane PCI Express Signal DescriptionsFour x1 Lane PCI Express Signal DescriptionsFour x1 Lane PCI Express Signal DescriptionsFour x1 Lane PCI Express Signal Descriptions


22

4.1.2. PCIe x1 Reference Schematics

SRC_IN-SRC_IN

SDATASCLK

IREF

OE_0OE_1OE_2OE_3OE_4OE_5OE_6OE_7

-HIGH_BW

OE_INV

-BYPASS

-SRC_DIV-SRC_STOP

+3.3VCLK_BF

-CLK_PD

PECLK0+PECLK0-

PECLK1+PECLK1-

PECLK2+PECLK2-

PECLK3+PECLK3-

PECLK4+PECLK4-

PEX8604_CLK+

PEX8604_CLK-

PCIE_CLK1-PCIE_CLK1+




PCIE_CLK_REF+PCIE_CLK_REF-

SMB_CLKSMB_DA

-PEREQ_1

+3.3V

+3.3V

PCIe Clock Buffer

TO PE1 SLOT

TO PE2 SLOT

TO Mini PCIe

TO PEX8604

TO PE3 SLOT

R226 22R226 22

TP_CKG_LOCKTP_CKG_LOCK1R261 0R261 0

R582 10KR582 10K

C2250.1uFC2250.1uF

R221 0R221 0

R251 22R251 22

C23010uFC23010uF

R576 10KR576 10K

R231 22R231 22

R573 10KR573 10K

C2450.1uFC2450.1uF

R579 10KR579 10K

R225 22R225 22

R581 10KR581 10K

U32

ICS9DB801BGLF

U32

ICS9DB801BGLF

SCLK23

SDATA24

VDD12

VDD211

VDD319

GNDA47

VDD539

SRC_IN4

DIF_08

DIF_0#9

DIF_112

DIF_1#13

DIF_216

DIF_2#17

DIF_320

DIF_3#21

DIF_430

DIF_4#29

DIF_534

DIF_5#33

SRC_IN#5

GND210

GND318

GND425

GND532

VDDA48

GND13

VDD431

DIF_638

DIF_6#37

DIF_742

DIF_7#41

OE_06

OE_114

OE_215

OE_37

OE_443

OE_535

OE_636

OE_744

OE_INV40

SRC_DIV#1

BYPASS#/PLL22

SRC_STOP#27

PD#26

HIGH_BW#28

IREF46

LOCK45

R255 475_1%R255 475_1%

C2230.1uFC2230.1uF

C2370.1uFC2370.1uF

R247 22R247 22

R256 0R256 0

FB35 AA-600Y03102FB35 AA-600Y03102

R234 22R234 22

R575 10KR575 10K

R236 22R236 22C2380.1uFC2380.1uF

R242 22R242 22

R578 10KR578 10K

R230 22R230 22

R222 0R222 0

R262 0R262 0

+

CE331000uF/10V

+

CE331000uF/10V

12

R240 22R240 22R580 10KR580 10K

PEX8604_CLK-

PCIE_CLK1+

PCIE_CLK1-

PCIE_CLK4+

PCIE_CLK4-

PCIE_CLK5+

PCIE_CLK5-

PCIE_CLK6+

PCIE_CLK6-

PEX8604_CLK+

meet Zdif=49.9 ohm

R237 49.9_1%R237 49.9_1%

R241 49.9_1%R241 49.9_1%

R235 49.9_1%R235 49.9_1%

R252 49.9_1%R252 49.9_1%

R232 49.9_1%R232 49.9_1%

R227 49.9_1%R227 49.9_1%

R248 49.9_1%R248 49.9_1%

R229 49.9_1%R229 49.9_1%

R224 49.9_1%R224 49.9_1%

R243 49.9_1%R243 49.9_1%

+3.3V

OE_INV

-HIGH_BW

-BYPASS

-SRC_DIV

-SRC_STOP

-CLK_PD

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

R572 10K/XR572 10K/X

R567 10K/XR567 10K/X

R246 10KR246 10K

R570 10K/XR570 10K/X

R250 10K/XR250 10K/X

R574 10KR574 10K

R568 10KR568 10K

R259 10K/XR259 10K/X

R571 10KR571 10K

R254 10KR254 10K

R577 10K/XR577 10K/X

R569 10KR569 10K

Figure Figure Figure Figure 14141414: : : : PCI Express Clock BufferPCI Express Clock BufferPCI Express Clock BufferPCI Express Clock Buffer

-PE1PRT2_2

-PE_RST1-PE_WAKE

SMB_DATSMB_CLK

-PE1PRT2_2

PCIE_TX1+

PCIE_RX1+

PCIE_CLK1-

PCIE_RX1-

PCIE_TX1-

PCIE_CLK1+

+12V_VCC

+3.3V

+3.3V

+3.3VSUS

+12V_VCC+12V_VCC

+3.3V

+3.3V

+3.3VSUS

C308 0.1uFC308 0.1uF

+CE47 470uF/16V+CE47 470uF/16V1 2+CE49 100uF+CE49 100uF1 2

C309 0.1uFC309 0.1uFR305 2.2KR305 2.2K

Mechanical Key

PCI_Express_x1

End of the x1 Connector

PE1

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE1

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1#A1

+12V3A2

+12V4A3

GNDA4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3V2A9

+3.3V3A10

PERST#A11

GNDA12

REFCLK+A13

REFCLK-A14

GNDA15

PERP0A16

PERN0A17

GNDA18

+CE48 100uF+CE48 100uF1 2

C310 0.1uFC310 0.1uF

Figure Figure Figure Figure 15151515: : : : PCI Express x1 Mode SlotPCI Express x1 Mode SlotPCI Express x1 Mode SlotPCI Express x1 Mode Slot


23

4.1.2.1.4.1.2.1.4.1.2.1.4.1.2.1. PCIe x1 Interface TopologyPCIe x1 Interface TopologyPCIe x1 Interface TopologyPCIe x1 Interface Topology

Each PCI Express slot (PE1 to PE4) contains one signal group that represents the PCI Express x1 mode.

These signal groups are listed in Table 6, and grouped in the example below. The PCI Express signal has a

point-to-point topology.

Figure Figure Figure Figure 16161616: : : : PCI Express PCI Express PCI Express PCI Express x1 Mode Topology Examplex1 Mode Topology Examplex1 Mode Topology Examplex1 Mode Topology Example

Signal Signal Signal Signal GGGGrouprouprouproupssss Signal NameSignal NameSignal NameSignal Name

PE1 slot (1-Lane) Lane 0

PCIE_RX0+

PCIE_RX0-

PCIE_TX0+

PCIE_TX0-


PCIE_RX1+

PCIE_RX1-

PCIE_TX1+

PCIE_TX1-


PCIE_RX2+

PCIE_RX2-

PCIE_TX2+

PCIE_TX2-


PCIE_RX3+

PCIE_RX3-

PCIE_TX3+

PCIE_TX3-

Table Table Table Table 6666: : : : PCI Express Signal Groups PE1 to PE4 slotPCI Express Signal Groups PE1 to PE4 slotPCI Express Signal Groups PE1 to PE4 slotPCI Express Signal Groups PE1 to PE4 slot


24

4.1.2.2.4.1.2.2.4.1.2.2.4.1.2.2. Mini PCI Express socketMini PCI Express socketMini PCI Express socketMini PCI Express socket

The Mini PCI Express socket is a 52-pin socket that is designed for modular PCI Express Mini Cards.

Applying the Mini PCIe socket enables the COM Express carrier board to have a flexible upgrade path.

The Mini PCI Express socket consists of a single PCIe x1 lane and single USB 2.0 channel wherein the PCI

Express Mini Card host can use either (PCIe x1 or USB 2.0 link) interfaces.

SignalSignalSignalSignal Pin #Pin #Pin #Pin # DescriptionDescriptionDescriptionDescription TypeTypeTypeType

WAKE# 1 Request to return to full operation and respond to PCIe

10, 6 and 2

+3.3VAUX 2 Primary source voltage, 3.3V

NC 3 No Connection

GND 4 Ground

NC 5 No Connection

+1.5V 6 Secondary source voltage, 1.5V

CLKREQ# 7 Clock request signal

UIM_PWR 8 User Identity Modules power source

GND 9 Ground

UIM_DATA 10 Data signal for User Identity Module

REFCLK- 11 Negative reference clock differential pair

UIM_CLK 12 Clock signal for User Identity Module

REFCLK+ 13 Positive reference clock differential pair

UIM_RESET 14 Reset signal for User Identity Module

GND 15 Ground

UIM_VPP 16 Variable supply voltage for User Identity Module

RSVD 17 Reserved

GND 18 Ground

RSVD 19 Reserved

W_DISABLE# 20 Used to disable radio operation on add-in cards

GND 21 Ground

PERST# 22 PCI Express reset

PERn0 23 Receiver differential pair negative signal, Lane 0

3.3VAUX 24 Auxiliary voltage source, 3.3V

PERp0 25 Receiver differential pair positive signal, Lane 0

GND 26 Ground

GND 27 Ground


GND 29 Ground

SMB_CLK 30 SMBus clock

PETn0 31 Transmit differential pair negative signal, Lane 0

SMB_DATA 32 SMBus data

PETp0 33 Transmit differential pair positive signal, Lane 0

GND 34 Ground

GND 35 Ground

USB_D- 36 USB data interface differential pair, negative signal

GND 37 Ground

USB_D+ 38 USB data interface differential pair, positive signal


GND 40 Ground


LED_WWAN# 42 LED status indicator signal

GND 43 Ground

LED_WLAN# 44 LED status indicator signal

RSVD 45 Reserved

LED_WPAN# 46 LED status indicator signal

RSVD 47 Reserved


RSVD 49 Reserved


25

GND 50 Ground

10, 6 and 2 RSVD 51 Reserved


Table Table Table Table 7777: : : : MiniMiniMiniMini----PCI Express socket pinout definitionPCI Express socket pinout definitionPCI Express socket pinout definitionPCI Express socket pinout definition

USB_ME_T6+USB_ME_T6-

-CLKR

-PE_RST0

SMB_CLKSMB_DAT

PCIE_RX5-PCIE_RX5+

PCIE_TX5-PCIE_TX5+


-PE_WAKE

-PEREQ_1

-W_DISABLE

+1.5V

+3.3VSUS

+3.3VSUS

+3.3VSUS

+1.5V

+3.3VSUS

TP6TP61

TP4TP41

TP7TP71

TP3TP31

MINICARD CONNMINICARD CONN

Mini 0BA68B

+3.3VAUX52

GND50

+1.5V48

LED_WPAN#46

LED_WLAN#44

LED_WWAN#42

GND40

USB_D+38

USB_D-36

GND34

SMB_DATA32

SMB_CLK30

+1.5V28

GND26

+3.3VAUX24

PERST#22

W_DISABLE#20

GND18

UIM_VPP16

UIM_RESET14

UIM_CLK12

UIM_DATA10

UIM_PWR8

+1.5V6

GND4

+3.3VAUX2

WAKE#1

Reserved51

Reserved49

Reserved47

Reserved45

GND43

+3.3VAUX41

+3.3VAUX39

GND37

GND35

PETp033

PETn031

GND29

GND27

PERp025

PERn023

GND21

Reserved(UIM_C4)19

Reserved(UIM_C8)17

GND15

REFCLK+13

REFCLK-11

GND9

CLKREQ#7

COEX25

COEX13

G1

G2

M1

M2

TP5TP51C313 4.7uFC313 4.7uF

C315 0.1uFC315 0.1uF

C312 4.7uFC312 4.7uF

C314 0.1uFC314 0.1uF

C311 4.7uFC311 4.7uF

C316 0.1uFC316 0.1uF

D35

RB751V-40/X

D35

RB751V-40/X

A K

Figure Figure Figure Figure 17171717: : : : Mini PCIMini PCIMini PCIMini PCI Express Card SocketExpress Card SocketExpress Card SocketExpress Card Socket

Figure Figure Figure Figure 18181818: : : : Mini PCI Express x1 Mode Topology ExampleMini PCI Express x1 Mode Topology ExampleMini PCI Express x1 Mode Topology ExampleMini PCI Express x1 Mode Topology Example


26

4.1.2.3.4.1.2.3.4.1.2.3.4.1.2.3. PCIe x1 Mode Layout and Routing RecommendationsPCIe x1 Mode Layout and Routing RecommendationsPCIe x1 Mode Layout and Routing RecommendationsPCIe x1 Mode Layout and Routing Recommendations

All the PCI Express signals should be referenced to the ground plane at all times.

Each trace of differential pairs should route to parallel to each other with the same trace length.

The spacing between differential pairs must be equal at all times (in parallel), even during trace

bending and serpentine topology.

Differential pairs must be routed on the same layer with maximum of one signal layer change

allowed. The differential pairs must always move to the same layer with the same reference plane.

Transmit differential pairs are recommended to be routed on the top layer and receive differential

pairs are recommended to be routed on the bottom layer.

Do not route PCI Express traces under magnetic devices or IC’s, oscillators and clock synthesizers.

To minimize signal crosstalk, wider spacing is recommended wherever possible between traces.

It is always best to reduce the line mismatch to add to the timing margin. In other words, a balanced

topology can match the trace lengths within the groups to minimize skew.

Figure Figure Figure Figure 19191919: : : : PCI Express (x1 mode) Trace SpacingPCI Express (x1 mode) Trace SpacingPCI Express (x1 mode) Trace SpacingPCI Express (x1 mode) Trace Spacing

SignaSignaSignaSignal Groupl Groupl Groupl Group Trace & SpacingTrace & SpacingTrace & SpacingTrace & Spacing

(S : W : S1 : W : S)(S : W : S1 : W : S)(S : W : S1 : W : S)(S : W : S1 : W : S)

DifferentialDifferentialDifferentialDifferential

Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance

Spacing toSpacing toSpacing toSpacing to

Other SignalsOther SignalsOther SignalsOther Signals

PE1 Receive

20 : 5 : 5 : 5 : 20

Differential 85Ω ± 10% 20 mil

Transmit

PE2 Receive

Transmit

PE3 Receive

Transmit

PE4 Receive

Transmit

Table Table Table Table 8888: : : : PCI Express Trace PropertiesPCI Express Trace PropertiesPCI Express Trace PropertiesPCI Express Trace Properties

Signal GroupSignal GroupSignal GroupSignal Group Routing TopologyRouting TopologyRouting TopologyRouting Topology Signal TypeSignal TypeSignal TypeSignal Type NoteNoteNoteNote

PE1 Receive

Point to Point

Source

Synchronous I/O

Signals

Do not cross power

plane division line

Transmit

PE2 Receive

Transmit

PE3 Receive

Transmit

PE4 Receive

Transmit

Table Table Table Table 9999: : : : PCI Express Interface Routing Topology and SPCI Express Interface Routing Topology and SPCI Express Interface Routing Topology and SPCI Express Interface Routing Topology and Signal Typeignal Typeignal Typeignal Type


27

Signal GroupSignal GroupSignal GroupSignal Group Routing LayerRouting LayerRouting LayerRouting Layer AccumulatedAccumulatedAccumulatedAccumulated

Trace LengthTrace LengthTrace LengthTrace Length

Differential Trace Differential Trace Differential Trace Differential Trace

Length MismatchLength MismatchLength MismatchLength Mismatch

PE1

Top or Bottom < 8” (for PCIe Gen1)

< 5” (for PCIe Gen2) < 0.005”

PE2

PE3

PE4

Table Table Table Table 10101010: : : : PCI Express Interface LayoPCI Express Interface LayoPCI Express Interface LayoPCI Express Interface Layout Guidelinesut Guidelinesut Guidelinesut Guidelines

Note:Note:Note:Note:

The PCIe Gen1 and PCIe Gen2 mode trace length in VIA COM Express module is approximately 3″, therefore

the PCIe Gen1 and PCIe Gen2 mode trace length in the carrier board should not be longer than 5″ and 2”

respectively.


28

4.2. PCI Express Graphics (PEG x4) Interface This section describes the layout and routing guidelines that ensure a robust PEG x4 interface design. The

PCI Express Graphics interface is defined by the PICMG COM Express specification on connector C-D. The

VIA COM Express modules (specifically the Type 6 and Type 2) can support one PCI Express Graphics

(PEG) x4 lane.

4.2.1. PEG x4 Signal Definition The PEG x4 lane uses differential signaling on each lane (consisting of a receive data and transmit data

signal pair) that results in a high-bandwidth interface. The PEG x4 lane signals on VIA COM Express

modules (COM.0 R2.0) are intended for handling an external video graphics card. However, if the PEG x4

lane signal is not used for an external video graphics interface, it can be used by other PCI Express

devices.


PEG_RX0+ C52 I Receive input differential pair. Channel 0

6 and 2 PEG_RX0- C53 I Receive input differential pair. Channel 0

PEG_TX0+ D52 O Transmit input differential pair. Channel 0

PEG_TX0- D53 O Transmit input differential pair. Channel 0













PCIE_CK_REF+ A88 O PCI Express reference clock, positive signal 10, 6 and 2

PCIE_CK_REF- A89 O PCI Express reference clock, negative signal

Table Table Table Table 11111111: : : : PEG x4 Signal DescriptionsPEG x4 Signal DescriptionsPEG x4 Signal DescriptionsPEG x4 Signal Descriptions


29

4.2.2. PEG x4 Reference Schematics

PSN2_1

PSN2_2

PEG_TX0+PEG_TX0-

PEG_TX1+PEG_TX1-

PEG_TX2+PEG_TX2-

PEG_TX3+PEG_TX3-

PEG_RX0+PEG_RX0-

PEG_RX1+PEG_RX1-

PEG_RX2+PEG_RX2-

PEG_RX3+PEG_RX3-

SMB_CLKSMB_DAT

-PE_WAKE

PCIE_CLK6+PCIE_CLK6-

-PE_RST0

+3.3V

+12V_VCC

+3.3VSUS

+3.3V

+3.3V

+12V_VCC+12V_VCC

+3.3V +3.3V

+3.3VSUS

+3.3V

+3.3V

Close PCI Express x16 Slot

C246 0.1uFC246 0.1uF

R265 0R265 0

R270 2.2KR270 2.2K

Mechanical Key

PCI_Express_x16









+12VB1

+12VB2

+12VB3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#1B17

GNDB18

PRSNT1#A1

+12VA2

+12VA3

GNDA4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3VA9

+3.3VA10

PERST#A11

GNDA12

REFCLK+A13

REFCLK-A14

GNDA15

PERP0A16

PERN0A17

GNDA18

PETP1B19

PETN1B20

GNDB21

GNDB22

PETP2B23

PETN2B24

GNDB25

GNDB26

PETP3B27

PETN3B28

GNDB29

RSVD3B30

PRSNT2#2B31

GNDB32

RSVD5A19

GNDA20

PERP1A21

PERN1A22

GNDA23

GNDA24

PERP2A25

PERN2A26

GNDA27

GNDA28

PERP3A29

PERN3A30

GNDA31

RSVD6A32

PETP4B33

PETN4B34

GNDB35

GNDB36

PETP5B37

PETN5B38

GNDB39

GNDB40

PETP6B41

PETN6B42

GNDB43

GNDB44

PETP7B45

PETN7B46

GNDB47

PRSNT2#3B48

GNDB49

RSVD7A33

GNDA34

PERP4A35

PERN4A36

GNDA37

GNDA38

PERP5A39

PERN5A40

GNDA41

GNDA42

PERP6A43

PERN6A44

GNDA45

GNDA46

PERP7A47

PERN7A48

GNDA49

PETP8B50

PETN8B51

GNDB52

GNDB53

PETP9B54

PETN9B55

GNDB56

GNDB57

PETP10B58

PETN10B59

GNDB60

GNDB61

PETP11B62

PETN11B63

GNDB64

GNDB65

PETP12B66

PETN12B67

GNDB68

GNDB69

PETP13B70

PETN13B71

GNDB72

GNDB73

PETP14B74

PETN14B75

GNDB76

GNDB77

PETP15B78

PETN15B79

GNDB80

PRSNT2#4B81

RSVD4B82

RSVD8A50

GNDA51

PERP8A52

PERN8A53

GNDA54

GNDA55

PERP9A56

PERN9A57

GNDA58

GNDA59

PERP10A60

PERN10A61

GNDA62

GNDA63

PERP11A64

PERN11A65

GNDA66

GNDA67

PERP12A68

PERN12A69

GNDA70

GNDA71

PERP13A72

PERN13A73

GNDA74

GNDA75

PERP14A76

PERN14A77

GNDA78

GNDA79

PERP15A80

PERN15A81

GNDA82

+CE41 100uF+CE41 100uF1 2

R268 0R268 0

+CE40 100uF+CE40 100uF1 2

+CE39 470uF/16V+CE39 470uF/16V1 2

R2664.7KR2664.7K

R264 4.7KR264 4.7K

+CE38 470uF/16V+CE38 470uF/16V1 2

R271 2.2KR271 2.2K

R269 4.7KR269 4.7K

C248 0.1uFC248 0.1uF

R2674.7KR2674.7K

+CE50 100uF+CE50 100uF1 2

C247 0.1uFC247 0.1uF

Figure Figure Figure Figure 20202020: : : : PEG x4 Slot (PE16) ExamplePEG x4 Slot (PE16) ExamplePEG x4 Slot (PE16) ExamplePEG x4 Slot (PE16) Example


30

4.2.2.1.4.2.2.1.4.2.2.1.4.2.2.1. PEG x4 Interface TopologyPEG x4 Interface TopologyPEG x4 Interface TopologyPEG x4 Interface Topology

The PE16 slot contains signal groups that represent 4-lane PCI Express (PEG x4) interfaces. These signal

groups are listed in Table 12.

Figure Figure Figure Figure 21212121: : : : PEG x4 Topology ExamplePEG x4 Topology ExamplePEG x4 Topology ExamplePEG x4 Topology Example

Signal GroupsSignal GroupsSignal GroupsSignal Groups PEG x4 Signal NamePEG x4 Signal NamePEG x4 Signal NamePEG x4 Signal Name

PE16 slot (4-Lane)

Lane 0

PEG_RX0+

PEG_RX0-

PEG_TX0+

PEG_TX0-

Lane 1

PEG_RX1+

PEG_RX1-

PEG_TX1+

PEG_TX1-

Lane 2

PEG_RX2+

PEG_RX2-

PEG_TX2+

PEG_TX2-

Lane 3

PEG_RX3+

PEG_RX3-

PEG_TX3+

PEG_TX3-

Table Table Table Table 12121212: : : : PEG x4 Signal GroupPEG x4 Signal GroupPEG x4 Signal GroupPEG x4 Signal Group


31

4.2.2.2.4.2.2.2.4.2.2.2.4.2.2.2. PEG x4 Layout and Routing RecommendationsPEG x4 Layout and Routing RecommendationsPEG x4 Layout and Routing RecommendationsPEG x4 Layout and Routing Recommendations

The layout and routing recommendations for the PEG x4 signals in COM Express carrier board are listed

below:

Each trace of differential pairs should route to parallel to each other with the same trace length.

All the PCI Express signals should be referenced to the ground plane at all times.

The spacing between differential pairs must be equal at all times (in parallel), even during trace

bending and serpentine topology.

Differential pairs must be routed on the same layer with maximum of one signal layer change

allowed. The differential pairs must always move to the same layer with the same reference plane.

Transmit differential pairs are recommended to be routed on the top layer and receive differential

pairs are recommended to be routed on the bottom layer.

Do not route PCI Express traces under magnetic devices or IC’s, oscillators and clock synthesizers.


It is always best to reduce the line mismatch to add to the timing margin. In other words, a

balanced topology can match the trace lengths within the groups to minimize skew.

Figure Figure Figure Figure 22222222: : : : PEG x4 Trace SpacingPEG x4 Trace SpacingPEG x4 Trace SpacingPEG x4 Trace Spacing

Signal GroupSignal GroupSignal GroupSignal Group Trace & SpacingTrace & SpacingTrace & SpacingTrace & Spacing


DifferentialDifferentialDifferentialDifferential



Other SignalOther SignalOther SignalOther Signal

PE16 (4-Lane) Transmit 15 : 5 : 5 : 5 : 15

Differential 85Ω ± 10% 20 mil

Receive

Table Table Table Table 13131313: : : : PEG x4 Interface Trace PropertiesPEG x4 Interface Trace PropertiesPEG x4 Interface Trace PropertiesPEG x4 Interface Trace Properties

Signal GroupSignal GroupSignal GroupSignal Group Routing TopologyRouting TopologyRouting TopologyRouting Topology Signal TypeSignal TypeSignal TypeSignal Type NoteNoteNoteNote

PE16 (4-Lane) Transmit

Point to Point Source Synchronous

I/O Signals

Don’t cross power

plane division line Receive

Table Table Table Table 14141414: : : : PEG x4 Interface Routing Topology and Signal TypePEG x4 Interface Routing Topology and Signal TypePEG x4 Interface Routing Topology and Signal TypePEG x4 Interface Routing Topology and Signal Type

Signal GroupSignal GroupSignal GroupSignal Group Routing LayerRouting LayerRouting LayerRouting Layer Accumulated Trace LengthAccumulated Trace LengthAccumulated Trace LengthAccumulated Trace Length Trace Length MismatchTrace Length MismatchTrace Length MismatchTrace Length Mismatch

PE16 (4-Lane) Top or Bottom < 5″ (for PCIe Gen1)

< 2″ (for PCIe Gen2) < 0.005″

Table Table Table Table 15151515: : : : PEG x4 Interface PEG x4 Interface PEG x4 Interface PEG x4 Interface Layout GuidelinesLayout GuidelinesLayout GuidelinesLayout Guidelines


32

4.3. Digital Display Interface The DDI interface is one of the newly added interfaces in COM Express (COM.0 R2.0). The VIA COM

Express (COM.0 R2.0 compliant) modules provide Digital Display Interface (DDI) pin-out signals designed

for interfacing the HDMI® (High Definition Multimedia Interface) or DisplayPort connection.

The Type 10 module supports one DDI interface for DDI port 1. Its pin-out locations are implemented

only on connector row B. Previously on Type 1 modules, the pin-out were used for the LVDS channel B

and VGA interfaces. The Type 6 module can support up to two DDI interface for DDI port 2 and DDI port

3 on connector C-D. The carrier board developer can use the DDI port 2 to configure it to either HDMI®

or DiplayPort connection. The DDI port 3 is intended only for DisplayPort interface connection. The

HDMI® and DisplayPort connectors both use differential signaling, however, the auxiliary channel is

required when DDI port 2 is going to be configured as a DisplayPort connection.

4.3.1. Digital Display Interface Signal Definition In Type 10 module, the corresponding DDI interfaces (DDI port 1) pin-out signals are defined in

connector row B. In Type 6 module, the corresponding DDI interfaces (DDI port 2 and port 3) pin-out

signals are defined in connector C-D.


DDI0_PAIR0+ B71 O Digital Display Interface 0 Pair 0 differential pair

10

DDI0_PAIR0- B72


DDI0_PAIR1- B74


DDI0_PAIR2- B76


DDI0_PAIR3- B82


DDI0_PAIR4- B78


DDI0_PAIR5- B92


DDI0_PAIR6- B94

DDI0_HPD B89 I Digital Display Interface 0 Hot-Plug Detect

DDI2_PAIR0+ D39 O Digital Display Interface 2 Pair 0 differential pair

6

DDI2_PAIR0- D40


DDI2_PAIR1- D43


DDI2_PAIR2- D47


DDI2_PAIR3- D50

DDI2_HPD D44 I Digital Display Interface 2 Hot-Plug Detect

DDI2_CTRLCLK_AUX+ C32 IO

DP Aux+ function if DDI[2]_DDC_AUX_SEL is

not connected

HDMI I²C CTRLCLK if DDI[2]_DDC_AUX_SEL is

pulled high

DDI2_CTRLDATA_AUX- C33 IO

DP Aux- function if DDI[2]_DDC_AUX_SEL is not

connected

HDMI I²C CTRLDATA if DDI[2]_DDC_AUX_SEL

is pulled high

DDI2_DDC_AUX_SEL C34 I Select the function of DDI[2]_CTRLCLK_AUX+

and DDI[2]_CTRLDATA_AUX-

DDI3_PAIR0+ C39 O Digital Display Interface 3 Pair 0 differential pair

DDI3_PAIR0- C40


DDI3_PAIR1- C43


33


6

DDI3_PAIR2- C47


DDI3_PAIR3- C50

DDI3_HPD C44 I Digital Display Interface 3 Hot-Plug Detect

DDI3_CTRLCLK_AUX+ C36 IO

DP Aux+ function if DDI[3]_DDC_AUX_SEL is

not connected

HDMI I²C CTRLCLK if DDI[3]_DDC_AUX_SEL is

pulled high

DDI3_CTRLDATA_AUX- C37 IO

DP Aux- function if DDI[3]_DDC_AUX_SEL is not

connected

HDMI I²C CTRLDATA if DDI[3]_DDC_AUX_SEL

is pulled high

Table Table Table Table 16161616: : : : Digital Display Interface Signal DescriptionsDigital Display Interface Signal DescriptionsDigital Display Interface Signal DescriptionsDigital Display Interface Signal Descriptions

4.3.2. DDI Reference Schematics

DP1TX2+_

P14

DP1TX_0-_

DP1TX_0+_

P15

P13

DP1TX0+_

DP1TX_3-_

P17

DP1TX3+_DP1TX_3+_

DP1TX_1-_

PWR_Select

DP1TX_2-_

DP1TX_1+_

P16

DP1TX2-_

P18

DP1TX_2+_DP1TX1-_

PWR_Select

-DP1HPD

DDI_CTRLCLK P15

P19P18

P17P16

DDI_CTRLDATA

DP1TX1+_DP1TX0-_

PWR_Select

DP1TX3-_DP1TX3+_

P17

P16

DP1TX0+_

DP1TX3-_

DP1TX2+_

P19P15

DP1TX0-_

P18

DP1TX1+_

P16

P14

DP1TX1-_

P13P18

DP1TX0-_

P15

DP1TX2-_DP1TX2+_

DP1TX1+_

P17

DP1TX3+_

P13

DP1TX2-_DP1TX0+_

P14

P19

DP1TX1-_

P15

P16

-DP1HPD

P19

P15

P17

DP1TX3-_

DP2_TX0+

DP2_TX0-DP2_TX1+

DP2_TX1-DP2_TX2+

DP2_TX2-DP2_TX3+

DP2_TX3-

DDI_CTRLCLKDDI_CTRLDATA

DDC_AUX_SEL

-DP2_HPD

+12V

HDMI_DP_PWR

HDMI_DP_PWR+3.3V

+5V

+3.3V

HDMI_DP_PWR

+3.3V+2.5V

+3.3V

HDMI_DP_PWR

+3.3V

HDMI (Blue Area)Co-layout With DisplayPort

DP (Pink Area)

For HDMI only, please remove all DisplayPort components ( ),

and install HDMI components on ( ).

Notes:

For DisplayPort Only, please remove all HDMI

components ( ), and install DP

components on ( ).

Pink Area

HDMICLK

HDMIT2

HDMIT1

HDMIT0

ESD

Blue Area

HPD

Vgs must less

than 2.5V

0.5A for layout reference 0.5A for layout reference

DDC_AUX_SEL = 0, DP selected

DDC_AUX_SEL = 1, HDMI selected

DP1_AUX+ to DDI_CTRLCLK

DP1_AUX- to DDI_CTRLDATA

Q20Si2308BDS-T1-GE3Q20Si2308BDS-T1-GE3

G

DS

C188 0.1uFC188 0.1uF

L34 ACM2012-900-2P-T002L34 ACM2012-900-2P-T0021 4

32

R521 620_1%R521 620_1%

R514 10KR514 10K

Q352N7002Q352N7002

G

DS

R524 0/XR524 0/X

C340 0.1uF/XC340 0.1uF/X

C186 0.1uFC186 0.1uF

D27RClamp0544T.TCTD27RClamp0544T.TCT

2

G1

34

1

56

78

R518 620_1%R518 620_1%

R529 0/XR529 0/XL32 ACM2012-900-2P-T002L32 ACM2012-900-2P-T002

1 4

32

R522 620_1%R522 620_1%

R528 1.5KR528 1.5K

R516 620_1%R516 620_1%


2

G1

34

1

56

78

PS10

SMD1206P150TF_1.5A

PS10

SMD1206P150TF_1.5A

1 2

HDMIC022034HDMIC022034

123456789

10111213141516171819

G1

G2

G4

G3

R526 200R526 200R525 0/XR525 0/X

C185 0.1uFC185 0.1uF

C1671uFC1671uF

R539 100K/XR539 100K/X

D37 BAV99D37 BAV99

2

3

1

C339 0.1uF/XC339 0.1uF/X

R519 620_1%R519 620_1%

R5150R5150

L30 ACM2012-900-2P-T002L30 ACM2012-900-2P-T0021 4

32


2

G1

34

1

56

78

R517 620_1%R517 620_1%

DP1

47272-0001/X

DP1

47272-0001/X

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

M1M1

G1

G1

G2

G2

G3

G3

G4

G4

R523 620_1%R523 620_1%

R530 1.5KR530 1.5K

R542 1KR542 1K

R543100KR543100K

FB20

ACMS160808A6001A

FB20

ACMS160808A6001A

C181 0.1uFC181 0.1uF

R527 200R527 200

C183 0.1uFC183 0.1uF

R5364.7KR5364.7K

R534 100K/XR534 100K/X

R540 10K/XR540 10K/X

L36 ACM2012-900-2P-T002L36 ACM2012-900-2P-T0021 4

32

Q34FDC6301NQ34FDC6301N

G1

1

S2

2

G2

3D

24

S1

5

D1

6

C189 0.1uFC189 0.1uF

R520 620_1%R520 620_1%

R544 0R544 0

R5350R5350

Q362N7002Q362N7002

G

DS

C179 0.1uFC179 0.1uF

Q332N7002Q332N7002

G

DS

C182 0.1uFC182 0.1uF

R5384.7KR5384.7K


2

G1

34

1

56

78

R541 0/XR541 0/X

R537 0/XR537 0/X

Blue Area

Pink Area

1.

2.

Figure Figure Figure Figure 23232323: : : : DDI Interface ImplementatiDDI Interface ImplementatiDDI Interface ImplementatiDDI Interface Implementation Exampleon Exampleon Exampleon Example


34

Figure Figure Figure Figure 24242424: : : : HDMIHDMIHDMIHDMI®®®® Interface Connector DiagramInterface Connector DiagramInterface Connector DiagramInterface Connector Diagram

Figure Figure Figure Figure 25252525: : : : DisplayPort Interface Connector DiagramDisplayPort Interface Connector DiagramDisplayPort Interface Connector DiagramDisplayPort Interface Connector Diagram


35

4.3.2.1.4.3.2.1.4.3.2.1.4.3.2.1. DDI Layout and Routing RecommendationsDDI Layout and Routing RecommendationsDDI Layout and Routing RecommendationsDDI Layout and Routing Recommendations

The layout and routing recommendations for the DDI interface in COM Express carrier board are listed

below:

Differential pair should be all referenced to ground.

Each differential pairs signal should route to parallel to each other with the same trace length.

Route the DDI pairs on a single layer adjacent to a ground plane.

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Termination Termination Termination Termination

OptionOptionOptionOption

Routing Routing Routing Routing

TopologyTopologyTopologyTopology Terminal TypeTerminal TypeTerminal TypeTerminal Type

Differential Pair

DDI0_PAIR[5:0]+

None Point to Point None

DDI0_PAIR[5:0]-

DDI2_PAIR[3:0]+

DDI2_PAIR[3:0]-

DDI3_PAIR[3:0]+

DDI3_PAIR[3:0]-

Single-ended

DDI0_HPD

None Point to Point None DDI2_HPD

DDI3_HPD

DDI2_CTRLCLK_AUX+

None Point to Point None DDI3_CTRLCLK_AUX+

DDI2_CTRLDATA_AUX-

DDI3_CTRLDATA_AUX-

Table Table Table Table 17171717: : : : DDI Interface TermiDDI Interface TermiDDI Interface TermiDDI Interface Termination Option and Routing Topologynation Option and Routing Topologynation Option and Routing Topologynation Option and Routing Topology

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Trace Trace Trace Trace

ImpedanceImpedanceImpedanceImpedance

TraceTraceTraceTrace

(Width : Spacing)(Width : Spacing)(Width : Spacing)(Width : Spacing)

Spacing to Spacing to Spacing to Spacing to


Differential Pair

DDI0_PAIR[5:0]+

85Ω ± 15% 15 : 5 : 6 : 5 : 15 15 mil

DDI0_PAIR[5:0]-

DDI2_PAIR[3:0]+

DDI2_PAIR[3:0]-

DDI3_PAIR[3:0]+

DDI3_PAIR[3:0]-

Single-ended

DDI0_HPD

50Ω 5 : 6 6 mil DDI2_HPD

DDI3_HPD

DDI2_CTRLCLK_AUX+

50Ω 5 : 6 6 mil DDI3_CTRLCLK_AUX+

DDI2_CTRLDATA_AUX-

DDI3_CTRLDATA_AUX-

Table Table Table Table 18181818: : : : DDI Interface DDI Interface DDI Interface DDI Interface Trace PropertiesTrace PropertiesTrace PropertiesTrace Properties


36

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer Trace MismatchTrace MismatchTrace MismatchTrace Mismatch Accumulated Accumulated Accumulated Accumulated


Differential Pair

DDI0_PAIR[5:0]+

Top or Bottom < 100 mil < 6”

DDI0_PAIR[5:0]-

DDI2_PAIR[3:0]+

DDI2_PAIR[3:0]-

DDI3_PAIR[3:0]+

DDI3_PAIR[3:0]-

Single-ended

DDI0_HPD

Top or Bottom - - DDI2_HPD

DDI3_HPD

DDI2_CTRLCLK_AUX+

Top or Bottom - - DDI3_CTRLCLK_AUX+

DDI2_CTRLDATA_AUX-

DDI3_CTRLDATA_AUX-

Table Table Table Table 19191919: : : : DDI IDDI IDDI IDDI Interface Layout Guidelinesnterface Layout Guidelinesnterface Layout Guidelinesnterface Layout Guidelines


We recommend the usage of a re-driver for some of the high speed interconnects including, but not limited to

the DisplayPort and HDMI®. Please contact VIA FAE for additional information.


37

4.4. VGA Interface The analog VGA interface signals defined in the connector row B of the COM Express specification.

4.4.1. VGA Signal Definition Analog Red, Green and Blue (RGB) signals, Horizontal Sync (HSYNC), Vertical Sync (VSYNC) and I²C data

control are the group of signals for the VGA interface implementation.

Signal NameSignal NameSignal NameSignal Name Pin #Pin #Pin #Pin # I/OI/OI/OI/O DescriptionDescriptionDescriptionDescription DDDD----SubSubSubSub 15151515----pin pin pin pin

ConnectorConnectorConnectorConnector TypeTypeTypeType

VGA_RED B89 O Red component of analog DAC monitor 1

6 and 2

VGA_GRN B91 O Green component of analog DAC monitor 2

VGA_BLU B92 O Blue component of analog DAC monitor 3

VGA_HSYNC B93 O Horizontal sync output to VGA monitor 13

VGA_VSYNC B94 O Vertical sync output to VGA monitor 14

VGA_I2C_CK B95 O DDC clock line 15

VGA_I2C_DAT B96 IO DDC data line 12

GND Ground 5, 8, 10

Power 5V DDC supply voltage for monitor EEPROM 9

NC No connection 4, 11

Table Table Table Table 20202020: : : : VGA Signal DescriptionsVGA Signal DescriptionsVGA Signal DescriptionsVGA Signal Descriptions

4.4.2. VGA Reference Schematics

Figure Figure Figure Figure 26262626: : : : VGA Interface Connector ExampleVGA Interface Connector ExampleVGA Interface Connector ExampleVGA Interface Connector Example


38

4.4.2.1.4.4.2.1.4.4.2.1.4.4.2.1. VGA Interface TopologyVGA Interface TopologyVGA Interface TopologyVGA Interface Topology

Analog Red, Green and Blue (RGB) traces should be designed to be as short as possible. The diagram

below, the RGB outputs are current sources and therefore require 150Ω ± 1% load resistors from each

RGB line to GND to create the output voltage (approximately 0 to 0.7 V). These resistors should be

placed near the VGA port (a 15-pin D-Sub connector). The 22Ω series damping resistors for HSYNC and

VSYNC should be placed near the D-Sub connector.

Figure Figure Figure Figure 27272727: : : : VGA Interface Sample DiagramVGA Interface Sample DiagramVGA Interface Sample DiagramVGA Interface Sample Diagram


The ferrite beads used for the RGB signals should have high frequency characteristics. (75Ω at 100 MHz).

4.4.2.2.4.4.2.2.4.4.2.2.4.4.2.2. VGA Layout and RecommendationsVGA Layout and RecommendationsVGA Layout and RecommendationsVGA Layout and Recommendations

The layout and routing recommendations for the VGA interface trace signals in COM Express Carrier

Board are listed below:

RGB signal traces should be designed to be as short as possible.

In order to maximize noise rejection characteristics of the RGB video outputs, it is then

recommended to route the RGB video outputs on the top layer over a solid ground plane.

The routing for the RGB signals should be as similar as possible (i.e., same routing layer(s), same

number of vias, same routing length, same bends and jogs)

Route the RGB trace signals and two sync signals (HSYNC and VSYNC) as a single-ended signal with

a trace impedance of 75Ω.

RGB signals should be connected to their each respective π-filter and to the VGA connector, and

then 150Ω ± 1% impedance should be strictly applied.

To maximize the effectiveness of the EMI filtering, it is recommended to put the π-filter near to the

VGA connector.


39

Figure Figure Figure Figure 28282828: : : : Recommended RGB Trace PropertiesRecommended RGB Trace PropertiesRecommended RGB Trace PropertiesRecommended RGB Trace Properties

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name TraceTraceTraceTrace

(Width : Spacing)(Width : Spacing)(Width : Spacing)(Width : Spacing) Trace Trace Trace Trace ImpedanceImpedanceImpedanceImpedance

Spacing inSpacing inSpacing inSpacing in

Other GroupOther GroupOther GroupOther Group

Analog

VGA_AR

10 : 10 37.5Ω ± 15% 20 mil VGA_AG

VGA_AB

Control

VGA_HSYNC

5 : 10 55Ω ± 15% 20 mil VGA_VSYNC

VGA_I2C_DATA

VGA_I2C_CK

Table Table Table Table 21212121: : : : VGA Interface Trace PropertieVGA Interface Trace PropertieVGA Interface Trace PropertieVGA Interface Trace Propertiessss

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Termination OptionTermination OptionTermination OptionTermination Option Routing TopologyRouting TopologyRouting TopologyRouting Topology

Analog

VGA_AR

Pull-down Point-to-Point VGA_AG

VGA_AB

Control

VGA_HSYNC

None Point-to-Point VGA_VSYNC

VGA_I2C_DATA

VGA_I2C_CK

Table Table Table Table 22222222: : : : VGA InterVGA InterVGA InterVGA Interface Termination Option and Routing Topologyface Termination Option and Routing Topologyface Termination Option and Routing Topologyface Termination Option and Routing Topology

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer AccumulatedAccumulatedAccumulatedAccumulated



MismatchMismatchMismatchMismatch

Analog

VGA_AR

Top or Bottom < 8″ < 0.5″ VGA_AG

VGA_AB

Control

VGA_HSYNC

Top or Bottom < 15″ None VGA_VSYNC

VGA_I2C_DATA

VGA_I2C_CK

Table Table Table Table 23232323: : : : VGA Interface Layout GuidelinesVGA Interface Layout GuidelinesVGA Interface Layout GuidelinesVGA Interface Layout Guidelines


1. Analog signal:Analog signal:Analog signal:Analog signal: the analog trace length in VIA COM Express module is approximately 3.5” therefore the

analog trace length in the carrier board should not be longer than 4”.

2. Control signal:Control signal:Control signal:Control signal: the control trace length in VIA COM Express Module is approximately 3.5” therefore the

Control trace length in the carrier board should not be longer than 11”.


40

4.5. LVDS Interface The LVDS interface in the VIA COM Express module enables displaying graphics on LVDS and flat panel

displays using a dual-channel LVDS. The dual channel LVDS supports 18-bit and 24-bit interfaces.

The LVDS signal interface consists of four differential data pairs and one differential clock pair for each

channel and five single-ended support signals. The included five single-ended signals are used for LVDS

power enable, backlight control, enable lines and I2C interface.

4.5.1. LVDS Signal Definition The LVDS interface signals are implemented in connector A-B.


LVDS_A0+ A71 O LVDS channel A differential signal pair 0

10, 6, and 2

LVDS_A0- A72


LVDS_A1- A74


LVDS_A2- A76


LVDS_A3- A79

LVDS_A_CLK+ A81 O LVDS channel A differential clock pair

LVDS_A_CLK- A82

LVDS_B0+ B71 O LVDS channel B differential signal pair 0

6 and 2

LVDS_B0- B72


LVDS_B1- B74


LVDS_B2- B76


LVDS_B3- B78

LVDS_B_CLK+ B81 O LVDS channel B differential clock pair

LVDS_B_CLK- B82

LVDS_VDD_EN A77 O LVDS flat panel power enable

10, 6 and 2

LVDS_BLKT_EN B79 O LVDS flat panel backlight enable

LVDS_BLKT_CTRL B83 O LVDS flat backlight brightness control

LVDS_I2C_CK A83 O DDC I²C clock signal for detection and control

LVDS_I2C_DAT A84 IO DDC I²C data signal for detection and control

Table Table Table Table 24242424: : : : LVDS Signal DescriptionsLVDS Signal DescriptionsLVDS Signal DescriptionsLVDS Signal Descriptions


41

4.5.2. LVDS Reference Schematics

-A7_L

A0_L

A7_L

A3_L

CLK1_L

-A6_L

-A5_L

-CLK1_L

SPCLK_R

-CLK1_L

-A2_L

-A4_L

-A1_L

A5_L

SPD_R

A6_L

-CLK2_L

-A7_L

-A4_L

A6_L

CLK2_L

A2_L

CLK1_L

A7_L

A4_L

A2_L

-A5_L

-A3_L

-A6_L

-A0_L

CLK2_L-CLK2_L

-A1_L

A4_L-A3_L

-A0_L

A3_L

A1_L

-A2_L

A0_L

A5_L

A1_L

PVDD

LVDS_A0+

LVDS_A0-

LVDS_A1+

LVDS_A1-

LVDS_A2+

LVDS_A2-

LVDS_A3+

LVDS_A3-

LVDS_A_CK+

LVDS_A_CK-

LVDS_B0+

LVDS_B2+

LVDS_B1-

LVDS_B_CK+

LVDS_B_CK-

LVDS_B1+

LVDS_B3+

LVDS_B3-

LVDS_B2-

LVDS_B0-

LVDS_I2C_CKLVDS_I2C_DAT

L33 ACM2012-900-2P-T002L33 ACM2012-900-2P-T002

1 4

32

L31 ACM2012-900-2P-T002L31 ACM2012-900-2P-T002

1 4

32

L29 ACM2012-900-2P-T002L29 ACM2012-900-2P-T002

1 4

32

L35 ACM2012-900-2P-T002L35 ACM2012-900-2P-T002

1 4

32

L27 ACM2012-900-2P-T002L27 ACM2012-900-2P-T002

1 4

32

R185 0R185 0

L28 ACM2012-900-2P-T002L28 ACM2012-900-2P-T002

1 4

32

L37 ACM2012-900-2P-T002L37 ACM2012-900-2P-T002

1 4

32

L25 ACM2012-900-2P-T002L25 ACM2012-900-2P-T002

1 4

32

L40 ACM2012-900-2P-T002L40 ACM2012-900-2P-T002

1 4

32

LVDS

20031-040U-01

LVDS

20031-040U-01

2 14 36 58 710 912 1114 1316 1518 1720 1922 2124 2326 2528 2730 2932 3134 3336 3538 3740 39L26 ACM2012-900-2P-T002L26 ACM2012-900-2P-T002

1 4

32

R186 0R186 0

Figure Figure Figure Figure 29292929: : : : LVDS Connector ExampleLVDS Connector ExampleLVDS Connector ExampleLVDS Connector Example

PVDD_SEL

VDD_EN

PVDD_ON

-VDD_EN

PVDD

PVDD_TR

LVDS_VDD_EN

+5V +3.3V

+5V

Pin 2,3 : Close

PVDD

Pin 1,2 : Close

+3.3V *

C184 0.1uFC184 0.1uF

Q22SI2301BDS-T1-E3Q22SI2301BDS-T1-E3

G

DS

Q26PMBT3904Q26PMBT3904

B

EC

R17933R17933

C1630.1uFC1630.1uF

R184 1KR184 1K

R1814.7KR1814.7K

C1970.1uFC1970.1uF

Q242N7002Q242N7002G

DS

PVDDHEADER_1X3PVDD

HEADER_1X321 3

FB19BLM21PG300SN1D

FB19BLM21PG300SN1D

Default: +3.3V (Pin 2,3 Close)

+5V

Figure Figure Figure Figure 30303030: : : : LVDS Panel PowerLVDS Panel PowerLVDS Panel PowerLVDS Panel Power


42

BAKLITE

IVDD_GND

LVDS_I2C_DAT

-BKLT_EN

IVDD_IN

LVDS_I2C_CK

BLT_CTRL

IVDD_SEL

BKLT_ENLVDS_BKLT_EN[4]

BLT_CK[4,5,26]

+5V

+5V

+12V_VCC

+5V

+5V

+12V *

IVDD_SEL

+5V Pin 1,2 : Close

Pin 2,3 : Close

Default: +12V (Pin 2,3 Close)

IVDDHEADER_1X3

IVDDHEADER_1X3

2 13


B

EC

Q42N7002Q42N7002G

DS

FB2BLM21PG300SN1D

FB2BLM21PG300SN1D

C50.1uFC50.1uF

U1

AD5301BRTZ

U1

AD5301BRTZ

GND1

A05

VOUT4

SCL3

SDA2

VDD6

C2 0.1uFC2 0.1uF

R5 0R5 0

INVERTER

1251S-08-SM1-TR-F5

INVERTER

1251S-08-SM1-TR-F5

11

22

33

44

55

66

88

77

M1M1

M2M2

C160.1uFC160.1uF

C19 0.1uFC19 0.1uF

R164.7KR164.7K

R6470_1%R6470_1%

+

CE147uF

+

CE147uF

12

FB3BLM21PG300SN1DFB3BLM21PG300SN1D

R15 1KR15 1K

R4 0/XR4 0/X

Figure Figure Figure Figure 31313131: : : : LVDS BacklightLVDS BacklightLVDS BacklightLVDS Backlight

4.5.2.1.4.5.2.1.4.5.2.1.4.5.2.1. LVDS Interface ToLVDS Interface ToLVDS Interface ToLVDS Interface Topologypologypologypology

Figure Figure Figure Figure 32323232: : : : LVDS Interface Sample DiagramLVDS Interface Sample DiagramLVDS Interface Sample DiagramLVDS Interface Sample Diagram


43

4.5.2.2.4.5.2.2.4.5.2.2.4.5.2.2. LLLLVDS Layout and Routing RecommendationsVDS Layout and Routing RecommendationsVDS Layout and Routing RecommendationsVDS Layout and Routing Recommendations

The layout and routing recommendations for the LVDS interface in COM Express Carrier board are listed

below:

Differential pairs should all be referenced to ground.

Each differential pair signal (LVDS_A±, LVDS_B±) and clock differential pair (LVDS_A_CK±,

LVDS_B_CK±) should be routed parallel to each other with the same trace length.

Clock differential pair signals (LVDS_A_CK±, LVDS_B_CK±) should be length matched <20 mil.

Route the LVDS pairs on a single layer adjacent to a ground plane.


OptionOptionOptionOption Routing TopologyRouting TopologyRouting TopologyRouting Topology Terminal TypeTerminal TypeTerminal TypeTerminal Type

Differential Pair

LVDS_A[3:0]+

None Point to Point None

LVDS_A[3:0]-

LVDS_B[3:0]+

LVDS_B[3:0]-

LVDS_A_CLK+

LVDS_A_CLK-

LVDS_B_CLK+

LVDS_B_CLK-

Single-ended

LVDS_BLKT_CTRL

None Point to Point None LVDS_I2C_CK

LVDS_I2C_DAT

LVDS_VDD_EN None Point to Point None

LVDS_BLKT_EN

Table Table Table Table 25252525: : : : LVDS Interface Termination Option and Routing TopologyLVDS Interface Termination Option and Routing TopologyLVDS Interface Termination Option and Routing TopologyLVDS Interface Termination Option and Routing Topology

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance TraceTraceTraceTrace




Differential Pair

LVDS_A[3:0]+

100Ω ± 15% 20 : 5 : 8 : 5 : 20 20 mil LVDS_A[3:0]-

LVDS_B[3:0]+

LVDS_B[3:0]-

LVDS_A_CLK+

100Ω ± 15% 20 : 5 : 8 : 5 : 20 20 mil LVDS_A_CLK-

LVDS_B_CLK+

LVDS_B_CLK-

Single-ended

LVDS_BLKT_CTRL

55Ω 5 : 8 8 mil LVDS_I2C_CK

LVDS_I2C_DAT

LVDS_VDD_EN 55Ω 5 : 8 8 mil

LVDS_BLKT_EN

Table Table Table Table 26262626: : : : LVDS Interface Trace PropertiesLVDS Interface Trace PropertiesLVDS Interface Trace PropertiesLVDS Interface Trace Properties


44

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer Trace MismatchTrace MismatchTrace MismatchTrace Mismatch Accumulated Accumulated Accumulated Accumulated


Differential Pair

LVDS_A[3:0]+

Top or Bottom < 100 mil < 6.5″ LVDS_A[3:0]-

LVDS_B[3:0]+

LVDS_B[3:0]-

LVDS_A_CLK+

Top or Bottom < 100 mil < 6.5″ LVDS_A_CLK-

LVDS_B_CLK+

LVDS_B_CLK-

Single-ended

LVDS_BLKT_CTRL

Top or Bottom - - LVDS_I2C_CK

LVDS_I2C_DAT

LVDS_VDD_EN Top or Bottom - -

LVDS_BLKT_EN

Table Table Table Table 27272727: : : : LVDS Interface LVDS Interface LVDS Interface LVDS Interface Layout GuidelinesLayout GuidelinesLayout GuidelinesLayout Guidelines


The LVDS trace length in VIA COM Express module is approximately 4.5”. Therefore, the LVDS trace length in

the carrier board should not be longer than 1.5”.


45

4.6. Digital Video Port (DVP) Interface The DVP interface is a parallel bus signals provided for interfacing DVP slot or an external digital TV

Encoder/DVI transmitter. The Digital Video Port is a VIA proprietary interface and available only in VIA

COM Express Type 6 and Type 2 modules.

4.6.1. DVP Signal Definition The DVP interface signals are implemented in connector C-D.


DVP1_D0 C78 O Digital Video Port 1 Data 0.

6 and 2

DVP1_D1 D78 O Digital Video Port 1 Data 1.















DVP1_DE C91 O Digital Video Port 1 Data Enable.

DVP1_VS D92 O Digital Video Port 1 Vertical Sync.

DVP1_HS C94 O Digital Video Port 1 Horizontal Sync.

DVP1_TVFLD C95 IO Digital Video Port 1 TV Field Out.

DVP1_TVCLKR D91 I Digital Video Port 1 TV Return Clock.

DVP1_CLK D94 O Digital Video Port 1 Clock.

DVP1_SPD C98 IO Digital Video Port 1 I²C Data.

DVP1_SPCLK C99 IO Digital Video Port 1 I²C Clock.

DVP1_VDD_EN D98 O Enable Panel VDD Power.

DVP1_BKLT_EN D99 O Enable Panel Back Light.

Table Table Table Table 28282828: : : : DVP Signal DescriptionsDVP Signal DescriptionsDVP Signal DescriptionsDVP Signal Descriptions


The DVP interface is not defined in standard COM Express Specification.


46

4.6.2. DVP Reference Schematics

DVP1_TVCLKR

DVP1_VDD_EN

DVP1_TVFLD

DVP1_SPDDVP1_SPCLK

DVP_SPDIF_HDMI

-SLOT_RST

DVP1_HSDVP1_VS

DVP1_TVCLKR

DVP1_D2DVP1_D3

DVP1_D6DVP1_D7

DVP1_D9

DVP1_D12DVP1_D13

DVP1_CLK

DVP1_DE

DVP1_BKLT_EN

DVP1_D0DVP1_D1

DVP1_D4DVP1_D5

DVP1_D8

DVP1_D10DVP1_D11

DVP1_D14DVP1_D15

BLT_CK

+5V+3.3V

+5V

+3.3V

+5V +3.3V

10V 080510V 0805

Plug detection from DVP2-3*

TTL/TV from DVP

DVP1TVCLKR function selectionTV_DVP_SEL

1-2

+CE54 470uF/16V+CE54 470uF/16V1 2

TV_DVP_SEL

HEADER_1X3

TV_DVP_SEL

HEADER_1X3

21

3

C331 10uFC331 10uFR3544.7KR3544.7K

+CE53 470uF/16V+CE53 470uF/16V1 2

C330 10uFC330 10uF

DVP_SLOT

EE03200S-CP3

DVP_SLOT

EE03200S-CP3

+5VB1

+5VB2

NCB3

GNDB4

SPCLK1B5

SPD1B6

GNDB7

+3.3VB8

TVFLDB9

+3.3VB10

DEB11

CLOCKB12

GNDB13

D13B14

D12B15

GNDB16

D9B17

GNDB18

RST#A1

+5VA2

+5VA3

GNDA4

NCA5

TS1ERRA6

VCP1VSYNCA7

VCP1HSYNCA8

+3.3VA9

+3.3VA10

INTA11

GNDA12

D15A13

D14A14

GNDA15

D11A16

D10A17

GNDA18

D7B19

D6B20

GNDB21

GNDB22

D3B23

D2B24

GNDB25

GNDB26

VSYNCB27

HSYNCB28

GNDB29

DET/TVCLKRB30

TVCLKRB31

GNDB32

D8A19

GNDA20

D5A21

D4A22

GNDA23

GNDA24

D1A25

D0A26

GNDA27

GNDA28

ENBLTA29

ENVDDA30

GNDA31

NCA32

Figure Figure Figure Figure 33333333: : : : DVP DVP DVP DVP SSSSlot lot lot lot EEEExamplexamplexamplexample

4.6.2.1.4.6.2.1.4.6.2.1.4.6.2.1. DVP Interface TopologyDVP Interface TopologyDVP Interface TopologyDVP Interface Topology

The topology example below shows the DVP signal interface from a VIA COM Express (Type 6/Type 2)

module connected to the DVP slot, external digital TV encoder, external DVI transmitter and TTL Panel

connector.

The DVP slot is designed for a TV encoder/DVI transmitter add-in card. The DVP slot enables the

connection of a TV monitor for displaying graphics on DVI flat panel.

Figure Figure Figure Figure 34343434: : : : DVP Slot Interface DiagramDVP Slot Interface DiagramDVP Slot Interface DiagramDVP Slot Interface Diagram


47

By using a digital TV encoder, PC images can be displayed on a TV set. The TV-Out interface example

connected to an external TV encoder (or compatible device) is shown in Figure 35. TV output is

generated whenever the clock input from the encoder is present to the TV_CLK.

Figure Figure Figure Figure 35353535: : : : Digital TVDigital TVDigital TVDigital TV----out Interface using External TV Encoder Implementationout Interface using External TV Encoder Implementationout Interface using External TV Encoder Implementationout Interface using External TV Encoder Implementation

One of the functions of the VIA COM Express module is displaying graphics on DVI flat panels (using a

DVP 12-bit digital interface DVP_D[11:00] to an external encoder or a DVI transmitter). The DVI

technology can transfer data, clock, and control signals from the host graphics controller to high

resolution, high color flat-panel-display-based monitors. This interface example below uses the VIA

VT1632A DVI transmitter chip (refer to the VT1632A data sheet and application notes for more details).

Special attention needs to be paid during voltage conversion of DVI hot plug (+5V) to +3.3V. A single

pixel per clock interface example supporting the industry standard Digital Flat Panel (DFP) interface or

Digital Video Interface (DVI) is shown in figure below.

Figure Figure Figure Figure 36363636: : : : DigiDigiDigiDigital Panel Interface using External DVI Transmitter Implementationtal Panel Interface using External DVI Transmitter Implementationtal Panel Interface using External DVI Transmitter Implementationtal Panel Interface using External DVI Transmitter Implementation


48

Another feature supported by the VIA COM Express module is displaying graphics on TTL LCD panel

monitors through the TTL panel (using an DVP digital interface DVP_D[15:00], DVP_DE, DVP_TVFLD,

DVP_VS, DVP_CLK and DVP_TVCLKR).

Figure Figure Figure Figure 37373737: : : : TTL Panel Interface using External TTL Panel ImplementationTTL Panel Interface using External TTL Panel ImplementationTTL Panel Interface using External TTL Panel ImplementationTTL Panel Interface using External TTL Panel Implementation

4.6.3. Digital Video Port Layout and Routing Recommendation Route traces to minimum whenever possible.

Place the DVI transmitter or TV Encoder as close to connector (LCD/ DVI /TV) as possible.

Each trace should route to parallel to each other with the same trace length.

The spacing of trace must be equal at all times (in parallel), even during trace bending and

serpentine topology.

All trace must be routed on the same layer with maximum of one signal layer change allowed.


It is always best to reduce the line mismatch to add to the timing margin. In other words, a balanced

topology can match the trace lengths within the groups to minimize skew.


OptionOptionOptionOption

Routing Routing Routing Routing

TopologyTopologyTopologyTopology

Termination Termination Termination Termination

TypeTypeTypeType

Data Bus DVP1_D[15:00] None Point-to-Point None

Control

DVP1_DE

None Point-to-Point None

DVP1_VS

DVP1_HS

DVP1_TVFLD

DVP1_TVCLKR

DVP1_CLK

DVP1_SPD

DVP1_SPCLK

DVP1_VDD_EN

DVP1_BKLT_EN

BLT_CK

Table Table Table Table 29292929: : : : DVP Interface Termination Option and Routing TDVP Interface Termination Option and Routing TDVP Interface Termination Option and Routing TDVP Interface Termination Option and Routing Topologyopologyopologyopology


49

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Signal TypeSignal TypeSignal TypeSignal Type TraceTraceTraceTrace

(Width(Width(Width(Width :::: Spacing)Spacing)Spacing)Spacing)





Data Bus DVP1_D[15:00] Single-ended 5 : 10 55Ω ± 10% 15 mil

Control

DVP1_DE

Single-ended 5 : 10 55Ω ± 10% 15 mil

DVP1_VS

DVP1_HS

DVP1_TVFLD

DVP1_TVCLKR

DVP1_CLK

DVP1_SPD

DVP1_SPCLK

DVP1_VDD_EN

DVP1_BKLT_EN

BLT_CK

Table Table Table Table 30303030: : : : DVP Interface Trace PropertiesDVP Interface Trace PropertiesDVP Interface Trace PropertiesDVP Interface Trace Properties

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer Trace Length Trace Length Trace Length Trace Length


AccumulatedAccumulatedAccumulatedAccumulated


Data Bus DVP1_D[15:00] Top or Bottom 500 mil ≤ 9″

Control

DVP1_DE

Top or Bottom 500 mil ≤ 9″

DVP1_VS

DVP1_HS

DVP1_TVFLD

DVP1_TVCLKR

DVP1_CLK

DVP1_SPD

DVP1_SPCLK

DVP1_VDD_EN

DVP1_BKLT_EN

BLT_CK

Table Table Table Table 31313131: : : : DVP Interface Layout GuidelinesDVP Interface Layout GuidelinesDVP Interface Layout GuidelinesDVP Interface Layout Guidelines

NoteNoteNoteNote::::

The DVP interface trace length in VIA COM Express module is approximately ≤ 4.5”. Therefore, the DVP trace

length in the carrier board should not be longer than 4.3”.


50

4.7. Low Pin Count Interface A Low Pin Count (LPC) interface is provided in VIA COM Express modules. The LPC interface serves as a

bus interface between the COM Express module and the LPC Super I/O chip to add peripheral devices

(e.g., mouse, keyboard, parallel port, COM port interface, etc.) on the carrier board design. The LPC

Super I/O chip is a controller that allows the integration of low-bandwidth legacy input/output (I/O)

components in the system. The data transfer on the LPC bus interface is serialized over a 4-bit bus and

uses PCI 33MHz electrical signal characteristics.

4.7.1. LPC Signal Definition The LPC interface signals are implemented in connector A-B.

Signal NaSignal NaSignal NaSignal Namemememe Pin #Pin #Pin #Pin # I/OI/OI/OI/O DescriptionDescriptionDescriptionDescription TypeTypeTypeType

LPC_SERIRQ A50 IO LPC serial IRQ

10, 6 and 2

LPC_FRAME# B3 O LPC frame indicates starts of new cycle or

termination of broken cycle

LPC_AD0 B4 IO

LPC command, address and data LCP_AD1 B5 IO

LPC_AD2 B6 IO

LPC_AD3 B7 IO

LPC_DRQ0# B8 I LPC encoded DMA/Bus master request

LPC_DRQ1# B9 I

LPC_CLK B10 O LPC clock output 33MHz

Table Table Table Table 32323232: : : : LPC Signal DescriptionLPC Signal DescriptionLPC Signal DescriptionLPC Signal Descriptionssss

4.7.2. LPC Reference Schematics

ROM_A5

LCLK_ROM2

ID1

LPC_AD2

CE

-BIOS_DIS0

-LPC_FRAME

ROM_A6

-ROM_OE

ID2

ROM_NC

ROM_CLK

LPC_AD1LPC_AD0

ROM_A7ROM_A8

ROM_A4

ROM_A9

LPC_AD3

ROM_A10

ID0

ID3

LCLK_ROM2-ROM_RESET

+3.3V

+3.3V

NOTE: CLOSE TO LPC ROM

RN1C 10KRN1C 10K5 6

RN1D 10KRN1D 10K7 8

RN1B 10KRN1B 10K3 4RN1A 10KRN1A 10K1 2

R1 10KR1 10KR2 10KR2 10K

U7A

SST49LF080A-33-4C-NHE

U7A


VDD32

WE/LFRAME23

DQ721

DQ620

DQ519

DQ418

LCLK31

RST2

OE/INIT24

MODE29

GND16

NC127

NC/GND26

NC222

A1/ID111

A0/ID012

LAD114

LAD215

LAD317

A10/GPI430

A9/GPI33

A8/GPI24

A7/GPI15

A6/GPI06

NC31

LAD013

VDD25

A5/WP7

A4/TBL8

A3/ID39

A2/ID210

NC/CE28

C45 22pF /XC45 22pF /X

R3 10KR3 10K

RN2B 10KRN2B 10K3 4

R29 10 /XR29 10 /X

RN2A 10KRN2A 10K1 2

RN2C 10KRN2C 10K5 6

C44 0.1uFC44 0.1uF

R28 0 /XR28 0 /X

RN2D 10KRN2D 10K7 8

R27 0 /XR27 0 /X

Figure Figure Figure Figure 38383838: : : : LPC Flash ROM ILPC Flash ROM ILPC Flash ROM ILPC Flash ROM Interfacenterfacenterfacenterface


51

FANPWM2

FANIO2

HWMGND

+3.3V_IN

HWMVCC

+12V_IN

SIO_48M_CLK

SIRQ

VCORE_IN

+5V_IN+5VSUS_IN

IRRX

DTDNDTDP

-PME

IRTX

-PME

IRRX1

SIO_33_CLK

-LPC_FRAME

LPC_AD2LPC_AD3

LPC_AD1LPC_AD0

-LPC_DRQ0

-SIO_RESET

FANPWM1

FANIO1

LPC_SERIRQ

SIO_GPO32

SIO_GPO30

SIO_GPO33

SIO_GPO31

SIO_GPI35SIO_GPI36

SIO_GPI34

SIO_GPI37

LP_D3LP_D2LP_D1LP_D0

LP_D7LP_D6LP_D5

LP_D4

LP_PELP_BUSY

-LP_ACK-LP_ERR-LP_SLIN

-LP_INIT-LP_AFD

-LP_STB

SIO_-RI1

SIO_-CTS1

SIO_-DTR1SIO_-RTS1SIO_-DSR1

SIO_TXD1SIO_RXD1

SIO_-DCD1

SIO_-DCD2SIO_-RI2

SIO_-CTS2

SIO_-DTR2SIO_-RTS2SIO_-DSR2

SIO_TXD2

SIO_RXD2

LP_SLCT

-PLED

-RF_ON

-WAKE1-W_DISABLE

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO +3.3VSIO

Add Wireless LAN disable function.

R95 0R95 0

U11

VT1211

U11

VT1211

DSEL0#1

INDEX#2

MTRA#3

DRVB#4

VCC5

DRVA#6

MTRB#7

DIR#8

STEP#9

WDATA#10

WGATE#11

TRCAK0#12

WPT#13

RDATA#14

HEAD#15

DSKCHG#16

CLKIN17

GND18

PCICLK19

LDRQ#20

SERIRQ21

VCC22

LAD323

LAD224

LAD125

LAD026

LFRAME#27

LRESET#28

SLCT29

PE30

BUSY31

ACK#32

ERR#33

SLIN#34

PD735

PD636

PD537

PD438

PD

339

PD

240

PD

141

PD

042

INIT

#43

AF

D#

44

VC

C45

ST

B#

46

CT

S1#

47

DS

R1#

48

RT

S1#

49

DT

R1#

50

SIN

151

SO

UT

152

DC

D1#

53

RL1#

54

GP

77/V

ID4/C

TS

2#

55

GP

76/V

ID3/D

SR

2#

56

GP

75/V

ID2/R

TS

2#

57

GP

74/V

ID1/D

TR

2#

58

GP

73/V

ID0/S

IN2

59

GN

DD

60

GP

72/S

MB

CK

/SO

UT

261

GP

71/S

MB

DT

/DC

D2#

62

GP

70/R

I2#/I

TM

ON

_O

FF

63

IRR

X64

IRTX65

XA18/GP6266

XA17/GP6167

XA16/GP6068

XA15/GP5769

XA14/GP5670

XA13/GP5571

XA12/GP5472

XA11/GP5373

XA10/GP5274

VCC75

XA9/GP5176

XA8/GP5077

XA7/GP4778

XA6/GP4679

XA5/GP4580

XA4/GP4481

XA3/GP4382

XA2/GP4283

XA1/GP4184

XA0/GP4085

XD7/GP3786

XD6/GP3687

XD5/GP3588

XD4/GP3489

GNDD90

XD3/GP3391

XD2/GP3292

XD1/GP3193

XD0/GP3094

ROMCS#/GP2795

MEMR#/GP2696

MEMW#/GP2597

SMI#//PME#98

GNDD//VSB99

IRRX/GP24//CIRRX100

COPEN/OVER_FAN/GP23/ATEST101

PLED/ITMOFF/GP22/OVER_VOLT//VBAT102

UIC

1103

UIC

2104

VC

CA

105

VR

EF

106

UIC

3107

UIC

4108

UIC

5109

DT

DN

110

DT

DP

111

GN

DA

112

FA

NIO

2113

FA

NIO

1/D

TE

ST

114

FA

NO

UT

2/G

P21

115

FA

NO

UT

1/G

P20

116

OV

TE

MP

#/S

MI#

(W)

117

BE

EP

118

MS

I/O

VE

R_F

AN

(GP

51)/

WD

TO

119

MS

O/O

VE

R_V

OLT

(PLE

D)/

DS

EL1(G

P50)

120

JA

B2/G

P17

121

JB

B2/G

P16

122

JA

CY

/GP

15

123

JB

CY

/P16/G

P14

124

JB

CX

/P15/G

P13

125

JA

CX

/P14/G

P12

126

JB

B1/P

13/G

P11

127

JA

B1/P

12/G

P10

128

R374.7KR374.7K

R36 0R36 0

R94 4.7KR94 4.7K

R82 4.7K/XR82 4.7K/X

TP_FANPWM2TP_FANPWM2 1

TP_FANIO2TP_FANIO2 1

Figure Figure Figure Figure 39393939: : : : LPC Super I/O ExampleLPC Super I/O ExampleLPC Super I/O ExampleLPC Super I/O Example

Figure Figure Figure Figure 40404040: : : : LPC COM InterfacesLPC COM InterfacesLPC COM InterfacesLPC COM Interfaces

COM_DCD1

COM_RI1

COM_RTS1

COM_DTR1

COM_DSR1COM_DCD1

COM_CTS1COM_TXD1

COM_RXD1

COM_CTS1

COM_RTS1

COM_DTR1

COM_TXD1

COM_RXD1COM_DSR1

-XRI1

SIO_-DSR1SIO_RXD1SIO_-RTS1SIO_TXD1

SIO_-DCD1

SIO_-CTS1SIO_-DTR1SIO_-RI1

-12V

+5V +12V_VCC

C3370.1uFC3370.1uF

CN1D

220pF

CN1D

220pF

87

CN2A

220pF

CN2A

220pF

21

C680.1uFC680.1uF

CN2B

220pF

CN2B

220pF

43

CN2C

220pF

CN2C

220pF

65

CN2D

220pF

CN2D

220pF

87

CN1A

220pF

CN1A

220pF

21

U10

GD75232PWR

U10

GD75232PWR

V+1

DIN116

DIN215

DIN313

ROUT119

ROUT218

ROUT317

ROUT414

ROUT512

V-10

GND11

RIN59

RIN47

RIN34

RIN23

RIN12

DOUT38

DOUT26

DOUT15

VCC20

CN1B

220pF

CN1B

220pF

43

VGA_COM1A

C020388-2

VGA_COM1A

C020388-2

C1C6C2C7C3C8C4C9C5

G1

G2

C670.1uFC670.1uF

CN1C

220pF

CN1C

220pF

65


52

4.7.2.1.4.7.2.1.4.7.2.1.4.7.2.1. LPC Interface TopologyLPC Interface TopologyLPC Interface TopologyLPC Interface Topology

The topology example below shows the LPC signal interface from VIA COM Express (Type 10/Type

6/Type 2) module connected to the LPC Super I/O controller.

Figure Figure Figure Figure 41414141: : : : LPC Topology ExampleLPC Topology ExampleLPC Topology ExampleLPC Topology Example

4.7.2.2.4.7.2.2.4.7.2.2.4.7.2.2. LPC Layout and Routing RecommendationsLPC Layout and Routing RecommendationsLPC Layout and Routing RecommendationsLPC Layout and Routing Recommendations

The layout guidelines for the LPC interface are listed below.

Route traces to minimum whenever possible.

Route LPC clocks as single-ended with 55Ω trace impedance and referenced to ground.

One source of the LPC clock comes from COM Express connector. And if there are multiple devices

or slots implemented on the carrier board, a zero delay clock buffer is required to expend the

number of LPC clocks.

Signal NameSignal NameSignal NameSignal Name Signal TypeSignal TypeSignal TypeSignal Type TopologyTopologyTopologyTopology Routing LayerRouting LayerRouting LayerRouting Layer AccumulatedAccumulatedAccumulatedAccumulated


LPC_AD0

Single-ended Point to Point Top or Bottom < 16″ LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

Single-ended Point to Point Top or Bottom < 16″ LPC_SERIRQ

LPC_DRQ0#

LPC_DRQ1#

LPC_CLK Single-ended Point to Point Top or Bottom -

Table Table Table Table 33333333: : : : LPC Interface Topology, Signal Type and Layout GuidelinesLPC Interface Topology, Signal Type and Layout GuidelinesLPC Interface Topology, Signal Type and Layout GuidelinesLPC Interface Topology, Signal Type and Layout Guidelines


53

Signal NameSignal NameSignal NameSignal Name Trace (Width : SpTrace (Width : SpTrace (Width : SpTrace (Width : Spacing)acing)acing)acing) Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance Spacing in Other GroupSpacing in Other GroupSpacing in Other GroupSpacing in Other Group

LPC_AD0

5 : 10 55Ω - LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

5 : 10 55Ω - LPC_SERIRQ

LPC_DRQ0#

LPC_DRQ1#

LPC_CLK 5 : 10 55Ω -

Table Table Table Table 34343434: : : : LPC Interface Trace ProperLPC Interface Trace ProperLPC Interface Trace ProperLPC Interface Trace Propertiestiestiesties


The LPC interface trace length in VIA COM Express module is approximately 4.7″. Therefore, the LPC interface

trace length in the carrier board should not longer than 8.4″.


54

4.8. Serial COM Interface The Serial COM interface is newly defined in the COM.0 R2.0 specifications in response to the demands of

the market. The VIA COM Express Type 10 and Type 6 modules offer a Serial COM interface that enables

interfacing two Serial COM ports on the carrier board design. The two Serial COM interface bus can

support standard RS-232 serial communications.

4.8.1. Serial COM Signal Definition The Serial COM interface signals are defined in the connector row A.


SER0_TX A98 O General purpose serial port 0 transmitter.

10 and 6 SER0_RX A99 I General purpose serial port 0 receiver.

SER1_TX A101 O General purpose serial port 1 transmitter.

SER1_RX A102 I General purpose serial port 1 receiver.

Table Table Table Table 35353535: : : : Serial COM Signal DescriptionsSerial COM Signal DescriptionsSerial COM Signal DescriptionsSerial COM Signal Descriptions

4.8.2. Serial COM Reference Schematics

SER0_RX_CON

SER0_TX_CON

SER1_RX_CON

SER1_TX_CONSER1_RX_CON

SER0_TX_CON SER0_RX_CON

SER1_TX_CONSER1_TXSER0_TX

SER1_RXSER0_RX

+5V +5V

C1030.1uFC1030.1uF

SER_PORT

2213S-10G-E10-F2

SER_PORT

2213S-10G-E10-F2

13 4

2

5 67 89

C1060.1uFC1060.1uF

C1070.1uFC1070.1uF

C1000.1uFC1000.1uF U15

MAX232DR

U15

MAX232DR

T1IN11

T2IN10

R1O12

R2O9

T1O14

T2O7

R1IN13

R2IN8

VCC16

GND15

C1+1

C1-3

C2+4

C2-5

V+2

V-6

C1080.1uFC1080.1uF

Figure Figure Figure Figure 42424242: : : : Serial COM port Interface ExampleSerial COM port Interface ExampleSerial COM port Interface ExampleSerial COM port Interface Example

4.8.2.1.4.8.2.1.4.8.2.1.4.8.2.1. Serial COM Interface TopologySerial COM Interface TopologySerial COM Interface TopologySerial COM Interface Topology

The topology example below shows the Serial COM interface signal from VIA COM Express (Type 10

and Type 6) module connected to the Serial COM port.

Figure Figure Figure Figure 43434343: : : : Serial COM port Interface Topology ExampleSerial COM port Interface Topology ExampleSerial COM port Interface Topology ExampleSerial COM port Interface Topology Example


55

4.8.2.2.4.8.2.2.4.8.2.2.4.8.2.2. Serial COM Layout and Routing RecommendationsSerial COM Layout and Routing RecommendationsSerial COM Layout and Routing RecommendationsSerial COM Layout and Routing Recommendations

Signal NameSignal NameSignal NameSignal Name Signal TypeSignal TypeSignal TypeSignal Type TopologyTopologyTopologyTopology Routing LayerRouting LayerRouting LayerRouting Layer AccumulatedAccumulatedAccumulatedAccumulated


SER0_TX

Single-ended Point to Point Top or Bottom < 16” SER0_RX

SER1_TX

SER1_RX

Table Table Table Table 36363636: : : : Serial COM Interface Topology, Signal Type and Layout GuidelinesSerial COM Interface Topology, Signal Type and Layout GuidelinesSerial COM Interface Topology, Signal Type and Layout GuidelinesSerial COM Interface Topology, Signal Type and Layout Guidelines

Signal NameSignal NameSignal NameSignal Name Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing) Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance Spacing in Other GroupSpacing in Other GroupSpacing in Other GroupSpacing in Other Group

SER0_TX

5 : 10 55Ω - SER0_RX

SER1_TX

SER1_RX

Table Table Table Table 37373737: : : : Serial COM Interface Trace PropertiesSerial COM Interface Trace PropertiesSerial COM Interface Trace PropertiesSerial COM Interface Trace Properties


56

4.9. General Purpose I2C Bus Interface VIA COM Express modules provide a General Purpose I2C interface signal for serial EEPROM memory.

4.9.1. General Purpose I2C Signal Definition The General Purpose I2C interface signals are defined in the connector row A.


I2C_CK B33 O General Purpose I²C Clock Output 10, 6 and 2

I2C_DAT B34 IO General Purpose I²C Data I/O line

Table Table Table Table 38383838: : : : General Purpose IGeneral Purpose IGeneral Purpose IGeneral Purpose I2222C Signal DescriptionsC Signal DescriptionsC Signal DescriptionsC Signal Descriptions

4.9.2. General Purpose I²C Reference Schematics

EEPROM_AX

EEPROM_WP

I2C_CLKI2C_DAT

+3.3V

+3.3V

+3.3V Write Protect

GND Normal Operation *

EEPROM Write Protect

R5210K/XR5210K/X

C720.1uFC720.1uF

U9

AT24C04N-10SU-1.8

U9

AT24C04N-10SU-1.8

A01

A12

A23

GND4

SDA5

SCL6

WP7

VCC8

R47 0R47 0

R42 0R42 0

Figure Figure Figure Figure 44444444: : : : EEPROM Circuitry Reference ExampleEEPROM Circuitry Reference ExampleEEPROM Circuitry Reference ExampleEEPROM Circuitry Reference Example

4.9.2.1.4.9.2.1.4.9.2.1.4.9.2.1. General Purpose I²C Layout and Routing RecommendationsGeneral Purpose I²C Layout and Routing RecommendationsGeneral Purpose I²C Layout and Routing RecommendationsGeneral Purpose I²C Layout and Routing Recommendations

SignSignSignSignal Nameal Nameal Nameal Name Signal TypeSignal TypeSignal TypeSignal Type TopologyTopologyTopologyTopology Routing LayerRouting LayerRouting LayerRouting Layer AccumulatedAccumulatedAccumulatedAccumulated


I2C_CK Single-ended Point to Point Top or Bottom -

I2C_DAT

Table Table Table Table 39393939: : : : General Purpose IGeneral Purpose IGeneral Purpose IGeneral Purpose I2222C Interface Topology, Signal Type and Layout GuidelinesC Interface Topology, Signal Type and Layout GuidelinesC Interface Topology, Signal Type and Layout GuidelinesC Interface Topology, Signal Type and Layout Guidelines

Signal NameSignal NameSignal NameSignal Name Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing) Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance Spacing to Other GroupSpacing to Other GroupSpacing to Other GroupSpacing to Other Group

I2C_CK 5 : 10 55Ω -

I2C_DAT

Table Table Table Table 40404040: : : : General Purpose IGeneral Purpose IGeneral Purpose IGeneral Purpose I2222C Interface Trace PropertiesC Interface Trace PropertiesC Interface Trace PropertiesC Interface Trace Properties


57

4.10. PCI Interface (Type 2 Only) The VIA COM Express Type 2 modules have a PCI bus interface that runs at 33MHz and can support up to

a maximum of three PCI slots or PCI compliant devices designed on the carrier board. The PCI interface

has a daisy chain topology and the signal traces may be laid out on either the component layer (top) or

the solder layer (bottom). The PCI interface is only supported in Type 2 modules.

4.10.1. PCI Signal Definition The PCI interface pin-out signals are implemented in connector C-D.


PCI_AD0 C24 IO PCI bus multiplexed data and address lines

2

PCI_AD1 D22 IO PCI bus multiplexed data and address lines































PCI_C/BE0# D26 IO PCI bus byte enable line 0

PCI_C/BE1# C33 IO PCI bus byte enable line 0



PCI_DEVSEL# C36 IO PCI bus device select

PCI_FRAME# D36 IO PCI bus frame control line

PCI_IRDY# C37 IO PCI bus initiator ready control line

PCI_TRDY# D35 IO PCI bus target ready control line

PCI_STOP# D34 IO PCI bus STOP control line

PCI_PAR D32 IO PCI bus parity

PCI_PERR# C34 IO Parity error

PCI_REQ0# C22 IO PCI bus master request input line



58


2

PCI_REQ3# D20 IO PCI bus master request input line

PCI_GNT0# C20 IO PCI bus grant output line



PCI_GNT3# D19 IO PCI bus grant output line

PCI_RESET# C23 IO PCI reset output

PCI_SERR# D33 IO System error

PCI_PME# C15 IO PCI power management event

PCI_IRQA# C49 IO PCI interrupt request line A

PCI_IRQB# C50 IO PCI interrupt request line B

PCI_IRQC# D46 IO PCI interrupt request line C

PCI_IRQD# D47 IO PCI interrupt request line D

PCI_CLK D50 IO PCI clock output 33MHz

Table Table Table Table 41414141: : : : PCI Signal DescriptionsPCI Signal DescriptionsPCI Signal DescriptionsPCI Signal Descriptions

4.10.2. PCI Reference Schematics

-P1REQ64

-P1LOCK

-P1ACK64

PCI_AD19

PCI_AD1

PCI_AD3PCI_AD5

PCI_AD7PCI_AD8

PCI_AD10PCI_AD12

PCI_AD14

PCI_AD17

PCI_AD19PCI_AD21

PCI_AD23

PCI_AD25PCI_AD27

PCI_AD29PCI_AD31

-PCI_IRDY

-PCI_DEVSEL

-PCI_PERR

PCI_-CBE1

PCI_-CBE2

PCI_-CBE3

-PCI_SERR

-PCI_INT_B-PCI_INT_D

-PCI_INT_A-PCI_INT_C

-PCI_RST2

-PCI_GNT0

PCI_AD30

PCI_AD28PCI_AD26

PCI_AD24

PCI_AD22PCI_AD20

PCI_AD18PCI_AD16

-PCI_FRAME

-PCI_TRDY

-PCI_STOP

PCI_PARPCI_AD15

PCI_AD13PCI_AD11

PCI_AD9

PCI_AD6PCI_AD4

PCI_ADPCI_AD0

PCI_-CBE0

PCI_33_CLK1

-PCI_PME-PCI_REQ0

+3.3V

+5V

+12V_VCC

+5V

+3.3VSUS

+3.3V -12V

R241 100R241 100

PCI1

EH0600F-DAW

PCI1

EH0600F-DAW

TRSTA1

+12VA2

TMSA3

TDIA4

+5VA5

INTAA6

INTCA7

+5VA8

RESERVED3A9

+5VA10

RESERVED4A11

GNDA12

GNDA13

3.3V_AUXA14

RSTA15

+5VA16

GNTA17

GNDA18

PMEA19

AD30A20

+3.3VA21

AD28A22

AD26A23

GNDA24

AD24A25

IDSELA26

+3.3VA27

AD22A28

AD20A29

GNDA30

AD18A31

AD16A32

+3.3VA33

FRAMEA34

GNDA35

TRDYA36

GNDA37

STOPA38

+3.3VA39

SDONEA40

SBOA41

GNDA42

PARA43

AD15A44

+3.3VA45

AD13A46

AD11A47

GNDA48

AD9A49

C/BE0A52

+3.3VA53

AD6A54

AD4A55

GNDA56

AD2A57

AD0A58

+5VA59

REQ64A60

+5VA61

+5VA62

-12VB1

TCKB2

GNDB3

TDOB4

+5VB5

+5VB6

INTBB7

INTDB8

PRSNT1B9

RESERVED1B10

PRSNT2B11

GNDB12

GNDB13

RESERVED2B14

GNDB15

CLKB16

GNDB17

REQB18

+5VB19

AD31B20

AD29B21

GNDB22

AD27B23

AD25B24

+3.3VB25

C/BE3B26

AD23B27

GNDB28

AD21B29

AD19B30

+3.3VB31

AD17B32

C/BE2B33

GNDB34

IRDYB35

+3.3VB36

DEVSELB37

GNDB38

LOCKB39

PERRB40

+3.3VB41

SERRB42

+3.3VB43

C/BE1B44

AD14B45

GNDB46

AD12B47

AD10B48

GNDB49

AD8B52

AD7B53

+3.3VB54

AD5B55

AD3B56

GNDB57

AD1B58

+5VB59

ACK64B60

+5VB61

+5VB62

Figure Figure Figure Figure 45454545: : : : PCI Connector ExamplePCI Connector ExamplePCI Connector ExamplePCI Connector Example


59

4.10.2.1.4.10.2.1.4.10.2.1.4.10.2.1. PCI Interface TopologyPCI Interface TopologyPCI Interface TopologyPCI Interface Topology

A topology example using three PCI slots on the carrier board connected to the COM Express module is

shown in Figure 46. Please note that the number of supported PCI slots will vary according to the design

of the carrier board.

The PCI control signals always require pull-up resistors, typically 4.7KΩ pull-up for +5V signaling; on the

carrier board to ensure that they do not float during the PCI idle state. Therefore each of the following

signals PCI_IRDY#, PCI_TRDY#, PCI_DEVSEL#, PCI_STOP#, PCI_PERR#, PCI_SERR#, PCI_FRAME# and

PCI_IRQ[D:A] requires a 4.7KΩ pull-up to +5V. The PCI_REQ[3:0]# and PCI_GNT[3:0]# signals need

4.7KΩ pull-up to +3.3V.

Figure Figure Figure Figure 46464646: : : : PCI Interface Topology ExamplePCI Interface Topology ExamplePCI Interface Topology ExamplePCI Interface Topology Example

4.10.2.2.4.10.2.2.4.10.2.2.4.10.2.2. PCI Layout and Routing RecommendationsPCI Layout and Routing RecommendationsPCI Layout and Routing RecommendationsPCI Layout and Routing Recommendations

Recommended layout rules for connecting PCI slots to the COM Express module are listed below:

Routing the PCI clock as single-ended 55Ω trace impedance and referencing to the ground plane is

recommended.

One source of the PCI clock comes from the COM Express connector, and if there are multiple

devices or slots implemented on the carrier board, a zero delay clock buffer is required to expend

the number of PCI clocks.

For PCI device-down application, the trace of PCI clock on carrier board should longer than 3.5″

from PCI device-up application.

Signal traces do not need to be matched; nor be serpentine in order to meet the minimum length

guidelines.

Routing to minimum is preferred.

Signal NameSignal NameSignal NameSignal Name PCI SlotsPCI SlotsPCI SlotsPCI Slots

PCI 1PCI 1PCI 1PCI 1 PCI 2PCI 2PCI 2PCI 2 PCI 3PCI 3PCI 3PCI 3

REQ Signals REQ0# REQ1# REQ2#

GNT Signals GNT0# GNT1# GNT2#

Table Table Table Table 42424242: : : : PCI slot connectionPCI slot connectionPCI slot connectionPCI slot connection


60

Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance No. of PCI SlotsNo. of PCI SlotsNo. of PCI SlotsNo. of PCI Slots Maximum Trace LengthMaximum Trace LengthMaximum Trace LengthMaximum Trace Length

L1L1L1L1 L2L2L2L2 L3L3L3L3

55Ω ± 10%

1 5″ ~ 10″ N/A N/A

2 5″ ~ 10″ 1″ N/A

3 5″ ~ 10″ 1″ 1″

Table Table Table Table 43434343: : : : PCI Interface Routing RequirementsPCI Interface Routing RequirementsPCI Interface Routing RequirementsPCI Interface Routing Requirements

Signal Signal Signal Signal GroupingGroupingGroupingGrouping TopologyTopologyTopologyTopology Routing LayerRouting LayerRouting LayerRouting Layer Accumulated Trace LengthAccumulated Trace LengthAccumulated Trace LengthAccumulated Trace Length

Single-ended Daisy Chain Top or Bottom < 10” (Route to minimum)

Table Table Table Table 44444444: : : : PCI Interface Layout GuidelinesPCI Interface Layout GuidelinesPCI Interface Layout GuidelinesPCI Interface Layout Guidelines

Signal Signal Signal Signal GroupingGroupingGroupingGrouping Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing) Spacing in Other GroupSpacing in Other GroupSpacing in Other GroupSpacing in Other Group

Single-ended 55Ω ± 10% 5 : 5 mil 20 mil

Table Table Table Table 45454545: : : : PCI Interface Trace PCI Interface Trace PCI Interface Trace PCI Interface Trace PropertiesPropertiesPropertiesProperties


The PCI trace length in VIA COM Express Type 2 modules is approximately 3.5”. Therefore, the PCI trace length

in carrier board should not be longer than 6”.


61

4.11. IDE Interface (Type 2 Only) VIA COM Express Type 2 modules provide the IDE interface signals for interfacing IDE drives. The IDE

interface is a disk drive interface that supports one independent enhanced IDE channel. And this IDE

channel can supports up to two enhanced IDE devices using the UltraDMA33 / 66 / 100 / 133 IDE devices

in a master or slave configuration.

4.11.1. IDE Signal Definition The corresponding IDE interface signals are defined in connector C-D.


IDE_D0 D7 IO Bidirectional data to or from IDE device

2

IDE_D1 C10 IO Bidirectional data to or from IDE device















IDE_A0 D13 O Address line to IDE device



IDE_IOW# D9 O Input/Output write line to IDE device

IDE_IOR# C14 O Input/Output read line to IDE device

IDE_REQ D8 I DMA request

IDE_ACK# D10 O DMA acknowledge

IDE_CS1# D16 O Chip select for 1F0h to 1FFh

IDE_CS3# D17 O Chip select for 30F0h to 3FFh

IDE_IORDY C13 I IDE device Input/Output ready input

IDE_RESET# D18 O Reset output to IDE device

IDE_IRQ D12 I Interrupt request from IDE device

IDE_CBLID# D77 I IDE cable type detector

Table Table Table Table 46464646: : : : IDE Signal DescriptionsIDE Signal DescriptionsIDE Signal DescriptionsIDE Signal Descriptions


62

4.11.2. IDE Reference Schematics

IDE_IRQ14

IDE_IORDY

-HD_LED

PRIMARY_28

IDE_REQ

IDE_D7

-IDE_CBLID

-HD_LED

IDE_D14

IDE_D12IDE_D11

IDE_D15

IDE_D8IDE_D9

IDE_D2

IDE_D0

IDE_D5 IDE_D10

IDE_D7IDE_D6

IDE_D1IDE_D13

IDE_D3IDE_D4

IDE_D[0:15]

-IDE_RST

IDE_A2-IDE_CS3

IDE_REQ-IDE_IOW-IDE_IORIDE_IORDY-IDE_ACKIDE_IRQ14IDE_A1IDE_A0

-IDE_CBLID

-SATA_LED

HD_LED

-IDE_CS1

+3.3V

+5V+5V

R544.7KR544.7K

D6 RLS4148D6 RLS4148

R95 10K/XR95 10K/X

R65 470R65 470


R484.7KR484.7K

R61 10K/XR61 10K/X

C45 0.01uFC45 0.01uF

R64 5.6K/XR64 5.6K/X

R72 4.7K/XR72 4.7K/X

IDE

IDE_CNTR_2X20

IDE

IDE_CNTR_2X20

13 4

2

5 67 8911

1012

13 141615

17 1819

22242628303234

21232527293133

36384039

3735

Figure Figure Figure Figure 47474747: : : : IDE ConnectorIDE ConnectorIDE ConnectorIDE Connector

-IDE_ACK

IDE_D8IDE_D0

IDE_IORDY

IDE_D10

-IDE_CS1

IDE_IRQ14

-IDE_IOW

IDE_A0

IDE_D2IDE_D1

-IDE_CBLID

IDE_D3

IDE_D13

-IDE_IOR

IDE_REQIDE_A1

-HD_LED

-CD1_CF

IDE_D7

-CF_SEL

IDE_D9

IDE_A2

-IDE_RST

-IDE_CS3

IDE_D4

IDE_D15

IDE_D12

-CD2_CF

IDE_D14IDE_D6

IDE_D11

IDE_D5

-CF_SEL

VCC_CF

VCC_CF

VCC_CF

VCC_CF

+5V +3.3VVCC_CF

V_CF_SEL

+3.3V

+5V

1 - 2

2 - 3

CF VOLTAGESLAVE

MS_CF_SEL

MASTER

CF MASTER/SLAVE

2 - 3

1 - 2

R81 0/XR81 0/X

C63 0.1uFC63 0.1uF

C67 0.1uFC67 0.1uF

R70 33R70 33

R74 10KR74 10K

R94 10KR94 10K

C66 0.1uFC66 0.1uFV_CF_SEL

HEADER_1X3

V_CF_SEL

HEADER_1X3

21

3

C91 0.1uFC91 0.1uF

R103 0R103 0

MS_CF_SEL

HEADER_1X3

MS_CF_SEL

HEADER_1X3

21

3

CF

0600000S35F

CF

0600000S35F

123

54

6789

10111213141516171819202122232425

26272829303132333435363738394041424344454647484950

G1

G2

G3

G4

G5

G6

M1

M2

Default: Pin (1,2) Close

Figure Figure Figure Figure 48484848: : : : CF Card SocketCF Card SocketCF Card SocketCF Card Socket


63

4.11.2.1.4.11.2.1.4.11.2.1.4.11.2.1. IDE Interface TopologyIDE Interface TopologyIDE Interface TopologyIDE Interface Topology

The topology example below shows the IDE interface signal from VIA COM Express Type 2 module

connected to two IDE devices: the IDE port and CF card socket. The master-slave setting configuration

should be applied if using the IDE connector and CF card socket at the same time.

Figure Figure Figure Figure 49494949: : : : IDE Devices Layout GuidelinesIDE Devices Layout GuidelinesIDE Devices Layout GuidelinesIDE Devices Layout Guidelines


64

4.11.2.2.4.11.2.2.4.11.2.2.4.11.2.2. IDE Supporting ModesIDE Supporting ModesIDE Supporting ModesIDE Supporting Modes

For IDE supporting modes, transfer rate and cable type; refer to Table 47. The transfer rate for each

device can support up to 133 MB/s to cover up to PIO Mode 4, Multiword DMA Mode 2 and Ultra DMA

Mode 6. An additional 80-conductor cable is required for all Ultra DMA modes higher than Mode 2. It is

interchangeable with the standard (40-conductor) cable for the remaining modes. There is no need for

new connectors on host or devices. Comparing to 40-conductor cable, 40 additional lines of the 80-

conductor cable interleaved between these original 40 signal/ground lines are all ground.

Supporting ModesSupporting ModesSupporting ModesSupporting Modes Transfer Rate (MB/s)Transfer Rate (MB/s)Transfer Rate (MB/s)Transfer Rate (MB/s) Cable TypeCable TypeCable TypeCable Type

PIO

Mode 0: 3.3

40-Conductor

Mode 1: 5.2

Mode 2: 8.3

Mode 3: 11.1

Mode 4: 16.7

Multiword DMA

Mode 0: 4.2

40-Conductor Mode 1: 13.3

Mode 2: 16.7

Ultra DMA

Mode 0: 16.7

40-Conductor Mode 1: 25

Mode 2: 33.3 (Ultra DMA 33)

Mode 3: 44.4 (Ultra DMA 66)

80-Conductor Mode 4: 66.6 (Ultra DMA 66)

Mode 5: 100 (Ultra DMA 100)

Mode 6: 133 (Ultra DMA 133)

Table Table Table Table 47474747: : : : IDE Supporting Modes, Transfer Rate and Cable TypeIDE Supporting Modes, Transfer Rate and Cable TypeIDE Supporting Modes, Transfer Rate and Cable TypeIDE Supporting Modes, Transfer Rate and Cable Type

4.11.2.3.4.11.2.3.4.11.2.3.4.11.2.3. IDE Cable DetectionIDE Cable DetectionIDE Cable DetectionIDE Cable Detection

The 80-conductor cable required by the Ultra DMA66 / 100 / 133 IDE interface is the major difference

from the 40-conductor cable of the former standard IDE interface (Ultra DMA33 specification below). For

the detection of the 80-conductor cable, pin 34 (-IDE_CBLID) of IDE connector may be used to provide a

signal state from an Ultra DMA66 / 100 / 133 device to COM Express module. The COM Express module

detects the cable type through BIOS operation with a 0.01 µF capacitor. The Ultra DMA mode 3, 4, 5 and

6 devices will drive –IDE_CBLID low. Then the drive will sample the –IDE_CBLID signal after releasing it.

The drive can detect the difference in rise times and it reports the cable type to the module BIOS when it

sends the IDENTIFY_DEVICE packet during system boot.

Figure Figure Figure Figure 50505050:::: IDE Cable Detection with 40IDE Cable Detection with 40IDE Cable Detection with 40IDE Cable Detection with 40----Conductor Ribbon CableConductor Ribbon CableConductor Ribbon CableConductor Ribbon Cable


65

Figure Figure Figure Figure 51515151: : : : IDE Cable Detection with 80IDE Cable Detection with 80IDE Cable Detection with 80IDE Cable Detection with 80----ConductoConductoConductoConductor Ribbon Cabler Ribbon Cabler Ribbon Cabler Ribbon Cable

4.11.2.4.4.11.2.4.4.11.2.4.4.11.2.4. IDE Layout and Routing RecommendationIDE Layout and Routing RecommendationIDE Layout and Routing RecommendationIDE Layout and Routing Recommendation

With the increase in speed, transmission line effects, signal crosstalk and bus timing issues emerge in the

IDE (PATA) related signals. And to eliminate the ringing and reflection caused by the transmission line

effect, proper routing, layout and impedance matching must be taken into account.

Recommended layout guidelines for IDE interface are listed below:

The IDE data lines for Ultra DMA mode operation should be routed as a bus.

All IDE signal lines should be as short as possible.

The IDE signals do not require series termination resistors, because the required series resistors are

present on the VIA COM Express Module.

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name Signal TypeSignal TypeSignal TypeSignal Type TopologyTopologyTopologyTopology

Address IDE_A[2:0] Single-ended Point-to-Point

Data

IDE_D[15:0]

Single-ended Point-to-Point IDE_IORDY

IDE_IOR#

IDE_IOW#

Control

IDE_ACK#

Single-ended Point-to-Point

IDE_CS1#

IDE_CS3#

IDE_REQ

IDE_IRQ

Table Table Table Table 48484848: : : : IDE Interface Signal Type IDE Interface Signal Type IDE Interface Signal Type IDE Interface Signal Type and Routing Topologyand Routing Topologyand Routing Topologyand Routing Topology

Signal GroupSignal GroupSignal GroupSignal Group Signal NameSignal NameSignal NameSignal Name TraceTraceTraceTrace

(Width : Spacing)(Width : Spacing)(Width : Spacing)(Width : Spacing) Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance



Address IDE_A[2:0] 5 : 10 55Ω 20 mil

Data

IDE_D[15:0]

5 : 10 55Ω 20 mil IDE_IORDY

IDE_IOR#

IDE_IOW#

Control

IDE_ACK#

5 : 10 55Ω 20 mil

IDE_CS1#

IDE_CS3#

IDE_REQ

IDE_IRQ

Table Table Table Table 49494949: : : : IDE Interface Trace PropertiesIDE Interface Trace PropertiesIDE Interface Trace PropertiesIDE Interface Trace Properties


66

Signal GSignal GSignal GSignal Grouprouprouproup Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer Trace MismatchTrace MismatchTrace MismatchTrace Mismatch AccumulateAccumulateAccumulateAccumulate


Address IDE_A[2:0] Top or Bottom < 5” < 0.5”

Data

IDE_D[15:0]

Top or Bottom < 5” < 0.5” IDE_IORDY

IDE_IOR#

IDE_IOW#

Control

IDE_ACK#

Top or Bottom < 5” < 0.5”

IDE_CS1#

IDE_CS3#

IDE_REQ

IDE_IRQ

Table Table Table Table 50505050: : : : IDE Interface Layout GuidelinesIDE Interface Layout GuidelinesIDE Interface Layout GuidelinesIDE Interface Layout Guidelines


The IDE trace length in VIA COM Express module is approximately 2.7”, therefore the IDE trace length in the

carrier board should not be longer than 2.3”.


67

4.12. SATA Interface The VIA COM Express modules support a SATA interface that complies with SATA Revision 1.0 and SATA

Revision 2.0. The VIA COM Express Type 2 module is designed to support up to four SATA ports, and the

VIA Type 6 and Type 10 modules can support up to two SATA ports. The SATA interface has a point-to-

point topology and it is configurable to support either SATA (3 Gbps) master port or SATA (1.5 Gbps)

master/slave port.

4.12.1. SATA Signal Definition The corresponding SATA interface signals are defined in the connector A-B.


SATA0_TX+ A16 O Serial ATA transmit output differential pair, channel 0

10, 6 and 2 SATA0_TX- A17 O

SATA0_RX+ A19 I Serial ATA receive input differential pair, channel 0

SATA0_RX- A20 I

SATA1_TX+ B16 O Serial ATA transmit output differential pair, channel 1

10, 6 and 2 SATA1_TX- B17 O

SATA1_RX+ B19 I Serial ATA receive input differential pair, channel 1

SATA1_RX- B20 I

SATA2_TX+ A22 O Serial ATA transmit output differential pair, channel 2

2 SATA2_TX- A23 O

SATA2_RX+ A25 I Serial ATA receive input differential pair, channel 2

SATA2_RX- A26 I

SATA3_TX+ B22 O Serial ATA transmit output differential pair, channel 3

2 SATA3_TX- B23 O

SATA3_RX+ B25 I Serial ATA receive input differential pair, channel 3

SATA3_RX- B26 I

SATA_ACT# A28 O SATA activity LED 10, 6 and 2

Table Table Table Table 51515151: : : : SATA SignalSATA SignalSATA SignalSATA Signal DescriptionsDescriptionsDescriptionsDescriptions

4.12.2. SATA Reference Schematics

Figure Figure Figure Figure 52525252: : : : SATA SATA SATA SATA ConnectorConnectorConnectorConnectorssss


68

4.12.2.1.4.12.2.1.4.12.2.1.4.12.2.1. SATA Layout and Routing RecommendationsSATA Layout and Routing RecommendationsSATA Layout and Routing RecommendationsSATA Layout and Routing Recommendations

Signal pairs should be referenced to the ground.

Each pair of SATA traces must be in parallel to each other with the same trace length and not

parallel with other signals to minimize crosstalk.

Receive and transmit group of traces do not need to be matched; nor be serpentine in order to

meet the minimum length guidelines.

Have all related SATA signals routed without interruptions on continuous ground planes. This is

recommended because any routing discontinuity or ground plane separation would impact signal

transmission.

For the SATA traces, do not route under magnetic devices or IC’s, oscillators, clock synthesizers,

crystals that use and/or duplicate clocks.

Signal trace with single-ended should maintain 55Ω impedance.

Figure Figure Figure Figure 53535353: : : : SATA Trace SpacingSATA Trace SpacingSATA Trace SpacingSATA Trace Spacing

GroupGroupGroupGroup Signal NameSignal NameSignal NameSignal Name DifferentialDifferentialDifferentialDifferential


Differential PairDifferential PairDifferential PairDifferential Pair

Trace MismatchTrace MismatchTrace MismatchTrace Mismatch

Differential TraceDifferential TraceDifferential TraceDifferential Trace


SATA0

SATA0_TX+

85Ω ± 10% < 5 mil 20 : 5 : 5 : 5 : 20 SATA0_TX-

SATA0_RX+

SATA0_RX-

SATA1

SATA1_TX+

85Ω ± 10% < 5 mil 20 : 5 : 5 : 5 : 20 SATA1_TX-

SATA1_RX+

SATA1_RX-

SATA2

SATA2_TX+

85Ω ± 10% < 5 mil 20 : 5 : 5 : 5 : 20 SATA2_TX-

SATA2_RX+

SATA2_RX-

SATA3

SATA3_TX+

85Ω ± 10% < 5 mil 20 : 5 : 5 : 5 : 20 SATA3_TX-

SATA3_RX+

SATA3_RX-

Table Table Table Table 52525252: : : : SATA Trace PropertiesSATA Trace PropertiesSATA Trace PropertiesSATA Trace Properties


69

GroupGroupGroupGroup Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer TopologyTopologyTopologyTopology AccumulatedAccumulatedAccumulatedAccumulated


SATA0

SATA0_TX+

Top or Bottom Point-to-Point < 1.5″ SATA0_TX-

SATA0_RX+

SATA0_RX-

SATA1

SATA1_TX+


SATA1_RX+

SATA1_RX-

SATA2

SATA2_TX+


SATA2_RX+

SATA2_RX-

SATA3

SATA3_TX+


SATA3_RX+

SATA3_RX-

Table Table Table Table 53535353: : : : SATA Routing, Topology and Layout GuidelinesSATA Routing, Topology and Layout GuidelinesSATA Routing, Topology and Layout GuidelinesSATA Routing, Topology and Layout Guidelines


1. The SATA signal trace length in VIA COM Express is approximately 1″, therefore the SATA trace length in

the carrier board should not be longer than 1.5″.

2. The placement of coupling capacitors is different between VIA COMe-8X80 / COMe-8X90 and COMe-9X90

COM Express module.

3. The coupling capacitors are already present in VIA COMe-8X80 and COMe-8X90 modules, but not in VIA

COMe-9X90 module. The coupling capacitor for COMe-9X90 module should be present in its carrier

board.


70

4.13. USB 2.0 and USB 3.0 Interface The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable Plug and Play serial

interface for adding external peripheral devices (e.g., game controllers, communication devices, and input

devices) on a single bus. The VIA COM Express Type 10, Type 6 and Type 2 modules can support up to

eight USB 2.0 interface ports and each USB port has its own over-current detect pin.

However, the VIA COM Express Type 6 module has four new USB interfaces designated only for

SuperSpeed USB or commonly knows as USB 3.0 interface. The pin-out of Type 6 uses the previously

assigned IDE interface in the pin-out of Type 2 for new USB 3.0 interface. Therefore, a Type 6 module

does not support the IDE interface anymore. Type 6 modules can support four USB 3.0 interface and eight

USB 2.0 interface signals. Type 10 and Type 2 use all eight USB interface for USB 2.0 signals.

4.13.1. USB 2.0 and USB 3.0 Signal Definition The corresponding USB 2.0 interface signals are defined in connector A-B, while the USB 3.0 interface

signals are implemented in connector C-D.

Signal NameSignal NameSignal NameSignal Name Pin #Pin #Pin #Pin # I/OI/OI/OI/O DDDDescriptionescriptionescriptionescription TypeTypeTypeType

USB0+ A46 IO USB 2.0 port 0, data+

10, 6 and 2

USB0- A45 IO USB 2.0 port 0, data-

USB1+ B46 IO USB 2.0 port 1, data+

USB1- B45 IO USB 2.0 port 1, data-













USB_0_1_OC# B44 I USB over-current sense, USB port 0 and 1

10, 6 and 2 USB_2_3_OC# A44 I USB over-current sense, USB port 2 and 3

USB_4_5_OC# B38 I USB over-current sense, USB port 4 and 5

USB_6_7_OC# A38 I USB over-current sense, USB port 6 and 7

Table Table Table Table 54545454: : : : USB 2.0 Signal DescriptionsUSB 2.0 Signal DescriptionsUSB 2.0 Signal DescriptionsUSB 2.0 Signal Descriptions


71


USB_SSTX0+ D4 O USB 3.0 transmit output differential pair, channel 0

6

USB_SSTX0- D3

USB_SSRX0+ C4 I USB 3.0 receive input differential pair, channel 0

USB_SSRX0- C3


USB_SSTX1- D6


USB_SSRX1- C6


USB_SSTX2- D9


USB_SSRX2- C9


USB_SSTX3- D12


USB_SSRX3- C12

Table Table Table Table 55555555: : : : USB USB USB USB 3333.0 Signal Descriptions.0 Signal Descriptions.0 Signal Descriptions.0 Signal Descriptions

4.13.2. USB 2.0 and USB 3.0 Reference Schematics

Figure Figure Figure Figure 54545454: : : : USB 2.0 (port 0 and port 1) InterfaceUSB 2.0 (port 0 and port 1) InterfaceUSB 2.0 (port 0 and port 1) InterfaceUSB 2.0 (port 0 and port 1) Interface


72

Figure Figure Figure Figure 55555555: : : : USB 3.0 (port 0 and port 1) InterfaceUSB 3.0 (port 0 and port 1) InterfaceUSB 3.0 (port 0 and port 1) InterfaceUSB 3.0 (port 0 and port 1) Interface

SS_TX1+SS_TX1-

SS_RX1+SS_RX1-

USB2_HP1+USB2_HP1-

+5V_DP0_1

SS_RX0+SS_RX0-

+5V_DP0_1

USB3_SSRX0+

SS_TX0-

USB3_SSTX0+_

USB3_SSTX0+_USB3_SSTX0-_

USB3_SSRX0-

USB3_SSTX0-_

SS_TX0+

USB2_HP0-

USB2_HP0+

USB2_DT0-USB2_DT0+

SS_RX0-

SS_TX0-

USB2_HP0+USB2_HP0-

SS_RX0+

SS_TX0+USB3_SSTX1-_

USB3_SSTX1-_

SS_TX1+

USB3_SSTX1+_

USB3_SSTX1+_

SS_TX1-

USB2_HP1+

USB2_HP1-

USB2_DT1-USB2_DT1+

SS_TX1+

USB2_HP1-

SS_TX1-

USB2_HP1+

USB2_HP0-USB2_HP0+

USB3_SSTX0+_

USB3_SSTX0-_ USB3_SSTX1-_

USB3_SSTX1+_

SS_RX0-

SS_RX0+

SS_TX0+SS_TX0-

SS_RX1-

SS_RX1+

SS_RX1-SS_RX1+

USB3_SSRX1-USB3_SSRX1+

USB2_DT0+

USB2_DT0-

USB2_DT1+

USB2_DT1-

USB3_SSTX0+

USB3_SSTX0-

USB3_SSTX1+

USB3_SSTX1-

USB3_SSRX0+

USB3_SSRX0-

USB3_SSRX1-

USB3_SSRX1+

+5VDUAL

Co-Layout Co-Layout

Note: Please place those parts close to USB Connector

+

CE8100uF

+

CE8100uF

12

C98 0.1uFC98 0.1uF

D19

AZ

C199-0

2S

.R7G

D19

AZ

C199-0

2S

.R7G

1 23

RN18 0/XRN18 0/X

1 23 4

L15 ACM2012-900-2P-T002L15 ACM2012-900-2P-T002

1 4

32

L18 ACM2012-900-2P-T002L18 ACM2012-900-2P-T002

1 4

32

RN16 0/XRN16 0/X

1 23 4

+

CE7100uF

+

CE7100uF

12

L16 ACM2012-900-2P-T002L16 ACM2012-900-2P-T002

1 4

32

L17 ACM2012-900-2P-T002L17 ACM2012-900-2P-T002

1 4

32

RN20 0/XRN20 0/X

1 23 4

RN19 0/XRN19 0/X

1 23 4

USB3_LANA

PU2B1EK-P6BB

USB3_LANA

PU2B1EK-P6BB

U9U8U7U6

U18U17U16U15

G1 G3G2

U5

U1U2U3U4

U14

U10U11U12U13

G4

PS5 2APS5 2A12

C97 0.1uFC97 0.1uF

RN21 0/XRN21 0/X

1 23 4

D18L15ESDL5V0NA-4D18L15ESDL5V0NA-4

Line-11

Line-22

GND3

Line-34

Line-45

NC6

NC7

NC9

NC10

L20 ACM2012-900-2P-T002L20 ACM2012-900-2P-T002

1 4

32

D17L15ESDL5V0NA-4

D17L15ESDL5V0NA-4

Line-11

Line-22

GND3

Line-34

Line-45

NC6

NC7

NC9

NC10

C101 0.1uFC101 0.1uF

C9210uF /XC9210uF /X

RN17 0/XRN17 0/X

1 23 4

L19 ACM2012-900-2P-T002L19 ACM2012-900-2P-T002

1 4

32

FB10BLM18PG300SN1D FB10BLM18PG300SN1D

C99 0.1uFC99 0.1uF

D20

AZ

C199-0

2S

.R7G

D20

AZ

C199-0

2S

.R7G

1 23


73

4.13.2.1.4.13.2.1.4.13.2.1.4.13.2.1. USB Layout and Routing RecommendationsUSB Layout and Routing RecommendationsUSB Layout and Routing RecommendationsUSB Layout and Routing Recommendations

The layout guidelines for the USB data lines are listed below. And a routing example for two pairs of USB

data buses is shown in Figure 58.

The differential pair signals should be all referenced to ground.

Differential pair route in parallel and in equal length.

The amount of vias and corners used for the USB 2.0 and USB 3.0 signal layout should be minimized;

this is to prevent the occurrence of reflection and impedance changes.

Each pair of USB data lines is required to be parallel to each other with the same trace length (see

Figure 58), and not parallel with other signals to minimize crosstalk.

Separate the signal traces into similar groups and route similar signal traces together. In addition, it

is recommended to have differential pairs routed together on the motherboard.

Control trace signals (USB_0_1_OC#, USB_2_3_OC#, USB_4_5_OC# and USB_0_6_7_OC#)

impedance should maintain 55Ω ± 10%.

For the USB traces, do not route them under oscillators, crystals, clock synthesizers, magnetic

devices or IC’s which could be using duplicate clocks.

Figure Figure Figure Figure 56565656: : : : USB 2.0 Differential Signal Layout RecommendationsUSB 2.0 Differential Signal Layout RecommendationsUSB 2.0 Differential Signal Layout RecommendationsUSB 2.0 Differential Signal Layout Recommendations

Figure Figure Figure Figure 57575757: : : : USB 3.0 Differential Signal Layout RecommendationsUSB 3.0 Differential Signal Layout RecommendationsUSB 3.0 Differential Signal Layout RecommendationsUSB 3.0 Differential Signal Layout Recommendations

Figure Figure Figure Figure 58585858: : : : USB Differential Signal Routing ExampleUSB Differential Signal Routing ExampleUSB Differential Signal Routing ExampleUSB Differential Signal Routing Example


74

Figure Figure Figure Figure 59595959: : : : USB 2.0 and 3.0 Trace SpacingUSB 2.0 and 3.0 Trace SpacingUSB 2.0 and 3.0 Trace SpacingUSB 2.0 and 3.0 Trace Spacing

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Termination OptionTermination OptionTermination OptionTermination Option Signal TypeSignal TypeSignal TypeSignal Type TopologyTopologyTopologyTopology

Differential

Data Pair

Port 0 USB0+, USB0-

None Differential

Data I/O Pairs Point to Point

Port 1 USB1+, USB1-

Port 2 USB2+, USB2-

Port 3 USB3+, USB3-

Port 4 USB4+, USB4-

Port 5 USB5+, USB5-

Port 6 USB6+, USB6-

Port 7 USB7+, USB7-

Control

USB_0_1_OC#

None Input Signals Point to Point USB_2_3_OC#

USB_4_5_OC#

USB_6_7_OC#

Table Table Table Table 56565656: : : : USB 2.0 Interface Routing Topology and Signal TypeUSB 2.0 Interface Routing Topology and Signal TypeUSB 2.0 Interface Routing Topology and Signal TypeUSB 2.0 Interface Routing Topology and Signal Type

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer Term StubTerm StubTerm StubTerm Stub

LengthLengthLengthLength





Differential

Data Pair

Port 0 USB0+, USB0-

Top or Bottom < 1″ < 0.005″

Route to

minimum

(or < 9″)

Port 1 USB1+, USB1-

Port 2 USB2+, USB2-

Port 3 USB3+, USB3-

Port 4 USB4+, USB4-

Port 5 USB5+, USB5-

Port 6 USB6+, USB6-

Port 7 USB7+, USB7-

Control

USB_0_1_OC#

Top or Bottom < 1″ - Route to

Minimum

USB_2_3_OC#

USB_4_5_OC#

USB_6_7_OC#

Table Table Table Table 57575757: : : : USB 2.0 Interface Layout GuidelinesUSB 2.0 Interface Layout GuidelinesUSB 2.0 Interface Layout GuidelinesUSB 2.0 Interface Layout Guidelines


75

Signal NameSignal NameSignal NameSignal Name Signal TypeSignal TypeSignal TypeSignal Type Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance



S : W : S1 : W : SS : W : S1 : W : SS : W : S1 : W : SS : W : S1 : W : S



USB0+, USB0-

Differential 90Ω ± 15% 20 : 6 : 7 : 6 : 20 < 0.03″

USB1+, USB1-

USB2+, USB2-

USB3+, USB3-

USB4+, USB4-

USB5+, USB5-

USB6+, USB6-

USB7+, USB7-

USB_0_1_OC#

Single-ended 55Ω ± 10% 5 : 10 < 0.02″ USB_2_3_OC#

USB_4_5_OC#

USB_6_7_OC#

Table Table Table Table 58585858: : : : USB 2.0 Trace PropertiesUSB 2.0 Trace PropertiesUSB 2.0 Trace PropertiesUSB 2.0 Trace Properties

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Termination Termination Termination Termination

OptionOptionOptionOption Signal TypeSignal TypeSignal TypeSignal Type TopologyTopologyTopologyTopology

Differential

Data Pair

Port 0 USB3_SSTX0+, USB3_SSTX0-

None Differential

Data I/O Pairs Point to Point

USB3_SSRX0+, USB3_SSRX0-







Control USB_0_1_OC#

None Input Signals Point to Point USB_2_3_OC#

Table Table Table Table 59595959: : : : USB 3.0 Interface Routing Topology and Signal TypeUSB 3.0 Interface Routing Topology and Signal TypeUSB 3.0 Interface Routing Topology and Signal TypeUSB 3.0 Interface Routing Topology and Signal Type

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Routing Routing Routing Routing

LayerLayerLayerLayer

Term StubTerm StubTerm StubTerm Stub

LengthLengthLengthLength





Differential

Data Pair


Top or

Bottom < 1″ < 0.005″

Route to

Minimum

(or < 3″)








Control USB_0_1_OC# Top or

Bottom < 1″ -

Route to

minimum USB_2_3_OC#

Table Table Table Table 60606060: : : : USB 3.0 Interface Layout GuidelinesUSB 3.0 Interface Layout GuidelinesUSB 3.0 Interface Layout GuidelinesUSB 3.0 Interface Layout Guidelines


76

Signal NameSignal NameSignal NameSignal Name Signal TypeSignal TypeSignal TypeSignal Type Trace Trace Trace Trace




S : W : S1 : W : SS : W : S1 : W : SS : W : S1 : W : SS : W : S1 : W : S



USB3_SSTX0+, USB3_SSTX0-

Differential 85Ω ± 15% 20 : 5 : 5 : 5 : 20 < 0.03″








USB_0_1_OC# Single-ended 55Ω ± 10% 5 : 10 < 0.02″

USB_2_3_OC#

Table Table Table Table 61616161: : : : USB 3.0 Trace PropertiesUSB 3.0 Trace PropertiesUSB 3.0 Trace PropertiesUSB 3.0 Trace Properties


The USB 2.0 and USB 3.0 trace length in VIA COM Express module is approximately 2.5″, therefore the USB 2.0

and USB 3.0 trace length in the carrier board should not longer than 9″ and 3” respectively.


77

4.14. Audio Interface The Audio Interface is a link between the VIA COM Express modules and Audio Codec that supports the

AC’97 and High Definition Audio in the carrier board design. This section contains AC’97 and High

Definition Audio layout and routing information. Although codec for AC’97 and High Definition Audio use

the same signal interface, these two are different and cannot be used at the same time on the board.

4.14.1. Audio Signal Definition The corresponding audio interface pin-out signals are defined in connector A-B.


AC/HDA_RST# A30 O Codec reset

10, 6 and 2

AC/HDA_SYNC A29 O Serial Sample Rate Synchronization

AC/HDA_BITCLK A32 O Bit clock for Codec

AC/HDA_SDOUT A33 O Serial Data Output

AC/HDA_SDIN0 B30 I Serial Data Input Stream from Codec 1



Table Table Table Table 62626262: : : : Audio IAudio IAudio IAudio Interface Signal Descriptionsnterface Signal Descriptionsnterface Signal Descriptionsnterface Signal Descriptions

4.14.2. Audio Reference Schematics

LINE-R

CD_R

SD_IN0

MIC2_FR_L

AFILT4

MIC2_FR_R

MIC1_LMIC1_R

LINE-L

JD2

CD_L

MIC2_FRR

BIT_CLK

FNT_IO_SENSE

PC_BEEP

MIC2_FRL

MIC1_VREFO_LMIC1_VREFO_R

MIC2_VREFO

JDREF

VCAP

U19_45U19_46

U19_43U19_44

U19_41U19_39

U19_35U19_36

LINE2_RLINE2_L

HP_OUT_RHP_OUT_L

JD1

AUDIO_VREF

AUDIO_VREF

JDREF

VREFOUT-C_L

VCAP

MIC2_JD

LINE2_JD

LINE2_VREFO

LINE1_IN_R

AZ_SDOUT

LINE1_IN_L

AZ_SDIN0

AZ_BITCLK-AZ_RST

AZ_SYNC

MIC1_VREFO_L

MIC1_RE_LMIC1_RE_R

SIDESURR_JDCEN_JD

FRONT_JDLINE1_JDMIC1_JDSURR_JD

SIDESURR_OUT_LSIDESURR_OUT_R

FRONT_OUT_LFRONT_OUT_R

LFE_OUTCEN_OUT

SURR_OUT_LSURR_OUT_R

CD_IN_GNDCD_IN_L

CD_IN_R

MIC1_VREFO_R

SPDIFO

DVP_SPDIF_HDMI

+3.3VSUS

+3.3V

VDD3_AUDIO

AGND

AGND

AVDD5 +5VAUDIO

AGND

AGND

AGND

AGND

AGND

+5VDUAL

Close to VT1708S

connect standby power(for pop noise)

R238 33R238 33

R198 0 /XR198 0 /X

+CE15 10uF+CE15 10uF12

+CE17 10uF+CE17 10uF12

R245 0R245 0

R212 39.2K_1%R212 39.2K_1%

FB37QT1608RL300LF

FB37QT1608RL300LF

+CE30 10uF+CE30 10uF1 2

C2360.1uFC2360.1uF

+CE37 10uF+CE37 10uF1 2

+CE34 10uF+CE34 10uF1 2

+

CE2210uF

+

CE2210uF

12

R195 20K_1%R195 20K_1%

C216 1uFC216 1uF

R239 22R239 22

R258 20K_1%/XR258 20K_1%/X

C239 10uF/XC239 10uF/X

C241 100pFC241 100pF

R210 33R210 33

R244 33R244 33

+CE13 10uF+CE13 10uF12

R216 33R216 33

C2090.1uFC2090.1uF

+CE19 220uF+CE19 220uF12

R211 20K_1%R211 20K_1%

U20

VT1708S/VT1818S/VT1828S

U20

VT1708S/VT1818S/VT1828S

DVDD11

SENSEA13

S/PDIF_TX1/GPIO02

DVSS14

SDATA_OUT5

BIT_CLK6

DVSS27

SDATA_IN8

DVDD29

SYNC10

RESET11

PC_BEEP12

SENSEB34

PORT-E/Fr.HP-L14

PORT-E/Fr.HP-R15

PORT-F/Fr.MIC1-L16

PORT-F/Fr.MIC2-R17

CD_L18

CD_GND19

CD_R20

PORT-B/MIC1-L21

PORT-B/MIC2-R22

PORT-C/LINE IN-L23

PORT-C/LINE IN-R24

AVDD125

AVSS126

NC37

VREFOUT-E31

CAP33

GPIO13

VREFOUT-C_L29

VREFOUT-F_L30

VREFOUT-B_L28

VREFOUT-B_R32

FRONT-OUT-L/PORT-D35

FRONT-OUT-R/PORT-D36

VREF27

AVDD238

SURR-OUT-L/PORT-A39

SURR-OUT-R/PORT-A41

JDREF40

AVSS242

CEN-OUT/PORT-G43

LEE-OUT/PORT-G44

SIDESURR-OUT-R/PORT-H46

SIDESURR-OUT-L/PORT-H45

EAPD47

S/PDIF_Tx048

FB40QT1608RL300LF /X


C234 0.1uFC234 0.1uF

R205 10K_1%R205 10K_1%

+CE31 10uF+CE31 10uF1 2

C214 2.2uFC214 2.2uF

FB43 QT1608RL060LF/XFB43 QT1608RL060LF/X

+

CE3210uF

+

CE3210uF

12

+CE23 10uF+CE23 10uF1 2

R233 22R233 22

C2080.1uFC2080.1uF

R257 5.1K_1%R257 5.1K_1%

R223 33R223 33

R199 39.2K_1%R199 39.2K_1%

FB41 0FB41 0

C217 1uFC217 1uF

+CE14 10uF+CE14 10uF12

R214 10K_1%R214 10K_1%

R209 33R209 33

R228 33R228 33+CE20 220uF+CE20 220uF12

C204 0.1uFC204 0.1uF

R204 5.1K_1%R204 5.1K_1%

FB24QT1608RL300LF

FB24QT1608RL300LF

C23110uF/XC23110uF/X

+CE25 10uF+CE25 10uF1 2

+

CE3610uF

+

CE3610uF

12

+CE28 10uF+CE28 10uF1 2

+CE27 10uF+CE27 10uF1 2

C218 100pFC218 100pF

+

CE2610uF

+

CE2610uF

12

C229 22pFC229 22pF+CE35 10uF+CE35 10uF1 2

C244 100pFC244 100pF

C203 0.1uFC203 0.1uF

+CE18 10uF+CE18 10uF12

+CE16 10uF+CE16 10uF12

C227 0.1uFC227 0.1uF

C233 10pFC233 10pF

R249 33R249 33

R213 5.1K_1%R213 5.1K_1%

C2420.1uFC2420.1uF

Figure Figure Figure Figure 60606060: : : : HD Audio Codec Implementation ExampleHD Audio Codec Implementation ExampleHD Audio Codec Implementation ExampleHD Audio Codec Implementation Example


78

4.14.2.1.4.14.2.1.4.14.2.1.4.14.2.1. Audio Layout and Routing RecommendationsAudio Layout and Routing RecommendationsAudio Layout and Routing RecommendationsAudio Layout and Routing Recommendations

Route the analog and digital trace signals as far as possible from each other to prevent noise.

Route the clock trace away from any analog input and voltage reference pins.

Isolate the codec or put away from any major current path or ground bounce.

Fill with copper the regions between the analog traces and attached it to the analog ground.

Fill with copper the regions between the digital traces and attached it to the digital ground.

Use the metal film resistors for all resistors in the signal path.

Grouped analog parts in one area and all digital parts in another area.

Route traces as short as possible.

Figure Figure Figure Figure 61616161: : : : Single OnSingle OnSingle OnSingle On----Board High Definition Audio Codec Implementation ExampleBoard High Definition Audio Codec Implementation ExampleBoard High Definition Audio Codec Implementation ExampleBoard High Definition Audio Codec Implementation Example

Figure Figure Figure Figure 62626262: : : : Fully OnFully OnFully OnFully On----Board High Definition Audio Codec Implementation ExampleBoard High Definition Audio Codec Implementation ExampleBoard High Definition Audio Codec Implementation ExampleBoard High Definition Audio Codec Implementation Example


79

Signal NameSignal NameSignal NameSignal Name Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing) Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance Spacing to OSpacing to OSpacing to OSpacing to Other Groupther Groupther Groupther Group

AC/HDA_RST#

5 : 10 55Ω ± 10% - AC/HDA_SYNC

AC/HDA_SDOUT

AC/HDA_SDIN0

5 : 10 55Ω ± 10% - AC/HDA_SDIN1

AC/HDA_SDIN2

AC/HDA_BITCLK 5 : 20 55Ω ± 10% -

Table Table Table Table 63636363: : : : Trace Properties for Audio InterfaceTrace Properties for Audio InterfaceTrace Properties for Audio InterfaceTrace Properties for Audio Interface

SignaSignaSignaSignal Namel Namel Namel Name Routing LayerRouting LayerRouting LayerRouting Layer TopologyTopologyTopologyTopology Accumulated Trace LengthAccumulated Trace LengthAccumulated Trace LengthAccumulated Trace Length

AC/HDA_RST#

Top Layer Point to Point < 17″ AC/HDA_SYNC

AC/HDA_SDOUT

AC/HDA_SDIN0

Top Layer Point to Point < 17″ AC/HDA_SDIN1

AC/HDA_SDIN2

AC/HDA_BITCLK Top Layer Point to Point < 17″

Table Table Table Table 64646464: : : : Topology and Layout Guidelines for Audio InterfaceTopology and Layout Guidelines for Audio InterfaceTopology and Layout Guidelines for Audio InterfaceTopology and Layout Guidelines for Audio Interface


1. The audio trace length in VIA COM Express module is approximately 3″, therefore the audio trace length in

the carrier board should not be longer than 14″.

2. The values of the series resistors depend on the design, and should be verified for optimized timing and

signal quality.


80

4.15. System Management Bus (SMBus) Interface The System Management Bus (SMBus) is a two-wire interface, which uses I²C bus to make a

communication between the COM Express module and the rest of the system.

4.15.1. System Management Bus Signal Definition The corresponding SMBus interface pin-out signals are defined in connector row B.


SMB_CLK B13 IO SMBus bi-directional clock line

10, 6 and 2 SMB_DAT B14 IO SMBus bi-directional data line

SMB_ALERT# B15 I SMBus Alert

Table Table Table Table 65656565: : : : SMBus Interface Signal DescriptionsSMBus Interface Signal DescriptionsSMBus Interface Signal DescriptionsSMBus Interface Signal Descriptions

Figure Figure Figure Figure 63636363: : : : SMBus Interface ExampleSMBus Interface ExampleSMBus Interface ExampleSMBus Interface Example

4.15.1.1.4.15.1.1.4.15.1.1.4.15.1.1. SSSSMBus Layout and Routing RecommendationsMBus Layout and Routing RecommendationsMBus Layout and Routing RecommendationsMBus Layout and Routing Recommendations

Signal NameSignal NameSignal NameSignal Name Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing)Trace (Width : Spacing) Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance NoteNoteNoteNote

SMB_CK 5 : 10 55Ω ± 10% Route to minimum

whenever possible SMB_DAT 5 : 10 55Ω ± 10%

SMB_ALERT# 5 : 10 55Ω ± 10%

Table Table Table Table 66666666: : : : Trace Properties for SMBus InterfaceTrace Properties for SMBus InterfaceTrace Properties for SMBus InterfaceTrace Properties for SMBus Interface

Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer TopologyTopologyTopologyTopology Accumulated Trace LengthAccumulated Trace LengthAccumulated Trace LengthAccumulated Trace Length

SMB_CK Top Layer Point to Point -

SMB_DAT Top Layer Point to Point -

SMB_ALERT# Top Layer Point to Point -

Table Table Table Table 67676767: : : : Topology and Layout Guidelines for SMBus InterfaceTopology and Layout Guidelines for SMBus InterfaceTopology and Layout Guidelines for SMBus InterfaceTopology and Layout Guidelines for SMBus Interface


81

4.16. LAN Interface The LAN interface supports a 10/100Mbps and 1000Mbps (Gigabit Ethernet), and complies with the IEEE

standard for 10BASE-T, 100BASE-T, 1000BASE-T, TX and T4 Ethernet interfaces. It consists of four

differential signals and control signals for activity link indicators. These signals can be used to connect to

the RJ-45 connector with integrated or external isolation magnetic (transformer) on the carrier board.

4.16.1. LAN Signal Definition The corresponding LANs interface pin-out signals are defined in connector A-B.


GBE0_MDI0+ A13 IO Media Dependent Interface differential pair 0

10, 6 and 2

GBE0_MDI0- A12


GBE0_MDI1- A9


GBE0_MDI2- A6


GBE0_MDI3- A2

GBE0_CTREF A14 Reference voltage for carrier board Ethernet

channel 0 magnetic center tap

GBE0_LINK100# A4 O Ethernet controller 0 100Mbps link indicator

GBE0_LINK1000# A5 O Ethernet controller 0 1000Mbps link indicator

GBE0__ACT# B2 O Ethernet controller 0 activity indicator

Table Table Table Table 68686868: : : : LANLANLANLAN Signal DescriptionsSignal DescriptionsSignal DescriptionsSignal Descriptions

4.16.2. LAN Reference Schematics

Figure Figure Figure Figure 64646464: : : : LAN Implementation ExampleLAN Implementation ExampleLAN Implementation ExampleLAN Implementation Example


82

4.16.2.1.4.16.2.1.4.16.2.1.4.16.2.1. LAN LayoLAN LayoLAN LayoLAN Layout and Routing Recommendationsut and Routing Recommendationsut and Routing Recommendationsut and Routing Recommendations

This section shows the layout recommendations of both transmit and receive differential data pairs and

single-ended control signal between the COM Express module and the transformer (magnetic module),

between the transformer and RJ-45 connector, and between the COM Express module and RJ-45

connector with integrated magnetic module.

Figure Figure Figure Figure 65656565: : : : 10/100 Ethernet Layout Recommendation (integrated magnetic module)10/100 Ethernet Layout Recommendation (integrated magnetic module)10/100 Ethernet Layout Recommendation (integrated magnetic module)10/100 Ethernet Layout Recommendation (integrated magnetic module)

Figure Figure Figure Figure 66666666: : : : 10/100 Ethernet Layout Recommendation (external magnetic module)10/100 Ethernet Layout Recommendation (external magnetic module)10/100 Ethernet Layout Recommendation (external magnetic module)10/100 Ethernet Layout Recommendation (external magnetic module)


1. It is recommended to use termination circuits for the unused pin at the RJ-45 connector and for wire-side

center-taps of the magnetic module. Improper usage (or lack of usage) of the termination circuits for those

unused pins at the RJ-45 connector wire-side center taps of the transformer will cause emissions and long

cable noise problems related to other IEEE conformance issues.

2. The LAN magnetic should be placed on the carrier board.


83

Figure Figure Figure Figure 67676767: : : : Gigabit Ethernet Layout Recommendations (integrated magnetic module)Gigabit Ethernet Layout Recommendations (integrated magnetic module)Gigabit Ethernet Layout Recommendations (integrated magnetic module)Gigabit Ethernet Layout Recommendations (integrated magnetic module)

Figure Figure Figure Figure 68686868: : : : Gigabit Ethernet Layout Recommendations (external magnetic module)Gigabit Ethernet Layout Recommendations (external magnetic module)Gigabit Ethernet Layout Recommendations (external magnetic module)Gigabit Ethernet Layout Recommendations (external magnetic module)


If the Gigabit Ethernet implementation is not being use, the pins GBE_MDI02+, GBE_MDI02-, GBE_MDI03+ and

GBE_MDI03- should not be connected.


84

4.16.3. LAN Layout and Routing Recommendations Route differential pairs close together and away from other signals.

Route any other trace parallel to one of the differential trace.

Keep trace length within each differential pair equal.

Keep proper impedance between two traces within a differential pair.

Each differential pair of signals is required to be paralleled to each other with the same trace length

(Tolerance ±50 mil) on the component (top) layer and to be paralleled to a respective ground

plane. The length difference between the shortest and longest pairs should be less than 200 mil.

The accumulated trace length of differential signals pair between the VIA COM Express module

pin-out connector and magnetic module should be less than 7″.

The accumulated trace length of differential signals pair between the external magnetic module and

RJ-45 connector should be less than 1″. Isolate ground plane and connect to chassis earth.

Keep each differential pair on the same plane.

To prevent any noise from injecting into the differential pairs, be sure to keep digital signals or other

signals away from the differential signals.

The external magnetic module should be placed close to the RJ-45 connector to limit EMI

emissions.

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Trace ImpedanceTrace ImpedanceTrace ImpedanceTrace Impedance TraceTraceTraceTrace

(Width : Spacing)(Width : Spacing)(Width : Spacing)(Width : Spacing) NoteNoteNoteNote

Differential Pair

GBE0_MDI0+ 100Ω ± 15%

differential 20 : 5 : 8 : 5 : 20

Route traces as

short as possible

GBE0_MDI0-

GBE0_MDI1+ 100Ω ± 15%

differential 20 : 5 : 8 : 5 : 20

GBE0_MDI1-

GBE0_MDI2+ 100Ω ± 15%

differential 20 : 5 : 8 : 5 : 20

GBE0_MDI2-

GBE0_MDI3+ 100Ω ± 15%

differential 20 : 5 : 8 : 5 : 20

GBE0_MDI3-

Single-ended

GBE0_LINK100# 55Ω ± 10% 5 : 10

GBE0_LINK1000# 55Ω ± 10% 5 : 10

GBE0_ACT# 55Ω ± 10% 5 : 10

Table Table Table Table 69696969: : : : Trace Properties for LAN InterfaceTrace Properties for LAN InterfaceTrace Properties for LAN InterfaceTrace Properties for LAN Interface

Signal GroupingSignal GroupingSignal GroupingSignal Grouping Signal NameSignal NameSignal NameSignal Name Routing LayerRouting LayerRouting LayerRouting Layer TopologyTopologyTopologyTopology Accumulated Accumulated Accumulated Accumulated


Differential Pair

GBE0_MDI0+

Top Layer Point to Point < 8″

GBE0_MDI0-

GBE0_MDI1+

GBE0_MDI1-

GBE0_MDI2+

GBE0_MDI2-

GBE0_MDI3+

GBE0_MDI3-

Single-ended

GBE0_LINK100#

Top Layer Point to Point < 8″ GBE0_LINK1000#

GBE0_ACT#

Table Table Table Table 70707070: : : : Topology and Layout Routing Guidelines for LAN InterfaceTopology and Layout Routing Guidelines for LAN InterfaceTopology and Layout Routing Guidelines for LAN InterfaceTopology and Layout Routing Guidelines for LAN Interface


85

Appendix A.Appendix A.Appendix A.Appendix A. Video Video Video Video CombinationsCombinationsCombinationsCombinations andandandand Display Display Display Display

Device SupportDevice SupportDevice SupportDevice Support The video combinations and the supported display devices listed below are only for COM.0 R1.0. These

combinations are supported when using a VIA COM Express Type 2 module such as COMe-8X80.

Display Device ConfigurationsDisplay Device ConfigurationsDisplay Device ConfigurationsDisplay Device Configurations

Request PriorityRequest PriorityRequest PriorityRequest Priority DACs ConnectionDACs ConnectionDACs ConnectionDACs Connection Integrated LVDS ConnectionIntegrated LVDS ConnectionIntegrated LVDS ConnectionIntegrated LVDS Connection DVP1 ConnectionDVP1 ConnectionDVP1 ConnectionDVP1 Connection

Configuration 1 CRT 1-Ch LVDS or 2-Ch LVDS DVI (VT1632A)

Configuration 2 CRT NC DVI (VT1632A)

Configuration 3 CRT 1-Ch LVDS or 2-Ch LVDS HDMI (AD9389/AD9889)

Configuration 4 CRT NC HDMI (AD9389/AD9889)

Configuration 5 CRT 1-Ch LVDS or 2-Ch LVDS TV (VT1625)

Configuration 6 CRT NC TV (VT1625)

Configuration 7 CRT NC 18 bits TTL Panel


HDMI® cannot support interlace mode.

Two Panel ConfigurationTwo Panel ConfigurationTwo Panel ConfigurationTwo Panel Configurationssss

Request PriorityRequest PriorityRequest PriorityRequest Priority DACs ConnectionDACs ConnectionDACs ConnectionDACs Connection Integrated LVDS ConnectionIntegrated LVDS ConnectionIntegrated LVDS ConnectionIntegrated LVDS Connection DVP1 ConnectionDVP1 ConnectionDVP1 ConnectionDVP1 Connection

Configuration 8 CRT 1-Ch LVDS or 2-Ch LVDS NC

Configuration 9 CRT 2-Ch LVDS LVDS (VT1636)


1. The two panels must share the same timing specification and resolution.

2. Only supports scaling on the primary LCD panel.


86

Appendix B.Appendix B.Appendix B.Appendix B. COMEDB4, COMEDB2 COMEDB4, COMEDB2 COMEDB4, COMEDB2 COMEDB4, COMEDB2 andandandand

COMEDB1 Reference SchematicsCOMEDB1 Reference SchematicsCOMEDB1 Reference SchematicsCOMEDB1 Reference Schematics The VIA COMEDB4, COMEDB2 and COMEDB1 are the carrier board reference schematics design using

the VIA COMe-9X90, COMe-8X90 and COMe-8X80 COM Express modules.

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title

Size Document Number Rev

Date: Sheet of

VIA TECHNOLOGIES INC.

COMEDB4

BLOCK DIAGRAM

1 27Thursday, August 01, 2013

AC

Title


Date: Sheet of


COMEDB4

BLOCK DIAGRAM


AC

Title


Date: Sheet of


COMEDB4

BLOCK DIAGRAM


AC

COMEBD4 Block Diagram

ROW A-B ROW C-D

LPC BUS

LPC SIOF71869ED

DDI2

Display Port 2

VIA Confidential

SPI BIOSSPI BUS

BIOS_DIS1#

2 X USB 3.0USB 3.0

DDI1

Display Port 1

2 X Serial2 x Serial Interface Signals

HDA LINK

HD CodecVT2021

SATA

2 X SATA

6 X USB 2.0USB 2.0

4 X PCIE X1PCIE

LVDSLVDS

GbE LANLAN

RTL8111G

VT1636 / CH7305

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWRBTN#

PWR_OK [4,24]

SUS_S3#, SUS_S4#, SUS_S5#

WAKE1#

SYS_RESET#

CB_RESET#

GPOn (4)

GPIn (4)

Title


Date: Sheet of


COMEDB4

System BLOCK DIAGRAM


AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

COME9X90COM-e Type 6 Module

VGA connector

LVDS connectorDVP Port

HDA CODECVT2021

HDA

SPKR

X-FormerEthernet

Ethernet Port Eth Ctrlr & PhyRTL8111G

USB 2.0 (6)

USB2_2/3 pin header

USB2_0/1 pin header

Mini-PCI-e socketPCI-e x1

PCI-e x1 Slot

PCI-e x1 Slot

PCI-e x1

DDI2DP connector 2

SMBUS

I2C Bus

SMBUS pin header

I2C Bus pin header

FLASH BIOS

PCI-e x1

PCI-e x1

USB3_LAN connector

FLASH BIOS

SPI BusLP

C B

us

Super I/O

F71869ED

Serial Ports (2)COM 1 connector

COM 2 pin header

LPT pin headerParallel Port

DIO2 pin headerGPIO (8)

UIC+12V, +5V, +3.3V, +5VSUS, +1.5VVoltage Sense

DP1

DP2

USB3_0/1 PortUSB 3.0 (2)

Audio connector

GPIO/SDIO (8)

DIO1 pin header

Hardware MonitorF75308AR

USB2_Port 2 & 3

USB2_Port 3

USB2_Port 0 & 1

Rear I/O:

Rear I/O:

Rear I/O:

Rear I/O:

Rear I/O:

SDIO

SDIO connector

DP RepeaterSN75DP120

SPI

PE1

PE2

DP RepeaterSN75DP120

DDI1DP connector 1Rear I/O:

PCI-e x1PCI-e x1 SlotPE3

Serial 1 & 2General Purpose Serial Ports (2)

TX1/2, RX1/2

SATA1 connector

SATA2 connector

SATA (2)

USB2 connectorRear I/O:

LVDS Trans.VT1636/CH7305

VIA Confidential

USB2_4/5 connector USB2_Port 4 & 5

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


COMEDB4

Cover Sheet


AC

Title


Date: Sheet of


COMEDB4

Cover Sheet


AC

Title


Date: Sheet of


COMEDB4

Cover Sheet


AC

VIA TECHNOLOGIES ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS.

COPYRIGHT 2005 VIA TECHNOLOGIES INCORPORATED.THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE.

Revision A

COMEDB4

TITLE

LVDS

7

16

8

2

9

18

PCIE / PCI Clock Buffer

15

SHEET

DP1 ReDriver_SN75DP120

DP2 ReDriver SN75DP120

LPC SIO F71869ED

26

Block Diagram

HD Codec VT2021 / F_Audio

SATA, VGA, RESET

17

1

COM1, COM2

10

14

3

11

20

27

Cover Sheet

12

214

Printer Port, BIOS, LPC

5

USB 2.0_6 Ports

19

22

6

TITLE SHEET

13

24

CPU & System FAN/EEPROM

Mini PCI-e

ATX_PWR, VCCRTC

FPNL, DIO, AT/ATX SEL

VIA Confidential

COM Express Connector (A-B)

COM Express Connector (C-D)

USB 3.0_2 Ports

LPC Debug Port, SDIO, LED

PCI-e x1

23

RJ45 & LAN LED

Audio Connectors

MOUNTING HOLES

System Power

System Block Diagram

25

DC-IN 12V & AT_ATX

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SER0_TX_SER0_RX_

SER1_TX_SER1_RX_

FAN_PWMOUT_FAN_TACHIN_

RSVD_A86RSVD_A87

RSVD_B98RSVD_B99

SER0_RX_

SER1_RX_ FAN_TACHIN_

SER0_TX_

SER1_TX_

FAN_PWMOUT_

CEM_5VSB

MDI0+[18]MDI0-[18]

MDI1+[18]MDI1-[18]

LAN_-SP100[18]

-SUSB[24]SATA0_TX+[13]SATA0_TX-[13]

SATA0_RX+[13]SATA0_RX-[13]

-SUSC[15]

-SATA_LED[15]AZ_SYNC[6]-AZ_RST[6]

AZ_BITCLK[6]AZ_SDOUT[6]

COM_GPI0[15,21]

LPC_SERIRQ[8,10]

-PE_RST0[22]

USB_DT0+[16]USB_DT0-[16]-USB_OC2_3[16]

USB_DT2-[16]USB_DT2+[16]


COM_GPO2 [15,21]

COM_GPO1 [15,21]

-SYS_RESET [15]

-PE_RST1 [22]

USB_DT1- [16]USB_DT1+ [16]

-USB_OC0_1 [16]USB_DT3+ [16,23]USB_DT3- [16,23]

USB_DT5+ [16]USB_DT5- [16]-USB_OC4_5 [16]

SPKR [6,21]

AZ_SDIN0 [6]

SATA1_RX- [13]SATA1_RX+ [13]

SATA1_TX- [13]SATA1_TX+ [13]

-LPC_FRAME [8,10,21]LPC_AD0 [8,10,21]LPC_AD1 [8,10,21]LPC_AD2 [8,10,21]LPC_AD3 [8,10,21]-LPC_DRQ0 [8]-LPC_DRQ1 [10]

-PW_BTN [15]SMB_CLK [12,15,22,23]SMB_DAT [12,15,22,23]

COM_GPI1[15,21]

COM_GPI2[15,21]PCIE_TX0+[22]PCIE_TX0-[22]

LVDS_A0+[14]LVDS_A0-[14]LVDS_A1+[14]LVDS_A1-[14]LVDS_A2+[14]LVDS_A2-[14]LVDS_VDD_EN[14]LVDS_A3+[14]LVDS_A3-[14]

LVDS_A_CK+[14]LVDS_A_CK-[14]LVDS_I2C_CK[14]LVDS_I2C_DAT[14]COM_GPI3[15,21]

PCIE_CLK_REF-[12]PCIE_CLK_REF+[12]

COM_GPO0[15,21]

PCIE_RX0- [22]

VGA_HSYNC [13]

CRT_SPD [13]

LVDS_B3+ [14]

LVDS_B_CK- [14]

VGA_R [13]

LVDS_B2- [14]

LVDS_B0+ [14]

LVDS_B1+ [14]

VGA_G [13]

COM_GPO3 [15,21]

PCIE_RX0+ [22]

CRT_SPCLK [13]

LVDS_B_CK+ [14]

LVDS_BKLT_EN [14]

LVDS_B0- [14]

LVDS_B2+ [14]

VGA_B [13]

VGA_VSYNC [13]

LVDS_B3- [14]

LVDS_B1- [14]

PWR_OK [24]

LPC_33_CLK [12]

I2C_DAT [11,15]I2C_CLK [11,15]

MDI3-[18]MDI3+[18]

LAN_-SP1000[18]MDI2-[18]MDI2+[18]

LAN_-ACT [18]

-CB_RESET [13]

-PE_WAKE [22,23]-WAKE1 [8]

BLT_CK [14]

-WDT_OUT [15]

VDDTXRX_LAN[18]

SPI_VCC[10]SPI_DI[10]

SPI_CLK[10]SPI_DO[10]

-SPI_SS0 [10]

-BIOS_DIS1 [10]

SD_PWOFF[21]

-SUSA[15]

SER0_RX[9]

SER1_RX[9] FAN_TACHIN[11]

SER0_TX[9]

SER1_TX[9]

FAN_PWMOUT[11]

PCIE_TX1+[22]PCIE_TX1-[22]


PCIE_RX1+ [22]PCIE_RX1- [22]




SD_PWSELS[21]

-USB2_OC6_7[17]

USB2_DT6-[17]USB2_DT6+[17]

USB2_DT7- [17]USB2_DT7+ [17]

+3.3VBAT

+12V +12V

+3.3V

+3.3V

+3.3V

+5VSUS

Title


Date: Sheet of


COMEDB4

COME_CONN(A-B)


AC

Title


Date: Sheet of


COMEDB4

COME_CONN(A-B)


AC

Title


Date: Sheet of


COMEDB4

COME_CONN(A-B)


AC

VIA Confidential

ROW A ROW BROW A ROW B

A4

A9A10

A12A13

A15A16A17

A19A20

A24

A28A29A30

A32A33

A39A40

A42A43A44A45A46

A48

A50

A54

B3B4B5B6B7B8B9B10

B12B13B14

B16B17

B19B20

B24

B27

B30

B32B33B34

B38B39B40

B42B43B44B45B46B47

B49

B54

B57

A63

A67A68A69

A71A72A73A74A75A76A77A78A79

A81A82A83A84A85

A88A89

A93

B63

B66

B68B69

B71B72B73B74B75B76B77B78B79

B81B82

B89

B91B92B93B94B95B96

B2A2A3

A5A6A7

B50

B67

B83

A14

A91A92

A94A95

B97

B88

B102B101

A102A101

A99A98

A18

Pin Protection Reclaim from VCC_12V Circuit

A61A62

A64A65

B64B65

B61B62

B58B59

A58A59

A36A37A38

B36B37

1-2: ATX mode (Default)

2-3: AT mode

JP_AT/ATX_SLE4

Q372N7002/XQ372N7002/XG

DS

R5490R5490

R5554.7K/XR5554.7K/X

Q422N7002/XQ422N7002/X G

DS

JP_AT/ATX_SEL4(1-2)

MINI-JUMPER

JP_AT/ATX_SEL4(1-2)

MINI-JUMPER

CON1AQT002206-4131-3HCON1AQT002206-4131-3H

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313 14 14

1515 16 16

1717 18 18

1919 20 20

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535 36 36

3737 38 38

3939 40 40

4141 42 42

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757 58 58

5959 60 60

6161 62 62

6363 64 64

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979 80 80

8181 82 82

8383 84 84

8585 86 86

8787 88 88

8989 90 90

9191 92 92

9393 94 94

9595 96 96

9797 98 98

9999 100 100

101101 102 102

103103 104 104

105105 106 106

107107 108 108

109109 110 110

111111 112 112

113113 114 114

115115 116 116

117117 118 118

119119 120 120

M1

G1

R5474.7K/XR5474.7K/X

R5534.7K/XR5534.7K/X

R559 1K/XR559 1K/X R552 1K/XR552 1K/X

CON1BQT002206-4131-3HCON1BQT002206-4131-3H

121121 122 122

123123 124 124

125125 126 126

127127 128 128

129129 130 130

131131 132 132

133133 134 134

135135 136 136

137137 138 138

139139 140 140

141141 142 142

143143 144 144

145145 146 146

147147 148 148

149149 150 150

151151 152 152

153153 154 154

155155 156 156

157157 158 158

159159 160 160

161161 162 162

163163 164 164

165165 166 166

167167 168 168

169169 170 170

171171 172 172

173173 174 174

175175 176 176

177177 178 178

179179 180 180

181181 182 182

183183 184 184

185185 186 186

187187 188 188

189189 190 190

191191 192 192

193193 194 194

195195 196 196

197197 198 198

199199 200 200

201201 202 202

203203 204 204

205205 206 206

207207 208 208

209209 210 210

211211 212 212

213213 214 214

215215 216 216

217217 218 218

219219 220 220

G2

M2

R558 1K/XR558 1K/X

R306 0R306 0

Q402N7002/XQ402N7002/X G

DS

Q412N7002/XQ412N7002/X G

DS

R5500R5500

R557 0R557 0

Q392N7002/XQ392N7002/XG

DS

R5614.7K/XR5614.7K/X

R5600R5600

R5484.7K/XR5484.7K/X

JP_AT/ATX_SEL4JP_AT/ATX_SEL42

1

3

R556 0R556 0

R551 0R551 0

R5544.7K/XR5544.7K/X

Q382N7002/XQ382N7002/XG

DS

R304 0R304 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDC_AUX_SEL2

RSVD_C17RSVD_C18

RSVD_D17RSVD_D18

RSVD_C27RSVD_C28

RSVD_D25RSVD_D24

RSVD_D28

RSVD_C35 RSVD_D35

RSVD_D38

RSVD_C45

RSVD_C48

RSVD_D45

RSVD_D48

RSVD_C63RSVD_C64

RSVD_C83

RSVD_C97 RSVD_D97

RSVD_D83

RSVD_D63RSVD_D64

-PEG_LANE_RV

DDC_AUX_SEL1

DDC_AUX_SEL1

DDC_AUX_SEL2

-TYPE2 [24]

-TYPE0[24]

-TYPE1[24]

DP2_AUX+[20]DP2_AUX-[20]

USB3_SSTX0- [17]USB3_SSTX0+ [17]


USB3_SSRX1-[17]USB3_SSRX1+[17]


DP2_LANE0+ [20]DP2_LANE0- [20]

DP2_LANE1+ [20]DP2_LANE1- [20]-DP2_HPD [20]



-DP1_HPD[19]

DP1_AUX+ [19]DP1_AUX- [19]





+12V +12V

Title


Date: Sheet of


COMEDB4

COME_CONN(C-D)


AC

Title


Date: Sheet of


COMEDB4

COME_CONN(C-D)


AC

Title


Date: Sheet of


COMEDB4

COME_CONN(C-D)


AC

ROW C ROW DROW C ROW D

C3C4

C6C7

D3D4

D6D7

D39D40

D42D43D44

D46D47

D50

D57

C54

C57

VIA Confidential

C32C33

D49

C34

DDI Configuration:

DDI 1: DISPLAY PORTDDI 2: DISPLAY PORT

C24

D15D16

D26D27

D29D30

D32D33

D34

D36D37

R616 4.7KR616 4.7K

CON2BQT002206-4131-3HCON2BQT002206-4131-3H

121121 122 122

123123 124 124

125125 126 126

127127 128 128

129129 130 130

131131 132 132

133133 134 134

135135 136 136

137137 138 138

139139 140 140

141141 142 142

143143 144 144

145145 146 146

147147 148 148

149149 150 150

151151 152 152

153153 154 154

155155 156 156

157157 158 158

159159 160 160

161161 162 162

163163 164 164

165165 166 166

167167 168 168

169169 170 170

171171 172 172

173173 174 174

175175 176 176

177177 178 178

179179 180 180

181181 182 182

183183 184 184

185185 186 186

187187 188 188

189189 190 190

191191 192 192

193193 194 194

195195 196 196

197197 198 198

199199 200 200

201201 202 202

203203 204 204

205205 206 206

207207 208 208

209209 210 210

211211 212 212

213213 214 214

215215 216 216

217217 218 218

219219 220 220

G2

M2

R617 4.7KR617 4.7K

CON2AQT002206-4131-3HCON2AQT002206-4131-3H

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313 14 14

1515 16 16

1717 18 18

1919 20 20

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535 36 36

3737 38 38

3939 40 40

4141 42 42

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757 58 58

5959 60 60

6161 62 62

6363 64 64

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979 80 80

8181 82 82

8383 84 84

8585 86 86

8787 88 88

8989 90 90

9191 92 92

9393 94 94

9595 96 96

9797 98 98

9999 100 100

101101 102 102

103103 104 104

105105 106 106

107107 108 108

109109 110 110

111111 112 112

113113 114 114

115115 116 116

117117 118 118

119119 120 120

M1

G1

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

LINE-R

CD_R

SD_IN0

MIC2_FR_L

AFILT4

MIC2_FR_R

MIC1_LMIC1_R

LINE-L

JD2

CD_L

MIC2_FRR

BIT_CLK

FNT_IO_SENSE

PC_BEEP

MIC2_FRL


MIC2_VREFO

JDREFVCAP

U19_35U19_36

MIC2_JD

LINE2_JD

LINE2_RLINE2_L

HP_OUT_R

FNT_DET

HP_OUT_L

JD1

PC_BEEP

MIC2_FR_LMIC2_FR_R

FNT_IO_SENSE

MIC2_VREFO

LINE2_VREFO

HP_OUT_L

HP_OUT_R

AUDIO_VREF

AUDIO_VREF

JDREF

VREFOUT-C_L

VCAP

MIC2_JD

LINE2_JD

LINE2_VREFO

U19_43U19_44

U19_41U19_39

U19_45U19_46

LINE1_IN_R[7]

AZ_SDOUT[4]

LINE1_IN_L[7]

AZ_SDIN0[4]

AZ_BITCLK[4]-AZ_RST[4]

AZ_SYNC[4]

MIC1_VREFO_L [7]

MIC1_RE_L[7]MIC1_RE_R[7]

FRONT_JD[7]LINE1_JD[7]MIC1_JD[7]

FRONT_OUT_L [7]FRONT_OUT_R [7]

SPKR[4,21]

CD_IN_GND[7]CD_IN_L[7]

CD_IN_R[7]

MIC1_VREFO_R [7]

SPDIFO [7]

SURR_JD[7]

CEN_JD[7]SIDESURR_JD[7]

LFE_OUT [7]CEN_OUT [7]

SURR_OUT_L [7]SURR_OUT_R [7]

SIDESURR_OUT_R [7]SIDESURR_OUT_L [7]

+3.3VDUAL

+3.3V

VDD3_AUDIO

AGND

+5VSUS

AGND AGNDAGND

+12V_VCC+5VAUDIO

AGND

AVDD5 +5VAUDIO

VDD3_AUDIO

AGND

AGND

+12V_VCC

AGND

+5VAUDIO

AGND

+12V_VCC

AGND

AGND

AGND

AGNDAGND

AGND

AGND

+5VDUAL

AGND

Title


Date: Sheet of


COMEDB4

HD Audio VT2021


AC

Title


Date: Sheet of


COMEDB4

HD Audio VT2021


AC

Title


Date: Sheet of


COMEDB4

HD Audio VT2021


AC

FRONT AUDIO

HD Audio Codec

+5VAUDIO

Close to VT2021

VIA Confidential

Note: connect standby power(for pop noise)

R258 for RealTek codec Jack detect.

FB41 0FB41 0

R223 33R223 33

+

CE2910uF

+

CE2910uF

12

C220100pFC220100pF

+

CE2110uF

+

CE2110uF

12

R197 3.3KR197 3.3K

R257 5.1K_1%R257 5.1K_1%

+CE37 10uF+CE37 10uF1 2

+CE23 10uF+CE23 10uF1 2

C216 1uFC216 1uF

+

CE3610uF

+

CE3610uF

12

TP_+5VAUDIOTP_+5VAUDIO

1

R209 33R209 33

R193 3.3KR193 3.3K

C239 10uF/XC239 10uF/X

R216 33R216 33

+CE17 10uF+CE17 10uF12

C233 10pFC233 10pF

FB24QT1608RL300LF

FB24QT1608RL300LF

+CE20 220uF+CE20 220uF12

R233 22R233 22

+CE31 10uF+CE31 10uF1 2

R239 22R239 22

+

CE2210uF

+

CE2210uF

12

C227 0.1uFC227 0.1uF

+CE28 10uF+CE28 10uF1 2

R204 5.1K_1%R204 5.1K_1%

R21510KR21510K

C2220.1uFC2220.1uF

C241 100pFC241 100pF

U20

VT2021

U20

VT2021

DVDD11

SENSEA13 SPDIF_TX1 2

DVSS14

SDATA_OUT5

BIT_CLK6

DVSS27

SDATA_IN8

DVDD29

SYNC10

RESET11

PC_BEEP12

SENSEB34

PORT-E/Fr.HP-L14

PORT-E/Fr.HP-R15

PORT-F/Fr.MIC1-L16

PORT-F/Fr.MIC2-R17

CD_L18

CD_GND19

CD_R20

PORT-B/MIC1-L21

PORT-B/MIC2-R22

PORT-C/LINE IN-L23

PORT-C/LINE IN-R24

AVDD1 25

AVSS1 26

NC 37VREFOUT-E 31

CAP 33

GPIO 3

VREFOUT-C 29

VREFOUT-F_L 30

VREFOUT-B_L 28

VREFOUT-B_R 32

FRONT-OUT-L/PORT-D 35

FRONT-OUT-R/PORT-D 36

VREF 27

AVDD2 38

SURR-OUT-L/PORT-A 39

SURR-OUT-R/PORT-A 41

JDREF 40

AVSS2 42

CEN-OUT/PORT-G 43LEE-OUT/PORT-G 44

SIDESURR-OUT-R/PORT-H 46SIDESURR-OUT-L/PORT-H 45

S/PDIF_RX0/EAPD 47

S/PDIF_Tx0 48

D31

BAT54A

D31

BAT54A

1

23

FB42 0FB42 0

R191 16R191 16

U19AMS1117-5.0U19AMS1117-5.0

V_INI

GN

DG

V_OUT O

C2360.1uFC2360.1uF

FB33EBMS160808A520 0.8A

FB33EBMS160808A520 0.8A

R190 16R190 16


R249 33R249 33

+CE13 10uF+CE13 10uF12

R198 0 /XR198 0 /X

+CE18 10uF+CE18 10uF12

C218 100pFC218 100pF

R189 16R189 16

R214 10K_1%R214 10K_1%

C217 1uFC217 1uF

R2171KR2171K

R211 20K_1%R211 20K_1%

+CE30 10uF+CE30 10uF1 2

C2240.1uFC2240.1uF

C244 100pFC244 100pF

C2130.1uFC2130.1uF

C234 0.1uFC234 0.1uF

R196 3.3KR196 3.3K


+CE34 10uF+CE34 10uF1 2

R210 33R210 33

FB37QT1608RL300LF

FB37QT1608RL300LF

C219 1uFC219 1uF

+

CE2610uF

+

CE2610uF

12

C229 22pFC229 22pF

C204 0.1uFC204 0.1uF

D32

BAT54A

D32

BAT54A

1

23

FB260FB260

D41

SSM5817PT

D41

SSM5817PT

A K

FB21 0FB21 0

R199 39.2K_1%R199 39.2K_1%

C2150.1uFC2150.1uF

C2090.1uFC2090.1uF

R258 20K_1%/XR258 20K_1%/X

R194 3.3KR194 3.3K

C2080.1uFC2080.1uF

+

CE3210uF

+

CE3210uF

12

+CE27 10uF+CE27 10uF1 2

C214 1uFC214 1uF

R228 33R228 33

+CE16 10uF+CE16 10uF12

+CE14 10uF+CE14 10uF12

+CE19 220uF+CE19 220uF12

+CE15 10uF+CE15 10uF12

R213 5.1K_1%R213 5.1K_1%

R205 10K_1%R205 10K_1%

R220 10KR220 10K

FB23 0FB23 0

R212 39.2K_1%R212 39.2K_1%

R21810KR21810K

D33

SSM5817PT

D33

SSM5817PT

A K

R188 16R188 16

R238 33R238 33

+CE25 10uF+CE25 10uF1 2

+CE35 10uF+CE35 10uF1 2

F_AUDIO2213S-14G-E08-F2


13 4

2

5 67

14

9 1011 1213

R244 33R244 33

C2420.1uFC2420.1uF

C203 0.1uFC203 0.1uF



R21910KR21910K

R195 20K_1%R195 20K_1%

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

MIC1_RE_L [6]

MIC1_RE_R [6]

MIC1_VREFO_R [6]

FRONT_OUT_L [6]

FRONT_OUT_R [6]

MIC1_JD [6]

FRONT_JD [6]

LINE1_JD [6]

LINE1_IN_L [6]

LINE1_IN_R [6]

CD_IN_R [6]

CD_IN_L [6]CD_IN_GND [6]

MIC1_VREFO_L [6]

SPDIFO [6]

LFE_OUT [6]

CEN_OUT [6]

SURR_OUT_R [6]

SURR_OUT_L [6]

SIDESURR_OUT_R [6]

SIDESURR_OUT_L [6]

SIDESURR_JD [6]

SURR_JD [6]

CEN_JD [6]

AGND

AGND

AGND

AGND

+5V

AGND

AGND

AGND

Title


Date: Sheet of


COMEDB4

Audio Connector


AC

Title


Date: Sheet of


COMEDB4

Audio Connector


AC

Title


Date: Sheet of


COMEDB4

Audio Connector


AC

MIC_IN

LINE1_IN

FRONT_OUT

CD_IN

GREEN

PINK

BLUE

VIA Confidential

For VT17084.7K => Mounted

GREY

BLACK

ORANGE

SIDESURR_OUT

SURR_OUT

CENTER/LFE

R192 3.3KR192 3.3K

FB29 QT1608RL300LFFB29 QT1608RL300LF



R680 1KR680 1K


C202100pFC202100pF

C205100pFC205100pF

AUDIO_JACK1C

ZJ388S-13B-PH

AUDIO_JACK1C

ZJ388S-13B-PH

343Q3P31

C235100pFC235100pF

R679 1KR679 1K

AUDIO_JACK2A

ZJ388S-13B-SH

AUDIO_JACK2A

ZJ388S-13B-SH

141Q1P115

G1

G2

R678 1KR678 1K

C232100pFC232100pF

R200 330R200 330

CD_IN

209-90-04GB20

CD_IN

209-90-04GB20

1234

R208100KR208100K

R207100KR207100K

R206100KR206100K


C243 0.1uFC243 0.1uF

R203 3.3KR203 3.3K



AUDIO_JACK1A

ZJ388S-13B-PH

AUDIO_JACK1A

ZJ388S-13B-PH

141Q1P115

G1

G2

AUDIO_JACK2C

ZJ388S-13B-SH

AUDIO_JACK2C

ZJ388S-13B-SH

343Q3P31

C221100pFC221100pF

C240100pFC240100pF

AUDIO_JACK1B

ZJ388S-13B-PH

AUDIO_JACK1B

ZJ388S-13B-PH

242Q2P21

G3

G4

C226100pFC226100pF




R201 330R201 330

SPDIF

209-90-03GB20

SPDIF

209-90-03GB20

123

C211100pFC211100pF

R2534.7KR2534.7K

C212100pFC212100pF

AUDIO_JACK2B

ZJ388S-13B-SH

AUDIO_JACK2B

ZJ388S-13B-SH

242Q2P21

G3

G4



C207100pFC207100pF

C228100pFC228100pFC210

100pFC210100pF

R202 330R202 330

R681 1KR681 1K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

S_P

SO

NS

_PW

OK

-S_S

3

TM

PIN

2

SIO

VB

AT

SIO_48M_CLK

HW

MG

ND

-CO

PE

N

+3.

3V_I

N

S_GA20

S_P

WR

_OK

VCORE_IN

+12

V_I

N

-S_R

SM

RS

T

-S_P

ME

S_KRST

S_M

DA

TA

S_K

BC

LKS

_KD

AT

A

S_M

SC

LK

-S_S

5

+5V_IN

+3.3V_IN

+12V_IN

+5VSUS_IN

HWMGND

+5V_IN

+1.

5V_I

N

+1.5V_IN

TMPIN2

HWMGND

S_PWOK

-S_S3-S_S5

S_KRSTS_GA20

S_PSON

S_KBCLK

S_MSCLKS_MDATA

S_KDATA

-COPEN

SIO_TXD1

48_CLK SIO_48M_CLK

+5V

SU

S_I

N

SERIRQ

-W_DISABLE

-S_PMES_PWR_OK-S_RSMRST

SIO_GPI50

SIO_GPO36

SIO_GPI52SIO_GPI51

SIO_GPI53

SIO_GPO37

SIO_GPO34SIO_GPO35

LP_SLCT[10]LP_PE[10]

LP_BUSY[10]-LP_ACK[10]-LP_SLIN[10]-LP_INIT[10]-LP_ERR[10]-LP_AFD[10]

-LP_STB[10]LP_D0[10]LP_D1[10]LP_D2[10]LP_D3[10]

LP_D4[10]LP_D5[10]

LP_D7[10]LP_D6[10]

SIO_-DCD1[9]SIO_-RI1[9]SIO_-CTS1[9]SIO_-DTR1[9]SIO_-RTS1[9]SIO_-DSR1[9]

SIO_-DCD2[9]SIO_-RI2[9]SIO_-CTS2[9]

LPC_AD3 [4,10,21]LPC_AD2 [4,10,21]LPC_AD1 [4,10,21]LPC_AD0 [4,10,21]

SIO_33_CLK [12]

SIO_RXD1[9]SIO_TXD1[9]

SIO_-DTR2[9]SIO_-RTS2[9]SIO_-DSR2[9]SIO_TXD2[9]SIO_RXD2[9]

SIO_GPO34[15]SIO_GPO35[15]SIO_GPO36[15]SIO_GPO37[15]SIO_GPI50[15]SIO_GPI51[15]SIO_GPI52[15]SIO_GPI53[15]

-LPC_FRAME [4,10,21]LPC_SERIRQ [4,10]-LPC_DRQ0 [4]-SIO_RESET [13]

FANPWM2 [11]FANIO2 [11]

-W_DISABLE [23]

-WAKE1 [4]

+3.3VBAT

+3.3VSUS

+3.3V

+3.3V

+3.3V +12V_VCC+5VSUS +5V

+5VSUS

+1.5V

+3.3V

+3.3VSUS

SIOVBAT

+3.3VSUS

+3.3V

Title


Date: Sheet of


COMEDB4

LPC SIO F71869ED


AC

Title


Date: Sheet of


COMEDB4

LPC SIO F71869ED


AC

Title


Date: Sheet of


COMEDB4

LPC SIO F71869ED


AC

F71869ED

VIA Confidential

Q13 places on top sideC400,C403 close to SIO

SOUT1 pull low for 2E

Configuration Register set as 4E

R9310K_1%R9310K_1%R388 0R388 0

R389 0R389 0

C960.1uFC960.1uF

R37110K_1%R37110K_1%

RN34 4.7KRN34 4.7K1 23 45 67 8

R405 10R405 10

R401 10KR401 10K

R395 10K/XR395 10K/X

R7820K_1%R7820K_1%

R732 10KR732 10K

R984.7K_1%R984.7K_1%

R396 10K/XR396 10K/X

R735 10KR735 10K

C552100pFC552100pF

RN36 4.7KRN36 4.7K

1 23 45 67 8

C550100pFC550100pF R86

10K_1%R8610K_1%

RN35 4.7KRN35 4.7K1 23 45 67 8

R731 10KR731 10K

R8010K_1%R8010K_1%

SYS_SENSYS_SEN21

3

C551100pFC551100pF

C55 22pF/XC55 22pF/X

C330100pFC330100pF

D44BAT54CD44BAT54C

1

23

C548 0.1uFC548 0.1uF

C5210uFC5210uF

R727 2MR727 2M

R729 10K/XR729 10K/X

F71869ED

U7

F71869ED

F71869ED

U7

F71869ED

DT

R2#

/GP

IO23

1

RT

S2#

/GP

IO24

2

DS

R2#

/GP

IO25

3

VC

C4

SO

UT

2#/G

PIO

265

SIN

2#/G

PIO

276

DE

NS

EL#

/GP

IO30

7

MO

A#/

GP

IO31

8

DR

VA

#/G

PIO

329

WD

AT

A#/

GP

IO33

10

DIR

#/G

PIO

3411

ST

EP

#/G

PIO

3512

HD

SE

L#/G

PIO

3613

WG

AT

E#/

GP

IO37

14

RD

AT

A#/

GP

IO50

15

TR

K0#

/GP

IO51

16

IND

EX

#/G

PIO

5217

WP

T#/

GP

IO53

18

DS

KC

HG

#/G

PIO

5419

GN

D20

FA

NIN

121

FA

NC

TL1

22

FA

NIN

223

FA

NC

TL2

24

FA

NIN

3/G

PIO

4025

FA

NC

TL3

/GP

IO41

26

IRT

X/G

PIO

4227

IRR

X/G

PIO

4328

LRE

SE

T#

29

LDR

Q#

30

SE

RIR

Q31

LFR

AM

E#

32

GPIO15 64

GPIO14 63

GPIO13 62

GPIO12 61

GPIO11 60

GPIO10 59

PECI/TSI_DAT 58

PECI_REQ#/TSI_CLK 57

ST1/GPIO05 56

ST2/SLOTOCC#/GPIO04 55

TIMING_1/GPIO03 54

TIMING_2/GPIO02 53

TIMING/GPIO 52

GPIO65 51

GPIO64 50

GPIO63 49

GND 48

TIMING_4/GPIO01 47

TIMING_3/GPIO00 46

5VSB 45

CTRL1# 44

CTRL0# 43

EVENT_IN# 42

GA20 41

KBRST# 40

CLKIN 39

BUSY102PE101SLCT100VSB99VIN1(Vcore)98VIN2(VLDT)97

VIN

3(V

DD

A)

96

VIN

4(V

DIM

M)

95

VIN

594

VIN

693

VR

EF

92

D1+

(CP

U)

91

D2+

90

D3+

(Sys

tem

)89

AG

ND

(D-)

88

CO

PE

N#

87

VB

AT

86

RS

MR

ST

#85

PW

OK

84

PS

_ON

#/G

PIO

4783

S3#

82

PW

SO

UT

#/G

PIO

4681

PW

SIN

#/G

PIO

4580

PM

E#

79

AT

XP

G_I

N/G

PIO

4478

S5#

77

PC

IRS

T3#

76

PC

IRS

T2#

75

PC

IRS

T1#

74

GN

D73

MC

LK72

MD

AT

A71

KC

LK70

KD

AT

A69

VS

B68

OV

T#

67

CP

U_P

WR

GD

/GP

IO17

66

GP

IO16

/LE

D_V

CC

65

ACK#103

SLIN#104

INIT#105

ERR#106

AFD#107

STB#108

PD0109

PD1110

PD2111

PD3112

PD4113

PD5114

PD6115

PD7116

GND117

DCD1#118

RI1#119

CTS1#120

DTR1#/FAN40_100121

RTS1#122

DSR1#123

SOUT1#/Config4E_2E124

SIN1#125

DCD2#/GPIO20126

RI2#/GPIO21127

CTS2#/GPIO22128 LAD0 33LAD1 34LAD2 35LAD3 36VCC 37

PCICLK 38

R733 10KR733 10K

R792K_1%R792K_1%

R728 10KR728 10KR730 10KR730 10K

C580.1uFC580.1uF

R734 0R734 0

C290100pFC290100pF

C75 0.1uFC75 0.1uF

R404 1KR404 1K

R8715K_1%R8715K_1%

C893300pFC893300pF

OSC1

48MHz

OSC1

48MHz

Tri-State1

GND2 OUT 3

VDD 4

R8110K_1%R8110K_1%

Q11MMBT3904/X

Q11MMBT3904/X

B

EC

R736 10KR736 10K

R9215K_1%R9215K_1%

C560.1uFC560.1uF

C549 0.1uFC549 0.1uF

R38 22R38 22

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

COM_RI1

COM_RTS1

COM_DTR1

COM_DSR1COM_DCD1

COM_CTS1COM_TXD1

COM_RXD1

COM_TXD2

COM_CTS2COM_DSR2

COM_RXD2COM_DCD2COM_DTR2

COM_RI2COM_RTS2

SER0_RX_CON

SER0_TX_CON

SER1_RX_CON

SER1_TX_CON

-XRI2

COM_RI2

-XRI1

COM_RI1

SER1_RX_CON


SER1_TX_CON

COM_DTR1COM_DSR1

COM_DCD1

COM_CTS1

COM_RTS1

COM_RXD1

-XRI1

COM_TXD1

COM_DSR2

COM_RTS2COM_DTR2

COM_CTS2

COM_DCD2COM_RXD2

COM_TXD2

-XRI2

SER1_TX[4]SER0_TX[4]

SER1_RX[4]SER0_RX[4]

SIO_-DCD1[8]

SIO_-DSR1[8]

SIO_RXD1[8]

SIO_-RTS1[8]SIO_TXD1[8]

SIO_-CTS1[8]

SIO_-DTR1[8]

SIO_-RI1[8]

SIO_-DCD2[8]

SIO_-DSR2[8]

SIO_RXD2[8]

SIO_-RTS2[8]SIO_TXD2[8]

SIO_-CTS2[8]

SIO_-DTR2[8]

SIO_-RI2[8]

+5V +5V

+5V +12V_VCC

+5V +12V_VCC

+5V

+5V

+5V

+5V

Title


Date: Sheet of


COMEDB4

COM1, COM2


AC

Title


Date: Sheet of


COMEDB4

COM1, COM2


AC

Title


Date: Sheet of


COMEDB4

COM1, COM2


AC

COM 1

COM 2

VIA Confidential

General Purpose

Serial Ports

JP_COM2_VSEL

1-2

2-3

+5V

+12V

VOLTAGE

JP_COM1_VSEL

1-2

2-3

+5V

+12V

VOLTAGE

Normal *

3-4

Normal *

3-4

C1030.1uFC1030.1uF

U10

TRS3243ECDBR

U10

TRS3243ECDBR

V- 3

VC

C26

FORCEOFF#22

C1+28

V+ 27

C1-24

C2+1

C2-2

FORCEON23

GND 25

DOUT1 9

DOUT2 10

DOUT3 11

RIN1 4

RIN2 5

RIN3 6

RIN4 7

RIN5 8

DIN114

DIN213

DIN312

ROUT119

ROUT218

ROUT317

ROUT416

ROUT515

ROUTB220

INVLID# 21

C4810.1uFC4810.1uF

C1060.1uFC1060.1uF

JP_COM2_VSEL

2211S-04G-BK-F2

JP_COM2_VSEL

2211S-04G-BK-F2

1

34

2

C5470.1uFC5470.1uF

U13

TRS3243ECDBR

U13

TRS3243ECDBR

V- 3

VC

C26

FORCEOFF#22

C1+28

V+ 27

C1-24

C2+1

C2-2

FORCEON23

GND 25

DOUT1 9

DOUT2 10

DOUT3 11

RIN1 4

RIN2 5

RIN3 6

RIN4 7

RIN5 8

DIN114

DIN213

DIN312

ROUT119

ROUT218

ROUT317

ROUT416

ROUT515

ROUTB220

INVLID# 21

F1SMD0805P050TF

F1SMD0805P050TF

1 2

C4820.1uFC4820.1uF

C4830.1uFC4830.1uF

C5350.1uFC5350.1uF

C4840.1uFC4840.1uF

JP_COM2_VSEL(2-3)

MINI-JUMPER

JP_COM2_VSEL(2-3)

MINI-JUMPER

SER_PORT

2213S-10G-E10-F2

SER_PORT

2213S-10G-E10-F2

13 4

2

5 67 89

JP_COM1_VSEL(2-3)

MINI-JUMPER

JP_COM1_VSEL(2-3)

MINI-JUMPER

C5460.1uFC5460.1uF

CN12220pFCN12220pF

12

34

56

78

JP_COM1_VSEL

2211S-04G-BK-F2

JP_COM1_VSEL

2211S-04G-BK-F2

1

34

2

R20 0R20 0C5410uFC5410uF

CN13220pFCN13220pF

12

34

56

78

C5340.1uFC5340.1uF

C1070.1uFC1070.1uF

C6510uFC6510uF

C5450.1uFC5450.1uF

U15

MAX232DR

U15

MAX232DR

T1IN11T2IN10R1O12R2O9

T1O 14T2O 7

R1IN 13R2IN 8

VCC16

GND15

C1+1

C1-3

C2+ 4

C2- 5

V+ 2

V- 6

F2SMD0805P050TF

F2SMD0805P050TF

1 2

CN11220pFCN11220pF

12

34

56

78

CN14220pFCN14220pF

12

34

56

78

R41 0R41 0

COM2

2213S-10G-E10-F2

COM2

2213S-10G-E10-F2

13 4

2

5 67 89

C1000.1uFC1000.1uF

C1080.1uFC1080.1uF

C5440.1uFC5440.1uF VGA_COM1A

C023650-01

VGA_COM1A

C023650-01

C1C6C2C7C3C8C4C9C5

G1

G2

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

-LP_STB

-LP_STB

-LP_ACK

LP_PE

LP_D2

LP_BUSY

LP_BUSY

LP_SLCTLP_PE

LP_D4

-LP_ERR

-LP_ACK

LP_D5

LP_D1

-LP_INIT

LPT

_VC

C

LP_SLCT

-LP_AFD

LP_D7

-LP_SLIN

LP_D6

LP_D3

LP_D0

LP_D6

-LP_ACK

LP_D4

LP_D2LP_D1 -LP_INIT

-LP_ERR-LP_STB

LP_D5

LP_BUSY

-LP_AFD

LP_SLCT

-LP_SLIN

LP_D7

LP_PE

LP_D0

LP_D3

-LP_INIT

LP_D4LP_D5

LP_D7LP_D6

LP_D0LP_D1

LP_D3LP_D2

-SPI_HOLD

-LP_SLIN

-LP_ERR-LP_AFD

-SPI_SS0SPI_DI

SPI_VCC

-SPI_HOLD-SPI_WP

SPI_DOSPI_CLK

-LP_STB[8]

LP_BUSY[8]-LP_ACK[8]

LP_SLCT[8]LP_PE[8]

LP_D4[8]LP_D5[8]

LP_D7[8]LP_D6[8]

LP_D0[8]LP_D1[8]

LP_D3[8]LP_D2[8]

-BIOS_DIS1 [4]

-LP_SLIN[8]

RST_SW [15]

SPI_CLK [4]SPI_DO [4]

SPI_VCC[4]

-SPI_SS0[4]SPI_DI[4]

LPC_AD2[4,8,21]

-LPC_RESET[13]

LPC_SERIRQ[4,8]-LPC_FRAME [4,8,21]

-LPC_DRQ1[4]

LPC_AD1[4,8,21]

LPC_AD0[4,8,21]

LPC_HEADER [12]

LPC_AD3 [4,8,21]

-LP_AFD[8]

-LP_INIT[8]-LP_ERR[8]

+5V

+3.3V+3.3V

+3.3V+5V

Title


Date: Sheet of


COMEDB4

Printer Port, BIOS & LPC


AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

Printer Port

BIOS_DISABLE BIOS_DIS1

MODULE SPI BIOS 1 - 2 *

BIOS Selection Table

VIA ConfidentialCARRIER SPI BIOS 2 - 3

BIOS DISABLE

Pitch 2.54mm

SPI ROM

KEY

LPC HEADER

R34 2.7KR34 2.7K

C51 180pFC51 180pF

C33 180pFC33 180pF

BIOS_DIS1(1-2)

MINI-JUMPER

BIOS_DIS1(1-2)

MINI-JUMPER

C37 180pFC37 180pF

BIOS_DIS1

HEADER_1X3

BIOS_DIS1

HEADER_1X3

21

3

C23 180pFC23 180pF

C90.1uFC90.1uF

LPT

2213S-26G-E26-F2

LPT

2213S-26G-E26-F2

13 4

2

5 67 89 10

11 1213 1415 1617 1819 2021 2223 2425

C31 180pFC31 180pF

R604.7KR604.7K

C29 180pFC29 180pF

SPI

2213S-08G-E7-F2

SPI

2213S-08G-E7-F2

13 4

2

5 68

C36 180pFC36 180pF

R22 4.7KR22 4.7K

C27 180pFC27 180pF

C22 180pFC22 180pF

C30 180pFC30 180pF

D5LL4148-GS08D5LL4148-GS08

R264.7KR264.7K

RN62.7KRN62.7K

1 23 45 67 8

C26 180pFC26 180pF

RN82.7KRN82.7K

1 23 45 67 8

C35 180pFC35 180pF

RN92.7KRN92.7K

1 23 45 67 8

C130.1uFC130.1uF

RN72.7KRN72.7K

1 23 45 67 8

C25 180pFC25 180pF

C28 180pFC28 180pF

U5

PCT25VF032B-80-4I-S2AF

U5

PCT25VF032B-80-4I-S2AF

CE#1

SO2

WP#3

VSS4 SI 5SCK 6

HOLD# 7VDD 8

C34 180pFC34 180pF

LPC

2208S-20G-BK-E01-F2

LPC

2208S-20G-BK-E01-F2

13 4

2

5 67 89 10

11 1213 1415 1617 1819

Q92N7002Q92N7002G

DS

C210.1uFC210.1uF

C24 180pFC24 180pF

R614.7KR614.7K

C32 180pFC32 180pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

OP+_INS FAN_PWRFAN_IO2

FAN_PWM2TR_BASE

OP_OUT

FAN_IN1

TR_IN

OP+_IN FAN_P

EEPROM_AX

EEPROM_WP

OP_OUTS

FANPWM2[8]

FAN_PWMOUT[4]

FAN_TACHIN [4]

FANIO2 [8]

I2C_CLK [4,15]I2C_DAT [4,15]

+3.3V

+3.3V

+12V_VCC+12V_VCC

+12V_VCC

+12V_VCC+12V_VCC+3.3V

+3.3V

+3.3V

+12V_VCC

+12V_VCC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

SYSTEM FAN

16V SMD

VIA Confidential

CPU FANEEPROM

+3.3V Write Protect

GND Normal Operation *EEPROM Write Protect

Device Address = 0x57(0xAE)

C9522pFC9522pF

R75 47K_1%R75 47K_1%

R47 0R47 0

Q142SB772PTQ142SB772PT

B

CE

C4910uFC4910uF

CPUFAN

2417SJ-03-01

CPUFAN

2417SJ-03-01

123

C6622pFC6622pF

+

-

U14ALM393DR

+

-

U14ALM393DR

3

21

84

C33822uFC33822uF

C8310uFC8310uF

R50 27KR50 27K

D15 LL4148-GS08D15 LL4148-GS08

R65 57.6K_1%R65 57.6K_1%

C720.1uFC720.1uF

U9

AT24C04C-SSHM-T

U9

AT24C04C-SSHM-T

A01

A12

A23

GND4 SDA 5SCL 6WP 7

VCC 8

R901KR901K

+

-

U14BLM393DR

+

-

U14BLM393DR

5

67

84

C7022pFC7022pF

C8222pFC8222pF

R89 1KR89 1K


B

CE

R57 1KR57 1K

C5010uFC5010uF

R560/XR560/X

R96 15K_1%R96 15K_1%R910/XR910/X

R734.7K/XR734.7K/X

R5110KR5110KR66

22KR6622K

R42 0R42 0

R7415K_1%R7415K_1%

R54610KR54610K

R5210K/XR5210K/X

R881KR881K

R454.7KR454.7K

C8410uFC8410uF

SYSFAN

2217S-03-F3

SYSFAN

2217S-03-F3

12

3

R54510KR54510K

R974.7KR974.7K

D9LL4148-GS08D9LL4148-GS08

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LCLK_AK2001

LPC_HEADER

SIO_33_CLK

LPCCLK2

LPCCLK5

LPCCLK4LPCCLK3

SRC_IN-SRC_IN

SDATASCLK

IREF

OE_0OE_1OE_2

OE_4OE_5OE_6OE_7

-HIGH_BW

OE_INV

-BYPASS

-SRC_DIV-SRC_STOP

+3.3VCLK_BF

-CLK_PD

PECLK0+PECLK0-

PECLK1+PECLK1-

PECLK2+PECLK2-

OE_3

PCIE_CLK0+

PCIE_CLK0-

PCIE_CLK1+

PCIE_CLK1-

PCIE_CLK2+

PCIE_CLK2-

PCIE_CLK4+

PCIE_CLK4-

OE_INV

-HIGH_BW

-BYPASS

-SRC_DIV

-SRC_STOP

-CLK_PD

PECLK4+PECLK4-

LCLK_AK2001 [21]LPC_HEADER [10]

SIO_33_CLK [8]LPC_33_CLK[4]

PCIE_CLK0+ [22]PCIE_CLK0- [22]

PCIE_CLK1- [22]PCIE_CLK1+ [22]


PCIE_CLK_REF+[4]PCIE_CLK_REF-[4]

SMB_CLK[4,15,22,23]SMB_DAT[4,15,22,23]

-PEREQ_1[23]


+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

Title


Date: Sheet of


COMEDB4

PCIE/ PCI Clock Buffer


AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

PCIE CLOCK BUFFER

VIA Confidential

LPC CLOCK BUFFER

TO PE1 SLOT

TO PE2 SLOT

TO PE3 SLOT

meet Zdif=49.9 ohm

TO Mini PCI-e

R226 22R226 22

R572 10K/XR572 10K/X

R567 10K/XR567 10K/X

R573 10KR573 10K

R570 10K/XR570 10K/X

R224 49.9_1%R224 49.9_1%

R574 10KR574 10K

R568 10KR568 10K

R575 10KR575 10K

R571 10KR571 10K


R577 10K/XR577 10K/X

R569 10KR569 10K

R221 0R221 0

R227 49.9_1%R227 49.9_1%

C590.1uFC590.1uF

R242 22R242 22

R261 0R261 0

R235 49.9_1%R235 49.9_1%

R576 10KR576 10K

R30 22R30 22

R256 0R256 0

R254 10KR254 10K

U6

CY23S05SXC-1

U6

CY23S05SXC-1

REF1

CLK2 2CLK1 3

GND4

CLKOUT 8

CLK4 7

VDD6

CLK3 5

TP_CKG_LOCKTP_CKG_LOCK1R237 49.9_1%R237 49.9_1%

R222 0R222 0

R262 0R262 0

FB35 QT2012RL060FB35 QT2012RL060

R578 10KR578 10K

U32

ICS9DB801BGLF

U32

ICS9DB801BGLF

SCLK23

SDATA24

VDD12

VDD211

VDD319

GNDA 47

VDD539

SRC_IN4

DIF_0 8

DIF_0# 9

DIF_1 12

DIF_1# 13

DIF_2 16

DIF_2# 17

DIF_3 20

DIF_3# 21

DIF_4 30

DIF_4# 29

DIF_5 34

DIF_5# 33

SRC_IN#5

GND2 10

GND3 18

GND4 25

GND5 32

VDDA48

GND1 3

VDD431

DIF_6 38

DIF_6# 37

DIF_7 42

DIF_7# 41

OE_06

OE_114

OE_215

OE_37

OE_443

OE_535

OE_636

OE_744

OE_INV40

SRC_DIV#1

BYPASS#/PLL22

SRC_STOP#27

PD#26

HIGH_BW#28

IREF46

LOCK 45

C2450.1uFC2450.1uF

R579 10KR579 10K

C6010uFC6010uF

R251 22R251 22

R230 22R230 22

R250 10K/XR250 10K/X

R255 475_1%R255 475_1%

R44 22R44 22

R580 10KR580 10K

TP_LPC_CLK4TP_LPC_CLK41

C23010uFC23010uF

R229 49.9_1%R229 49.9_1%

+

CE331000uF/10V

+

CE331000uF/10V

12

C2250.1uFC2250.1uF

R232 49.9_1%R232 49.9_1%

R581 10KR581 10K

R236 22R236 22

R241 49.9_1%R241 49.9_1%

FB8 QT2012RL060FB8 QT2012RL060

C2230.1uFC2230.1uF

R582 10KR582 10K

C7122pF/XC7122pF/X

C2380.1uFC2380.1uF

R243 49.9_1%R243 49.9_1%

R43 22R43 22

C2370.1uFC2370.1uF

R247 22R247 22

R259 10K/XR259 10K/X


R231 22R231 22

R225 22R225 22

R246 10KR246 10K


A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CON_R

CON_G

CON_VS

CON_B

CON_HS

V_SYNC

H_SYNC

CRTSPCLK

CRTSPD

VGA_PS

CRT_SPCLK [4]

CRT_SPD [4]VGA_G[4]

VGA_R[4]

VGA_B[4]

VGA_VSYNC[4]

VGA_HSYNC[4]



-CB_RESET[4]

-SIO_RESET [8]

-LPC_RESET [10]

-80_PORT_RESET [21]

SATA1_TX+[4]SATA1_TX-[4]

SATA0_TX-[4]SATA0_TX+[4]

+5VCRT

+3.3V

+5VCRT

+3.3V

+3.3V

+5VCRT

+5VCRT

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+5V

+5VCRT

+5VCRT

+12V_VCC

Title


Date: Sheet of


COMEDB4

SATA & VGA


AC

Title


Date: Sheet of


COMEDB4

SATA & VGA


AC

Title


Date: Sheet of


COMEDB4

SATA & VGA


AC

GNDRGB should be at least 15 mils width.NOTE: R,G,B should be 12 mils width and no longer than 6".

VGA

VIA Confidential

SATA

2A

R72 22R72 22

R39150_1%R39150_1%

R11 10R11 10

R351.5KR351.5K

SATA2

WATF-07DBN6SA1UW

SATA2

WATF-07DBN6SA1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

C155 0.01uF X7RC155 0.01uF X7R

U3

74AHCT1G08GV

U3

74AHCT1G08GV

12

43

5

U12A

SN74LV04ADR

U12A

SN74LV04ADR

1 2

147


G

DS

R25150_1%R25150_1%

R17 10R17 10

D6BAT54SD6BAT54S

2

3

1

R191.5KR191.5K

C425pFC425pF

D2BAT54SD2BAT54S

2

3

1

R55 22R55 22

C745pFC745pF

U12F

SN74LV04ADR

U12F

SN74LV04ADR

13 12

147

L6 BLM15BB220SN1DL6 BLM15BB220SN1D

D4

BAT54S

D4

BAT54S

2

3

1

R211.5KR211.5K

D1BAT54SD1BAT54S

2

3

1

SATA1

WATF-07DBN6SA1UW

SATA1

WATF-07DBN6SA1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

U12E

SN74LV04ADR

U12E

SN74LV04ADR

11 10

147

PS1SMD1206P150TFTPS1SMD1206P150TFT

12

VGA_COM1B

C023650-01

VGA_COM1B

C023650-01

V6

G3

V1V7V2V8V3V9V4

V10

G4

V5

V11

V12

V13

V14

V15

U12D

SN74LV04ADR

U12D

SN74LV04ADR

9 8

147

C153 0.01uF X7RC153 0.01uF X7R

U12C

SN74LV04ADR

U12C

SN74LV04ADR

5 6

147

C10.1uFC10.1uF

Q62N7002Q62N7002 G

D S

R77 22R77 22

D7

BAT54S

D7

BAT54S

2

3

1

U12B

SN74LV04ADR

U12B

SN74LV04ADR

3 4

147

C613pFC613pF

U2

74AHCT1G08GV

U2

74AHCT1G08GV

12

43

5

FB1

QT2012RL600HC2ALF

FB1

QT2012RL600HC2ALF


C150 0.01uF X7RC150 0.01uF X7R

C413pFC413pF

D3BAT54SD3BAT54S

2

3

1

D8

BAT54S

D8

BAT54S

2

3

1

Q52N7002Q52N7002

G

D S

C1010pFC1010pF

C800.1uFC800.1uF

C625pFC625pF

C151 0.01uF X7RC151 0.01uF X7R

R46150_1%R46150_1%

R141.5KR141.5K

C733pFC733pF

C1710pFC1710pF


A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

-A7_L

A0_L

A7_L

A3_L

CLK1_L

-A6_L

-A5_L

-CLK1_L

SPCLK_R

-CLK1_L

-A2_L

-A4_L

-A1_L

A5_L

SPD_RA6_L

-CLK2_L

-A7_L

-A4_L A6_L

CLK2_L

A2_L

CLK1_L

A7_L

A4_L

A2_L

-A5_L

-A3_L

-A6_L

-A0_L

CLK2_L-CLK2_L

-A1_L

A4_L

-A3_L

-A0_L

A3_L

A1_L

-A2_L

A0_L

A5_LA1_L

BAKLITE

IVDD_GND

LVDS_I2C_DAT

-BKLT_EN

IVDD_IN

LVDS_I2C_CK

BLT_CTRL

PVDD_SEL

VDD_EN

PVDD_ON

-VDD_EN

PVDD

IVDD_SEL

BKLT_EN

PVDD_TR

PVDD

LVDS_I2C_CK

LVDS_I2C_DAT

SPCLK_R

SPD_R

DDC_PWR

LVDS_A0+[4]

LVDS_A0-[4]

LVDS_A1+[4]

LVDS_A1-[4]

LVDS_A2+[4]

LVDS_A2-[4]

LVDS_A3+[4]

LVDS_A3-[4]

LVDS_A_CK+[4]

LVDS_A_CK-[4]

LVDS_B0+[4]

LVDS_B2+[4]

LVDS_B1-[4]

LVDS_B_CK+[4]

LVDS_B_CK-[4]

LVDS_B1+[4]

LVDS_B3+[4]

LVDS_B3-[4]

LVDS_B2-[4]

LVDS_B0-[4]

LVDS_BKLT_EN[4]

LVDS_VDD_EN[4]

BLT_CK[4]

LVDS_I2C_CK[4]LVDS_I2C_DAT[4]

+5V

+5V

+12V_VCC

+5V +3.3V

+5V

+5V

+5V

PVDD

PVDD

+3.3V

+5V

Title


Date: Sheet of


COMEDB4

LVDS


AC

Title


Date: Sheet of


COMEDB4

LVDS


AC

Title


Date: Sheet of


COMEDB4

LVDS


AC

+12V *

IVDD_SEL

+5V Pin 1,2 : Close

Pin 2,3 : Close



+5V

Pin 2,3 : Close

PVDD

Pin 1,2 : Close

+3.3V *

LVDS CONNECTOR

PANEL POWERBACKLIGHT CONTROL

VIA Confidential

L35 ACM2012-900-2P-T002L35 ACM2012-900-2P-T0021 4

32

IVDD(2-3)

MINI-JUMPER

IVDD(2-3)

MINI-JUMPER

Q82N7002/XQ82N7002/X

G

D S

INVERTER

85205-0800N

INVERTER

85205-0800N

11

22

33

44

55

66

8877

G1G1

G2G2

R186 0R186 0L33 ACM2012-900-2P-T002L33 ACM2012-900-2P-T002

1 4

32

L27 ACM2012-900-2P-T002L27 ACM2012-900-2P-T002

1 4

32

EDID_PWR

HEADER_1X3

EDID_PWR

HEADER_1X3

21

3R185 0R185 0

Q22SI2301CDS-T1-GE3Q22SI2301CDS-T1-GE3

G

DS

C19 0.1uFC19 0.1uF

Q26MMBT3904Q26MMBT3904

B

EC

R6470_1%R6470_1%

IVDDHEADER_1X3

IVDDHEADER_1X3

2 13

LVDS

87209-4040-06

LVDS

87209-4040-06

22 1 1

44 3 3

66 5 5

88 7 7

1010 9 9

1212 11 11

1414 13 13

1616 15 15

1818 17 17

2020 19 19

2222 21 21

2424 23 23

2626 25 25

2828 27 27

3030 29 29

3232 31 31

3434 33 33

3636 35 35

3838 37 37

4040 39 39

G1

G1

G2

G2

M1

M1

M2

M2

R4 0/XR4 0/X

Q42N7002Q42N7002G

DS

L31 ACM2012-900-2P-T002L31 ACM2012-900-2P-T0021 4

32

C50.1uFC50.1uF

R164.7KR164.7K

C2 0.1uFC2 0.1uF

R5 0R5 0

L26 ACM2012-900-2P-T002L26 ACM2012-900-2P-T0021 4

32

C1630.1uFC1630.1uF

+

CE147uF

+

CE147uF

12

L40 ACM2012-900-2P-T002L40 ACM2012-900-2P-T002

1 4

32

EDID_PWR(1-2)

MINI-JUMPER

EDID_PWR(1-2)

MINI-JUMPER

R274.7K/XR274.7K/X

L28 ACM2012-900-2P-T002L28 ACM2012-900-2P-T0021 4

32

C1970.1uFC1970.1uF


FB2BLM21PG300SN1D

FB2BLM21PG300SN1D

C184 0.1uFC184 0.1uF

L25 ACM2012-900-2P-T002L25 ACM2012-900-2P-T0021 4

32

FB19BLM21PG300SN1D

FB19BLM21PG300SN1D

L29 ACM2012-900-2P-T002L29 ACM2012-900-2P-T002

1 4

32

C160.1uFC160.1uF

R1814.7KR1814.7K

PVDD(2-3)

MINI-JUMPER

PVDD(2-3)

MINI-JUMPER

R17933R17933

R184 1KR184 1K

Q212N7002/XQ212N7002/X

G

D S

R15 1KR15 1K

U1

AD5301BRTZ

U1

AD5301BRTZ

GND1

A0 5

VOUT 4SCL3SDA2

VDD 6

Q242N7002Q242N7002G

DS

PVDDHEADER_1X3

PVDDHEADER_1X32

1 3


B

EC

R244.7K/XR244.7K/X

L37 ACM2012-900-2P-T002L37 ACM2012-900-2P-T002

1 4

32

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

5V_DIO1 12V_DIO1

-PLED_2

-SLEEP_LED

Q11_Q

12

-PLED_2

FP_1_3 FP_2

FP_7

Q21_G

FP_14

-PW_BTN

RST_SW

-PLED_2FP_1_3 -SATA_LEDFP_2

RST_SW

5V_DIO2 12V_DIO2

-SYS_RESET

-PW_BTN-RST1 -RST2

Q22_B

-PW_BTN

-PWRBTN

COM_GPO1[4,21]COM_GPI2 [4,21]

COM_GPO3[4,21] COM_GPI3 [4,21]COM_GPO2[4,21]

COM_GPO0[4,21]COM_GPI1 [4,21]COM_GPI0 [4,21]

-SATA_LED [4]

SPEAK[21]

-PW_BTN [4]

-SUSC[4]

RST_SW [10]

-WDT_OUT[4]

-SYS_RESET [4]

SIO_GPO34[8]SIO_GPO35[8]


SIO_GPI50 [8]SIO_GPI51 [8]SIO_GPI52 [8]SIO_GPI53 [8]

SMB_CLK [4,12,22,23]SMB_DAT [4,12,22,23] I2C_CLK [4,11]

I2C_DAT [4,11]

-SUSA[4]

+12V_VCC+5V

+5V

+5VDUAL +5V

+5V

+3.3VDUAL

+3.3V

+3.3V

+5V +12V_VCC

+3.3V

+5VSUS+5VSUS +5VSUS

+5VDUAL

Title


Date: Sheet of


COMEDB4

FPNL, DIO, SMBUS, I2C


AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

SPEAK

FRONT PANEL

RESET

PW-BN

HD-LED

PW-LED PWRBTN

SMBUS

RESET_BTN

Digital I/O

VIA Confidential

RESET_IC

I2C_BUS

AT/ATX Mode Select


2-3: AT mode

RST_BTN

PT-002-B1

RST_BTN

PT-002-B1

1

2

3

4

R349 330R349 330

U30

MIC6315-44D4UY/X

U30

MIC6315-44D4UY/X

VC

C4

RST 2

GN

D1

MR3

R3404.7KR3404.7K

R341 0/XR341 0/X


B

EC

JP_AT/ATX_SEL1

HEADER_1X3

JP_AT/ATX_SEL1

HEADER_1X3

21

3

F_PANEL

2213S-16G-E15-F2

F_PANEL

2213S-16G-E15-F2

13 4

2

5 67 89 10

11 1213 14

16

R354 68R354 68

PS7SMD1206P050TF/15

PS7SMD1206P050TF/15

1 2

PS12SMD1206P050TF/15


1 2

U31

MIC6315-44D4UY/X

U31

MIC6315-44D4UY/X

VC

C4

RST 2

GN

D1

MR3 R356 0/XR356 0/X

R3554.7K/XR3554.7K/X

R3574.7K /XR3574.7K /X

R3394.7K /XR3394.7K /X

U28

NC7SZ08M5X_NL/X

U28

NC7SZ08M5X_NL/X

12

43

5

PS6SMD1206P050TF/15

PS6SMD1206P050TF/15

1 2

HDD_LED

17-21SURC/S530-A2/TR8

HDD_LED

17-21SURC/S530-A2/TR8

1 2

TP_SLEEP_LEDTP_SLEEP_LED1

PWR_LED

LED LAMP GREEN

PWR_LED

LED LAMP GREEN

1 2

R345 0R345 0

JP_AT/ATX_SEL1(1-2)

MINI-JUMPER

JP_AT/ATX_SEL1(1-2)

MINI-JUMPER

I2C_BUS

HEADER_1X3

I2C_BUS

HEADER_1X3

21

3



1 2

R6081KR6081K

SMBUS

HEADER_1X3

SMBUS

HEADER_1X3

21

3

PWR_BTN

PT-002-B1

PWR_BTN

PT-002-B1

1

2

3

4

R367330R367330

R359330R359330

R366 2.2KR366 2.2K

R511 2.2KR511 2.2K

DIO2

2213S-12G-F2

DIO2

2213S-12G-F2

13 45 67 89 10

11 12

2

R353 68R353 68

C45922uFC45922uF

DIO1

2213S-12G-F2

DIO1

2213S-12G-F2

13 45 67 89 10

11 12

2

Q322N7002Q322N7002

G

DS

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VUSB0

USBD_T0+

-ROC0_1

USBD_T0- USBD_T1-USBD_T1+

USBD_T4-USBD_T4+

-ROC4

VUSB4

USBD_T5-USBD_T5+

USBD_T5+

USBD_T4-

USBD_T4+

USBD_T5-

USBD_T1+

USBD_T0-

USBD_T0+

USBD_T1-

USBH_DT3-

USBH_DT3+ USBD_T3+

USBD_T3-

USBD_T2+

USBD_T2-

USBD_T2+

VUSB2

USBD_T2-USBD_T3+USBD_T3-

USBH_DT3+USBH_DT3-

-ROC2_3-USB_OC0_1[4]

-USB_OC4_5[4]

USB_DT4+[4]

USB_DT5-[4]

USB_DT4-[4]

USB_DT5+[4]

USB_DT0+[4]

USB_DT0-[4]

USB_DT2-[4]

USB_DT2+[4]

-USB_OC2_3[4]

USB_DT1+[4]

USB_DT1-[4]

USB_DT3-[4,23]USB_DT3+[4,23]

+5VDUAL

+5VDUAL

+5VDUAL

Title


Date: Sheet of


COMEDB4

USB 2.0 Ports


AC

Title


Date: Sheet of


COMEDB4

USB 2.0 Ports


AC

Title


Date: Sheet of


COMEDB4

USB 2.0 Ports


AC

VIA Confidential

USB 2.0 Port 0/1

USB 2.0 Port 4/5

NOTE: Please place close to USB pin header


USB 2.0 Port 2/3

JP_USBP3_SEL JP_USBME_SEL

1 - 2 & 3 - 4 *USB Port 3

Mini PCIE USB

NA

NA

USB Port Select

USB Port Selection Table

1 - 2 & 3 - 4

L32ACM2012-900-2P-T002L32ACM2012-900-2P-T002

1 4

32

R144 68KR144 68K

R14582KR14582K

L4ACM2012-900-2P-T002L4ACM2012-900-2P-T002

1 4

32

L56ACM2012-900-2P-T002L56ACM2012-900-2P-T002

1 4

32

R676 68KR676 68K

R3182KR3182K

FB14CBF-2012ES-121UFB14CBF-2012ES-121U

+

CE2220uF

+

CE2220uF

12

+

CE46220uF

+

CE46220uF

12



PS92APS92A

12

JP_USBP3_SEL(1-2)

MINI-JUMPER

JP_USBP3_SEL(1-2)

MINI-JUMPER

USB2_2/3

210-92-05GY02

USB2_2/3

210-92-05GY02

13 4

2

5 67

108

C471000pFC471000pF

L3ACM2012-900-2P-T002L3ACM2012-900-2P-T002

1 4

32

C4100.1uFC4100.1uF

R67782KR67782K

C1481uFC1481uF

L30ACM2012-900-2P-T002L30ACM2012-900-2P-T002

1 4

32

C70.1uFC70.1uF

C4091uFC4091uF

C1470.1uFC1470.1uF

C1381000pFC1381000pF

JP_USBP3_SEL(3-4)

MINI-JUMPER

JP_USBP3_SEL(3-4)

MINI-JUMPER

R23 68KR23 68K

C1430.1uFC1430.1uF

JP_USBP3_SEL

2213S-04G-F2

JP_USBP3_SEL

2213S-04G-F2

13 4

2

L57ACM2012-900-2P-T002L57ACM2012-900-2P-T002

1 4

32

C40.1uFC40.1uF

C4081000pFC4081000pF

C381uFC381uF

USB2_4/5

UB1112C-8FDE-4F

USB2_4/5

UB1112C-8FDE-4F

U1U2U3U4

U5U6U7U8

G1 G3

G2 G4

C4110.1uFC4110.1uF

USB2_0/1

210-92-05GY02

USB2_0/1

210-92-05GY02

13 4

2

5 67

108

PS152APS152A

12

PS22APS22A

12

+

CE58220uF

+

CE58220uF

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SS_RX0+

SS_TX0-

SS_RX0-

5V_P05V_P1

USB3_SSRX0+

SS_TX0-

USB3_SSTX0+_


USB3_SSRX0-

USB3_SSTX0-_

SS_TX0+

SS_RX0-

SS_TX0-SS_RX0+

SS_TX0+USB3_SSTX1-_

USB3_SSTX1-_

SS_TX1+

USB3_SSTX1+_

USB3_SSTX1+_

SS_TX1-

USB2_HP7+

USB2_HP7-

USB2_DT7-USB2_DT7+

SS_TX1+

USB2_HP7-

SS_TX1-

USB2_HP7+

USB2_HP6-USB2_HP6+

USB3_SSTX0+_


USB3_SSTX1+_

SS_RX0-

SS_RX0+

SS_TX0+

SS_RX1-

SS_RX1+

SS_RX1-SS_RX1+


USB2_HP6-

USB2_HP6+

USB2_HP6-USB2_HP6+

USB2_DT6-USB2_DT6+

SS_RX1-

USB2_HP7-

SS_TX1+SS_TX1-

USB2_HP7+

SS_RX1+

USB2_DT7+ [4]

USB2_DT7- [4]

USB3_SSTX0+ [5]

USB3_SSTX0- [5]

USB3_SSTX1+ [5]

USB3_SSTX1- [5]

USB3_SSRX0+ [5]

USB3_SSRX0- [5]

USB3_SSRX1- [5]

USB3_SSRX1+ [5]

USB2_DT6+ [4]

USB2_DT6- [4]

-USB2_OC6_7 (9)

+5VDUAL

+5VDUAL

Title


Date: Sheet of


COMEDB4

USB 3.0 Ports


AC

Title


Date: Sheet of


COMEDB4

USB 3.0 Ports


AC

Title


Date: Sheet of


COMEDB4

USB 3.0 Ports


AC

Co-Layout VIA ConfidentialCo-Layout


USB 3.0 Port 0 & 180 mils

80 mils

FB44QT2012RL080HC3A-LF


L20 ACM2012-900-2P-T002L20 ACM2012-900-2P-T002

1 4

32

L15 DLW2012B-900NPL15 DLW2012B-900NP1 4

32

RN16 0/XRN16 0/X1 23 4

R147560KR147560K

L18 DLW2012B-900NPL18 DLW2012B-900NP

1 4

32

RN20 0/XRN20 0/X

1 23 4

C101 0.1uFC101 0.1uF



+

CE39560uF

+

CE39560uF

12

C3010.1uFC3010.1uF

RN18 0/XRN18 0/X1 23 4

RN21 0/XRN21 0/X

1 23 4

RN17 0/XRN17 0/X

1 23 4

L19 ACM2012-900-2P-T002L19 ACM2012-900-2P-T002

1 4

32

C99 0.1uFC99 0.1uF


Line-1 1Line-2 2GND 3

Line-3 4Line-4 5NC6

NC7

NC9

NC10

D19 AZ

C19

9-02

S.R

7GD

19 AZ

C19

9-02

S.R

7G

1 23

C3000.1uFC3000.1uF

+

CE38560uF

+

CE38560uF

12

D20 AZ

C19

9-02

S.R

7GD

20 AZ

C19

9-02

S.R

7G1 2

3

PS10

2A

PS10

2A1 2

L16 DLW2012B-900NPL16 DLW2012B-900NP

1 4

32

R114 470KR114 470K

C881000pFC881000pF

C98 0.1uFC98 0.1uF

R148 470KR148 470K

R149560KR149560K


Line-11Line-22GND3Line-34Line-45 NC 6

NC 7

NC 9

NC 10

PS14

2A

PS14

2A1 2

L17 DLW2012B-900NPL17 DLW2012B-900NP1 4

32

USB3_LANA

05-000730003-1

USB3_LANA

05-000730003-1

U9U8U7U6

U18U17U16U15

G1 G3G2

U5

U1U2U3U4

U14

U10U11U12U13

G4

C97 0.1uFC97 0.1uF

C871000pFC871000pF

RN19 0/XRN19 0/X

1 23 4

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LAN_-ACT

T_CT1

T_CT4

T_CT3

T_CT2

MCT2

MCT1

MCT0

-SP1000

-SP100

-ACT

-MDI0+MDI0

+MDI2-MDI2

-MDI3+MDI3

+MDI1

-MDI1

MCT3

MDI2-

MDI3+

MDI3-

MDI0+

MDI0-

MDI1+

MDI1-

MDI2+

-MDI3+MDI3

+MDI2-MDI2

-MDI1+MDI1

+MDI0-MDI0

MDI3+MDI3-

MDI2+MDI2-

MDI0+MDI0-

MDI1+MDI1-

MDI3+MDI3-

MDI2+MDI2-

MDI0+MDI0-

MDI1+MDI1-

W_LESS_LED[23]

LAN_-SP100 [4]

LAN_-SP1000 [4]

MDI0- [4]MDI0+ [4]

MDI1- [4]MDI1+ [4]

MDI3- [4]MDI3+ [4]

MDI2- [4]MDI2+ [4]

VDDTXRX_LAN [4]

LAN_-ACT [4]

+3.3VDUAL

+3.3VDUAL

Title


Date: Sheet of


COMEDB4

RJ45/ LAN LED


AC

Title


Date: Sheet of


COMEDB4

RJ45/ LAN LED


AC

Title


Date: Sheet of


COMEDB4

RJ45/ LAN LED


AC

VIA Confidential

RJ45

1st : LAN LED

Wireless LAN LEDStandby PW LED(optional)

FRONT LAN LED

GST5009 LF / LG-2413S-1 / P1012

place near T1(transformer)

99G26-07053299G26-070542

99G26-07056F

99G26-07053J

/ VT6122 / VT6130

BothhandGST5009 LF

LG-2413S-1

P1012(001-00)

TST1284A LF

LF-H6442S-1

VT6107

P1212(007-00)

T1

LANKOM

UDE

VT6130 / RTL8111G T1 install GST5009 LFVT6107 T1 install TST1284A LF

RTL8111G

VT6122 /

O:mount X:unmount

VT6107

RTL8111G

VT6122

GST5009 LF99G26-070532

TST1284A LF99G26-070542

T1 C124,C115

99G26-070532GST5009 LF

FB17 C118,C112,C105,C102(6.8pFx4)

O

X

X

O

O

X

X

10M Bits

Note:

LED Selection

RJ45 Link status GMTI_05-000730003-1 for RTL8111G

LAN Connector not Plug

Link: LED on

R111

O O

R104, R109

O X

X X

C104C110

0.01uF

0.1uF

X X

O X X

O

99G26-07055F

99G26-07058J

VT6130GST5009 LF99G26-070532 O O 0.1uF O O O X

LED0

LED1

LED2

NEW_1

ACT

SP100

SP1000

LEDCFG (0F, 42)

Link Active

Black Black

Black Orange (Blinking)

100M Bits Orange (Blinking)

1000M Bits Orange (Blinking)

Green

Orange

R10675R10675

R129 330R129 330

C114 0.1uFC114 0.1uF

R99 330R99 330

D24

RClamp0544T.TCT

D24

RClamp0544T.TCT

2

G1

34

1

56

78

R128 330R128 330R127 330R127 330

T1

GST5009 LF

T1

GST5009 LF

TCT1 1

TD1+ 2

TD1- 3

TCT2 4

TD2+ 5

TD2- 6

TCT3 7

TD3+ 8

TD3- 9

TCT4 10

TD4+ 11

TD4- 12

MCT124

MX1+23

MX1-22

MCT221

MX2+20

MX2-19

MCT318

MX3+17

MX3-16

MCT415

MX4+14

MX4-13

C1040.01uFC1040.01uF

D16

RClamp0544T.TCT

D16

RClamp0544T.TCT

2

G1

34

1

56

78

R110 330R110 330

C1100.1uF/XC1100.1uF/X

C125 1000pF/25VC125 1000pF/25V

R1090R1090

FB17CBG201209-260/XFB17CBG201209-260/X

R10875R10875

FLAN_LED

2208S-10G-E09-F2

FLAN_LED

2208S-10G-E09-F2

134

2

567

108

R10175R10175

C1150.1uF/XC1150.1uF/X

Yellow/R

Green/L

Yellow/L

TX_D1+TX_D1-

BI_D3+

BI_D4-

BI_D3-RX_D2-BI_D4+

RX_D2+

USB3_LANB05-000730003-1

Yellow/R

Green/L

Yellow/L

TX_D1+TX_D1-

BI_D3+

BI_D4-

BI_D3-RX_D2-BI_D4+

RX_D2+

USB3_LANB05-000730003-1

R1R2R3R4R5R6

R8R7

G5G6

G7

G8L4L3L2L1

C1186.8pF/XC1186.8pF/X

R100 330R100 330

C1126.8pF/XC1126.8pF/X

C1240.1uF/XC1240.1uF/X

C1056.8pF/XC1056.8pF/X

R126 330R126 330

R1040R1040

R1110R1110

C1026.8pF/XC1026.8pF/X

R11875R11875

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-LP1

ML1_IN0+_DPML1_IN0-_DP


AUX1_IN-

ML1_IN2+_DP

VCC3_DP120_LF1

ML1_IN2-_DP


CA_DET_DP1DP1_HPD

CAD_INV1

DP1TX2-

DP1TX3-

DP1TX_0-_

DP1TX_0+_

DP1TX0-

DP1TX_2+_DP1TX_1-_

DP1TX_1+_

DP1_P19DP1TX_2-_ DP1_HPD

DP1TX1-

DP1_P15

DP1_P17

DP1TX0+_

DP1TX_3+_DP1TX3+

DP1TX2+

DP1_P13

DP1TX2+_

DP1_P14

DP1TX1-_

DP1TX2-_DP1TX3+_

DP1TX1+_DP1TX0-_

DP1_P16

DP1_P19

DP1_P17DP1_P18

DP1_P15

DP1TX1+ DP1_P16

DP1_P18

DP1TX0+

DP1TX3-_DP1TX_3-_

DP1TX3+_

DP1TX0-_

DP1TX1+_DP1TX1-_

DP1TX2+_

DP1TX3-_

DP1TX2-_DP1TX0+_ DP1TX2+_

DP1TX1+_ DP1TX3+_DP1TX3-_

DP1TX0+_DP1TX0-_ DP1TX2-_

DP1TX1-_

DP1_HPD

CAD_OUT1

DP1_ADJ_AUX_IN+DP1_P17DP1_P15

DP1_P13

DP1_P14

CA_DET_DP1

DP1_P17 DP1_P17

DP1_PWR_

DP1_P15 DP1_P15

DP1_P18 DP1_P18DP1_P13 DP1_P13

DP1TX_1+_

DP1TX_0+_DP1TX_0-_

DP1TX_1-_DP1TX1-

DP1TX0-DP1TX1+

DP1TX0+

DP1TX_3+_

DP1TX_2+_DP1TX_2-_

DP1TX_3-_DP1TX3-

DP1TX2-DP1TX3+

DP1TX2+

DP1TX0+DP1TX0-

DP1TX3+DP1TX3-

DP1TX1+DP1TX1-

DP1TX2+DP1TX2-

-DP1_HPD[5]

DP1_AUX+[5]

DP1_AUX-[5]

DP1_LANE3+[5]DP1_LANE3-[5]




+3.3V

+3.3V

DP1_PWR

DP1_PWR

+2.5V

+3.3V

+12V_VCC

DP1_PWR

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

VIA Confidential

DP reDriver

HPD 19

ML_Lane0-

1817 AUX_CH-16

GNDML_Lane3+

14

H.P. Detect

2

20

GND

5

ML_Lane0+GND

AUX_CH+

12

6

4

7

3

DP_PWR_Return

ML_Lane1+

GND

GND

GND

11

13

ML_Lane2-10

ML_Lane2+

9

ML_Lane3-

15

8

DisplayPort

1

GND

ML_Lane1-

DP_PWR

ESD

ESD Rcalmp RCLAMP0524P(Package:GSLP2510P8) RCLAMP0544T(Package:GSLP2010P8T)

LP Mode

Hi = Normal ModeLo = Low Power Mode

C127 0.1uFC127 0.1uF


G

DS

R131 0R131 0

C1220.01uFC1220.01uF D23

RClamp0544T.TCTD23RClamp0544T.TCT

2

G1

34

1

56

78

FB15 QT2012RL060FB15 QT2012RL060

U16

SN75DP120RHHT

U16

SN75DP120RHHT

VC

C1

4

CAD_INV31

GN

D2

7

LP33

HPD_OUT11CAD_OUT12

VC

C2

16

GN

D3

13

ML_OUT3- 19

VC

C3

24

ML_OUT2+ 23

ML_OUT2- 22

GN

D4

21

ML_OUT1+ 26

ML_OUT1- 25

VC

C4

28

ML_OUT0+ 30

ML_OUT0- 29

HP

D_I

NV

27

CAD_IN 14

HPD_IN 15

DP_ADJ/AUX_IN+ 17NC/AUX_IN- 18

GN

D6

32V

CC

536

ML_IN3+8

ML_IN3-9

ML_IN2+5

ML_IN2-6

ML_IN1+2

ML_IN1-3

VD

D10

ML_IN0+34

ML_IN0-35

G1

G1

GN

D1

1

ML_OUT3+ 20

RN28 0/XRN28 0/X

1 23 4

C130 0.1uFC130 0.1uF

R122 0_0805/XR122 0_0805/X

L24 DLW2012B-900NPL24 DLW2012B-900NP1 4

32

C1350.1uFC1350.1uF

C152 0.1uFC152 0.1uF

C1360.01uFC1360.01uF

R632 0R632 0

R125100KR125100K

R116 0R116 0

C154 0.1uFC154 0.1uF

C159 0.1uFC159 0.1uF

C137100pFC137100pF

R115 0R115 0

C1201uFC1201uF

RN27 0/XRN27 0/X1 23 4

R138 4.7KR138 4.7K

R124 0R124 0

C1310.1uFC1310.1uF

C144 0.1uFC144 0.1uF

DP1

62U020S-330N-A1B-B

DP1

62U020S-330N-A1B-B

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

M1 M1

G1

G1

G2

G2

G3

G3

G4

G4

C132 0.1uFC132 0.1uF

C146 0.1uFC146 0.1uFC149 0.1uFC149 0.1uF

R1420R1420

C126 0.1uFC126 0.1uF

R136 100KR136 100K

C1191uFC1191uF

R112 0R112 0

R137 0/XR137 0/X


2

G1

34

1

56

78

RN29 0/XRN29 0/X

1 23 4

L22 DLW2012B-900NPL22 DLW2012B-900NP1 4

32

R633 0R633 0

RN26 0/XRN26 0/X1 23 4

C157 0.1uFC157 0.1uF

C134 0.1uFC134 0.1uF

R117 100K/XR117 100K/X

C140 0.1uFC140 0.1uF

R140 100KR140 100K

C139 0.1uFC139 0.1uF

R134 100KR134 100K

L21 DLW2012B-900NPL21 DLW2012B-900NP1 4

32

C3420.01uFC3420.01uF D22

RClamp0544T.TCTD22RClamp0544T.TCT

2

G1

34

1

56

78

C162 0.1uFC162 0.1uF

C129 0.1uFC129 0.1uF

R113 0R113 0

L23 DLW2012B-900NPL23 DLW2012B-900NP1 4

32

C3410.1uFC3410.1uF

C1330.1uFC1330.1uF

PS8

SMD1812P160TF/8(4L)

PS8

SMD1812P160TF/8(4L)

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-LP2



AUX2_IN-

ML2_IN2+_DP

VCC3_DP120_LF2

ML2_IN2-_DP


CA_DET_DP2DP2_HPD

CAD_INV2

DP2TX2-

DP2TX3-

DP2TX_0-_

DP2TX_0+_

DP2TX0-

DP2TX_2+_DP2TX_1-_

DP2TX_1+_


DP2TX1-

DP2_P15

DP2_P17

DP2TX0+_

DP2TX_3+_DP2TX3+

DP2TX2+

DP2_P13

DP2TX2+_

DP2_P14

DP2TX1-_

DP2TX2-_DP2TX3+_

DP2TX1+_DP2TX0-_

DP2_P16

DP2_P19

DP2_P17DP2_P18

DP2_P15

DP2TX1+ DP2_P16

DP2_P18

DP2TX0+

DP2TX3-_DP2TX_3-_

DP2TX3+_

DP2TX0-_

DP2TX1+_DP2TX1-_

DP2TX2+_

DP2TX3-_




DP2TX1-_

DP2_HPD

CAD_OUT2

DP2_ADJ_AUX_IN+DP2_P17DP2_P15

DP2_P13

DP2_P14

CA_DET_DP2

DP2_PWR_

DP2TX_1+_

DP2TX_0+_DP2TX_0-_

DP2TX_1-_DP2TX1-

DP2TX0-DP2TX1+

DP2TX0+

DP2TX_3+_

DP2TX_2+_DP2TX_2-_

DP2TX_3-_DP2TX3-

DP2TX2-DP2TX3+

DP2TX2+

DP2TX0+DP2TX0-

DP2TX3+DP2TX3-

DP2TX1+DP2TX1-

DP2TX2+DP2TX2-

DP2_P13DP2_P15

DP2_P13DP2_P15

DP2_P17 DP2_P17DP2_P18 DP2_P18-DP2_HPD[5]

DP2_AUX+[5]

DP2_AUX-[5]





+3.3V

+3.3V

DP2_PWR

DP2_PWR

+2.5V

+3.3V

+12V_VCC

DP2_PWR

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

VIA Confidential

DP reDriver

HPD 19

ML_Lane0-

1817 AUX_CH-16

GNDML_Lane3+

14

H.P. Detect

2

20

GND

5

ML_Lane0+GND

AUX_CH+

12

6

4

7

3

DP_PWR_Return

ML_Lane1+

GND

GND

GND

11

13

ML_Lane2-10

ML_Lane2+

9

ML_Lane3-

15

8

DisplayPort

1

GND

ML_Lane1-

DP_PWR

ESD


LP Mode


Rev A

R647 0R647 0

C361 0.1uFC361 0.1uF

C3570.01uFC3570.01uF

R643 0R643 0

C363 0.1uFC363 0.1uF

U37

SN75DP120RHHT

U37

SN75DP120RHHT

VC

C1

4

CAD_INV31

GN

D2

7

LP33

HPD_OUT11CAD_OUT12

VC

C2

16

GN

D3

13

ML_OUT3- 19

VC

C3

24

ML_OUT2+ 23

ML_OUT2- 22

GN

D4

21

ML_OUT1+ 26

ML_OUT1- 25

VC

C4

28

ML_OUT0+ 30

ML_OUT0- 29

HP

D_I

NV

27

CAD_IN 14

HPD_IN 15


GN

D6

32V

CC

536

ML_IN3+8

ML_IN3-9

ML_IN2+5

ML_IN2-6

ML_IN1+2

ML_IN1-3

VD

D10

ML_IN0+34

ML_IN0-35

G1

G1

GN

D1

1

ML_OUT3+ 20

C3510.01uFC3510.01uF

R635 100K/XR635 100K/X

C3660.1uFC3660.1uF

C369 0.1uFC369 0.1uF


2

G1

34

1

56

78

C374 0.1uFC374 0.1uF

C3560.1uFC3560.1uF

C360 0.1uFC360 0.1uF

L48 DLW2012B-900NPL48 DLW2012B-900NP1 4

32

R637 0R637 0

C359 0.1uFC359 0.1uF

C3500.01uFC3500.01uF

R634 0R634 0


2

G1

34

1

56

78

R648 100KR648 100K

R642 0_0805/XR642 0_0805/X

C3551uFC3551uF

R640 0/XR640 0/X

L50 DLW2012B-900NPL50 DLW2012B-900NP1 4

32

R644 0R644 0

DP2

62U020S-330N-A1B-B

DP2

62U020S-330N-A1B-B

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

M1 M1

G1

G1

G2

G2

G3

G3

G4

G4

R650100KR650100K

R636 100KR636 100K

C371 0.1uFC371 0.1uF

C373 0.1uFC373 0.1uFR649 0R649 0


G

DS

R639 0R639 0

R645 0R645 0

C358 0.1uFC358 0.1uF

PS13

SMD1812P160TF/8(4L)

PS13

SMD1812P160TF/8(4L)

1 2

C375100pFC375100pF

C3541uFC3541uF

C368 0.1uFC368 0.1uF

C365 0.1uFC365 0.1uF

C372 0.1uFC372 0.1uF

R638 4.7KR638 4.7K

C362 0.1uFC362 0.1uF


2

G1

34

1

56

78

RN31 0/XRN31 0/X1 23 4

RN30 0/XRN30 0/X1 23 4

FB46 QT2012RL060FB46 QT2012RL060

C3530.1uFC3530.1uF

C367 0.1uFC367 0.1uF

C364 0.1uFC364 0.1uF

RN33 0/XRN33 0/X

1 23 4

L47 DLW2012B-900NPL47 DLW2012B-900NP1 4

32

RN32 0/XRN32 0/X

1 23 4

R6410R6410

R646 100KR646 100K

C3520.1uFC3520.1uF

C370 0.1uFC370 0.1uFL49 DLW2012B-900NPL49 DLW2012B-900NP

1 4

32

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LED_A

LED_B

LED_E

LED_G

LED_C

LED_F

LED_D

-DGH

-DGL

-DGH_

-DGL_

-DGHLED_B

LED_ELED_C

LED_G

LED_DLED_FLED_A

-DGL

SD_FBS

COM_GPO2

COM_GPO3

SPKR [4,6]

SPEAK [15]

LCLK_AK2001 [12]

-LPC_FRAME [4,8,10]

LPC_AD0 [4,8,10]

LPC_AD1 [4,8,10]

LPC_AD2 [4,8,10]

LPC_AD3 [4,8,10]

-80_PORT_RESET [13]

COM_GPO1 [4,15]

COM_GPO3 [4,15]

COM_GPI0 [4,15]COM_GPI1 [4,15]COM_GPI2 [4,15]

COM_GPI3 [4,15]

COM_GPO0 [4,15]

COM_GPO2 [4,15]

SD_PWOFF[4]

SD_PWSELS[4]SD_PWOFF [4]

+3.3V

+3.3VSUS

+5VSUS

+5V

-12V

+12V_VCC

+5V

+5V

+3.3V

+3.3V

+3.3V

SD_SOCKET

SD_SOCKET

+5VSUS

SD_SOCKET

+5VSUS

+3.3VDUAL

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

LED

=R 30mA

V- Vf------------

LED If=30mAVf= 1.9V ~ 2.6V

VIA Confidential

BUZZER

LPC DEBUG PORT

SD/MMC Socket

VOUT=(R2/R1+1)*0.8V

CARD READER Socket +3.3V/+1.8V PWR SEL

Near Socket

H: 1.8VL: 3.3V

R2

R1

SD_CD#

GPIO SDIO

COM_GPI2COM_GPI3

COM_GPI0COM_GPI1

COM_GPO2COM_GPO3

COM_GPO0COM_GPO1

SD_D0SD_D1SD_D2SD_D3SD_CLKSD_CMDSD_WP

R361 51R361 51

R36868R36868

+5V_DUAL_LED

LED LAMP GREEN

+5V_DUAL_LED

LED LAMP GREEN

1 2

C4021uFC4021uF

C40522uFC40522uF

R351 22R351 22

R363 360R363 360C40 10uFC40 10uF

R67520R67520

U39

APW7142KI-TRG

U39

APW7142KI-TRG

PGND1

VIN2

AGND3

FB4 COMP 5EN 6

LX_1 7LX_2 8

Q462N7002Q462N7002

G

DS

R365 360R365 360

C40622uFC40622uF

C4030.1uFC4030.1uF

C20 0.1uFC20 0.1uF

R18 33R18 33

U4

AK2001-G

U4

AK2001-G

DGH#1

GND2

LEDA3

LEDB4

LEDC5

LEDD6

LEDE7

LEDF8

LEDG9

VCC110 DGL# 11

GND 12

PCICLK 13

LFRAME# 14

LAD0 15

LAD1 16

LAD2 17

LAD3 18

PCIRST# 19

VCC2 20

C15 0.1uFC15 0.1uFR364 110R364 110

R669 10K/XR669 10K/X

C407220pFC407220pF

C3331uFC3331uF

Q472N7002Q472N7002G

DS

R350 4.7KR350 4.7K

C40456pFC40456pF

R362 110R362 110

L55 EB-22AM08N01L55 EB-22AM08N01

R347 1KR347 1K

Q452N7002Q452N7002

G

D S

PORT_80

ELD-305SURWA/S530-A2

PORT_80


DG1

DA3

DF4

SEL0#5 DD 6DE 7DC 8DB 9

SEL1# 10

BUZZER

BU-SAT-1205HE3-LF

BUZZER

BU-SAT-1205HE3-LF

12

R6721KR6721K

-12V_LED

LED LAMP GREEN

-12V_LED

LED LAMP GREEN

12

+3_3VSUS_LED

LED LAMP GREEN

+3_3VSUS_LED

LED LAMP GREEN

1 2

+5V_LED

LED LAMP GREEN

+5V_LED

LED LAMP GREEN

1 2

R668 10K/XR668 10K/X

R6702.2K_1%R6702.2K_1%


B

EC

R67443KR67443K

+12V_VCC_LED

LED LAMP GREEN

+12V_VCC_LED

LED LAMP GREEN

1 2

+3_3V_LED

LED LAMP GREEN

+3_3V_LED

LED LAMP GREEN

1 2

R33 33R33 33

R6713.3K_1%R6713.3K_1%

SDIO

SDC013-A0-501F

SDIO

SDC013-A0-501F

DAT3 1

CMD 2

VSS1 3

VDD 4

CLK 5

VSS2 6

DAT0 7

DAT1 8

DAT2 9

DAT4 10

DAT5 11

DAT6 12

DAT7 13

SD_CDT 14

SD_WP 15

GND M1

GND M2

GND M3

GND M4

G1

G1

G2

G2

R360 51R360 51

R6731.05K_1%R6731.05K_1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-PE1PRT2_2

-PE2_RST

-PE1PRT2_2

-PE1_RST-PE_WAKE

SMB_DATSMB_CLK

-PE1PRT2_2

PCIETX2+PCIETX2-

PCIETX1+PCIETX1-

-PE1PRT2_2

-PE3_RST-PE_WAKE

SMB_DATSMB_CLK

PCIETX0+PCIETX0-

-PE1_RST

-PE3_RST

-PE2_RST

SMB_CLK[4,12,15,23]SMB_DAT[4,12,15,23]


-PE_WAKE[4,23]


PCIE_TX1-[4]PCIE_TX1+[4]

PCIE_RX1- [4]PCIE_RX1+ [4]


-PE_RST0[4]

-MPE_RST [23]

-PE_RST1[4]





+3.3VDUAL

+3.3V +12V_VCC

+12V_VCC

+3.3V+3.3V

+12V_VCC

+3.3VDUAL

+12V_VCC

+3.3V+3.3V

+12V_VCC+12V_VCC

+3.3V

+3.3V

+3.3VDUAL

+12V_VCC

+3.3V+3.3V

+3.3VDUAL

+12V_VCC+12V_VCC

+3.3V

+3.3VDUAL

+3.3V+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3VDUAL

Title


Date: Sheet of


COMEDB4

PCI Express x1 Slots


AC

Title


Date: Sheet of


COMEDB4



AC

Title


Date: Sheet of


COMEDB4



AC

#2 PCIE X 1 SLOT#1 PCIE X 1 SLOT

VIA Confidential

#3 PCIE X 1 SLOT

+CE45 100uF+CE45 100uF1 2

C339 0.1uFC339 0.1uF

+CE43 470uF/16V+CE43 470uF/16V1 2

C322 0.1uFC322 0.1uF

R305 2.2KR305 2.2K

C261 0.1uFC261 0.1uF

C310 0.1uFC310 0.1uF

C340 0.1uFC340 0.1uF

+CE49 100uF+CE49 100uF1 2

+CE44 100uF+CE44 100uF1 2

C258 0.1uFC258 0.1uF C297 0.1uFC297 0.1uF

C309 0.1uFC309 0.1uF

U43E

SN74LV04ADR

U43E

SN74LV04ADR

11 10

147

C4560.1uFC4560.1uF

+CE48 100uF+CE48 100uF1 2

C308 0.1uFC308 0.1uF

+CE55 470uF/16V+CE55 470uF/16V1 2

U43A

SN74LV04ADR

U43A

SN74LV04ADR

1 2

147

C283 0.1uFC283 0.1uF

U43C

SN74LV04ADR

U43C

SN74LV04ADR

5 6

147

Mechanical Key

PCI_Express_x1


PE3

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE3

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

Mechanical Key

PCI_Express_x1


PE1

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE1

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

U43B

SN74LV04ADR

U43B

SN74LV04ADR

3 4

147

Mechanical Key

PCI_Express_x1


PE2

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE2

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

+CE56 100uF+CE56 100uF1 2

C285 0.1uFC285 0.1uF

+CE57 100uF+CE57 100uF1 2

U43F

SN74LV04ADR

U43F

SN74LV04ADR

13 12

147

C260 0.1uFC260 0.1uF

U43D

SN74LV04ADR

U43D

SN74LV04ADR

9 8

147

R721 22R721 22

R720 22R720 22

C284 0.1uFC284 0.1uF

+CE47 470uF/16V+CE47 470uF/16V1 2

R722 22R722 22

R723 22R723 22

C296 0.1uFC296 0.1uFC259 0.1uFC259 0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


-CLKR

PCIETX3+PCIETX3-

USB_MEDT3+

USB_ME_T3-

USB_ME_T3+USB_MEDT3-

-MPE_RST [22]

SMB_CLK [4,12,15,22]SMB_DAT [4,12,15,22]

PCIE_RX3-[4]PCIE_RX3+[4]


PCIE_CLK4-[12]PCIE_CLK4+[12]

-PE_WAKE[4,22]

-PEREQ_1[12]

-W_DISABLE [8]

USB_DT3+[4,16]USB_DT3-[4,16]

W_LESS_LED [18]

+1.5V

+3.3VDUAL

+3.3VDUAL

+3.3VDUAL

+1.5V

+3.3VDUAL

Title


Date: Sheet of


COMEDB4

Mini PCIe Slot


AC

Title


Date: Sheet of


COMEDB4

Mini PCIe Slot


AC

Title


Date: Sheet of


COMEDB4

Mini PCIe Slot


AC

VIA Confidential

Mini PCIE Socket

C313 4.7uFC313 4.7uF

MINICARD CONN

MINI_PCIE

0710A0BA68B

MINICARD CONN

MINI_PCIE

0710A0BA68B

+3.3VAUX 52

GND 50

+1.5V 48

LED_WPAN# 46

LED_WLAN# 44

LED_WWAN# 42

GND 40

USB_D+ 38

USB_D- 36

GND 34

SMB_DATA 32

SMB_CLK 30

+1.5V 28

GND 26

+3.3VAUX 24

PERST# 22

W_DISABLE# 20

GND 18

UIM_VPP 16

UIM_RESET 14

UIM_CLK 12

UIM_DATA 10

UIM_PWR 8

+1.5V 6

GND 4

+3.3VAUX 2WAKE#1

Reserved51

Reserved49

Reserved47

Reserved45

GND43

+3.3VAUX41

+3.3VAUX39

GND37

GND35

PETp033

PETn031

GND29

GND27

PERp025

PERn023

GND21

Reserved(UIM_C4)19

Reserved(UIM_C8)17

GND15

REFCLK+13

REFCLK-11

GND9

CLKREQ#7

COEX25

COEX13

G1

G2

M1

M2

C312 4.7uFC312 4.7uF

L44ACM2012-900-2P-T002L44ACM2012-900-2P-T002

1 4

32

JP_USBME_SEL(1-2)/X

MINI-JUMPER

JP_USBME_SEL(1-2)/X

MINI-JUMPER

C314 0.1uFC314 0.1uF

C316 0.1uFC316 0.1uF

C299 0.1uFC299 0.1uF

JP_USBME_SEL

2213S-04G-F2

JP_USBME_SEL

2213S-04G-F2

13 4

2

C315 0.1uFC315 0.1uF

D35

RB751V-40/X

D35

RB751V-40/X

A K

C311 4.7uFC311 4.7uF

C298 0.1uFC298 0.1uF

JP_USBME_SEL(3-4)/X

MINI-JUMPER

JP_USBME_SEL(3-4)/X

MINI-JUMPER

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PWR_OK

TYPE1_2

TYPE0_

SUSB_PASS

SUSB

EN_3S

Q5_B

SUSBSUSB

Q20_B

PWR_OK [4]

-TYPE2[5]

-TYPE1[5]

-TYPE0[5]

-SUSB[4]

-SUSB [4]

PW_OK [26]

PS_ON[26]

+5V

+5VSUS

+3.3V

+12V_VCC

-12V

+5V

+5V

+3.3VBAT

+5VSUS

+12V_VCC

+5VDUAL+5VSUS

+5V

+5VSUS

+5VDUAL+3.3VDUAL

+5VSUS+5VSUS

+5VSUS

+5VSUS

+5VSUS

+3.3VSUS

+3.3V

+3.3VSUS

+3.3VDUAL

+12V +12V_VCC

+12V_VCC+12V

+12V_VCC+12V

DC_12V

Title


Date: Sheet of


COMEDB4

ATX Power Connector


AC

Title


Date: Sheet of


COMEDB4

ATX Power Connector


AC

Title


Date: Sheet of


COMEDB4

ATX Power Connector


AC

ATX POWER

VCC_RTC

ENABLE

NORMAL

FUNCTION

2 - 3

1 - 2

CLEAR_CMOS +3.3VSUS+5VDUAL

*

VIA Confidential

Iout Max = 2A

Vout = 0.8 * (1+R2/R1)

2A for Layoutreference

3.3V 2A~

R1

R2


Adjust this R-C todelay +3.3VSUS tosync VSUSVDDsequence

+3.3VDUAL

PWR

ATATX

JP_AT_SEL1,2

OPEN1-2 & 3-4 SHORT

0

10

S4/S5

S111 S3

Pstate-SUSC0

-SUSB-SUSA000

Discharge Circuit


2-3: AT mode

R3373.32K_1%R3373.32K_1%

ATXPWR

ATP12120-F0D8H /X

ATXPWR

ATP12120-F0D8H /X

3V3-113

-12V14

GND15

PS-ON16

GND17

GND18

GND19

-5V20

5V121

5V222

3V3-2 1

3V3-3 2

GND 3

5V4 4

GND 5

5V5 6

GND 7

PW-OK 8

5VSB 9

12V1 10

5V323

GND2412V2 11

3V3-4 12

C1990.1uFC1990.1uF

C1230.1uFC1230.1uF

JP_AT_SEL2(1-2)

2228BG-RD-F1

JP_AT_SEL2(1-2)

2228BG-RD-F1

C32310uFC32310uF

R8410KR8410K

TP_+12V_VCCTP_+12V_VCC

1


21

3

R1304.7K/XR1304.7K/X

VCC

GND

U17A

74HCT08D/X

VCC

GND

U17A

74HCT08D/X

1

23

147

Q172N7002Q172N7002G

DS

D40

B320A-13-F

D40

B320A-13-F

A K

C810.1uFC810.1uF

R1334.7KR1334.7K

C17610uFC17610uF

R70470_1%R70470_1%

R338 10.7K_1%R338 10.7K_1%

Q162N7002Q162N7002G

DS

R336 1KR336 1K

C9010uFC9010uF

Q122N7002Q122N7002

G

DS

JP_AT_SEL2

2213S-04G-F2

JP_AT_SEL2

2213S-04G-F2

13 4

2

CLEAR_CMOSCLEAR_CMOS

21

3

TP_+5VSUSTP_+5VSUS

1

+

CE41000uF/10V

+

CE41000uF/10V

12 C320 0.033uF/XC320 0.033uF/X

R83 10KR83 10K

C780.1uFC780.1uF

U26

UP0105PSW8

U26

UP0105PSW8

POK1

EN2

VIN3

CNTL4 NC 5

VOUT 6

FB 7

GND 8

PG

ND

G1

R139 1KR139 1K

CLEAR_CMOS(1-2)

MINI-JUMPER

CLEAR_CMOS(1-2)

MINI-JUMPER

R1583.48K_1%R1583.48K_1%

JP_AT/ATX_SEL5(1-2)

MINI-JUMPER

JP_AT/ATX_SEL5(1-2)

MINI-JUMPER

TP_+3_3VTP_+3_3V

1

JP_AT_SEL2(3-4)

2228BG-RD-F1

JP_AT_SEL2(3-4)

2228BG-RD-F1

JP_AT_SEL1(1-2)

2228BG-RD-F1

JP_AT_SEL1(1-2)

2228BG-RD-F1

R76 1KR76 1K

TP_+5VTP_+5V

1

R1234.7K/XR1234.7K/X

D39

B320A-13-F

D39

B320A-13-F

A K

BAT1A

BAT_3V

BAT1A

BAT_3V

1 2

BAT1AAA-BAT-029-K01BAT1AAA-BAT-029-K01

12

TP_+3_3VBATTP_+3_3VBAT

1

R67200_1%R67200_1%

R1434.7K/XR1434.7K/X

+

CE10470uF/16V+

CE10470uF/16V1

2


B

EC

R146 1KR146 1K

VCC

GND

U17C

74HCT08D/X

VCC

GND

U17C

74HCT08D/X

9

108

147

D12BAT54CD12BAT54C

1

23

R12022RES0603

R12022RES0603

+

CE111000uF/16V

+

CE111000uF/16V

12

VCC

GND

U17B

74HCT08D/X

VCC

GND

U17B

74HCT08D/X

4

56

147

R121100KR121100K

R1566.65K_1%R1566.65K_1%

R11922RES0603

R11922RES0603

+

CE91000uF/10V

+

CE91000uF/10V

12

C19810uFC19810uF

JP_AT_SEL1

2213S-04G-F2

JP_AT_SEL1

2213S-04G-F2

13 4

2

JP_AT_SEL1(3-4)

2228BG-RD-F1

JP_AT_SEL1(3-4)

2228BG-RD-F1

Q10

AP4800AGM

Q10

AP4800AGM

S11

S22

S33

G4 D4 5D3 6D2 7D1 8

Q202N7002Q202N7002G

DS

C19010uFC19010uF

TP_+5VDUALTP_+5VDUAL

1

Q192N7002Q192N7002G

DS

TP_-12VTP_-12V

1

C3190.1uFC3190.1uF

D10

SSM5817PT

D10

SSM5817PT

A K

+

CE12470uF/16V

+

CE12470uF/16V

12

C1170.1uFC1170.1uF

C1280.1uFC1280.1uF

C3061uFC3061uF

R69 0 /XR69 0 /X

R141100K/XR141100K/X

R68 1KR68 1K

C1800.1uFC1800.1uF

Q152N7002Q152N7002

G

DS

R135 0R135 0

R1621KR1621K

C1560.1uFC1560.1uF

C3054.7uFC3054.7uFR71

1KR711K

C32110uFC32110uF

TP_+3_3VSUSTP_+3_3VSUS

1

R641KR641K

R1324.7K/XR1324.7K/X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.5V_FB

1.5V_PHASE

1.5V_UGATE

1.5V_LGATE

1.5V_OCSET

1.5V_BOOT

+3.3V

+2.5V

+5V

+5V

+1.5V+5V

Title


Date: Sheet of


COMEDB4

System Power


AC

Title


Date: Sheet of


COMEDB4

System Power


AC

Title


Date: Sheet of


COMEDB4

System Power


AC

VIA Confidential

Iout Max = 3A

+2.5V

10.8VR280

+= )

L43 MAX. 6.5A

+1.5VR281

------------(

+1.5V

For Mini-PCIe Slot +1.5V

For SN75DP120 +2.5V

C2701uFC2701uF

R343 51K_1%R343 51K_1%

Q27BAPM7334KC-TRGQ27BAPM7334KC-TRG

4

35 6

C3271uFC3271uF

TP_+2_5VTP_+2_5V

1

C26810uFC26810uF

C3251uFC3251uF

R28188.7_1%R28188.7_1%

C2720.01uFC2720.01uF

TP_1_5VTP_1_5V

1

+

CE42100uF/6.3V

+

CE42100uF/6.3V

12

D34 RB551V-30D34 RB551V-30AK

C3240.1uFC3240.1uF

C274 0.1uFC274 0.1uF

L43WSRPG0603-4R7M-L

L43WSRPG0603-4R7M-L

C2730.1uFC2730.1uF

R34424K_1%R34424K_1%

U23

RT9202GS

U23

RT9202GS

PHASE8

OCSET7

FB6

VCC5

BOOT 1

UGATE 2

GND 3

LGATE 4

R286 20K_1%R286 20K_1%

+

CE52100uF/6.3V

+

CE52100uF/6.3V

12

R280100_1%R280100_1%

C326 30pFC326 30pF

Q27AAPM7334KC-TRGQ27AAPM7334KC-TRG2

17 8

C2710.1uFC2710.1uF

R342 10KR342 10K

U27

APL5930KAI-TRG

U27

APL5930KAI-TRG

VIN5

VCNTL6

POK7

EN8 GND 1FB 2

VOUT1 3VOUT2 4

VIN

1G

1

C2880.1uFC2880.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FB2

FPO_0

FSET1

PV

CC

2

OV1OV2

LGATE1

VC

C1

OCSET1

UGATE2

PHASE2

UGATE1

BOOT2

EN2

PHASE1

FSET2

LGATE2

PV

CC

1

Q20_8

BOOT1

Q19_G1

OCSET2

EN1

12_RC

Q50

_G

U41_VDDU17_PG

U41_VS5

U41_VS33

FB1

VC

C2

PV

CC

2

FPO

Q48_G

Q20_8

FPO_0

FPO

FPO_0

DV12

PW_OK [24]

PS_ON[24]

+5VSUS

+5V_A

+5V_A

+3.3V

+12V+5V

+5V_A

+5VSUS

+3.3V

+5VSUS

+12V

+5V

+5V

VINDC

VINDC

VINDC

+5V

+5V+12V

+12V

+5VSUS

+12V

DC_12V +12V+12VDC_12V

VINDC

+5VSUS

DC_12V VINDC

Title


Date: Sheet of


COMEDB4

DC-In 12V/ AT_ATX


AC

Title


Date: Sheet of


COMEDB4

DC-In 12V/ AT_ATX


AC

Title


Date: Sheet of


COMEDB4

DC-In 12V/ AT_ATX


AC

X7R

DC INPUT

X7R

R1

OCP = 20A

Vout = 0.6 * (1+R1/R2)

R2

202KHz

R2

255.4KHz

R1

Vout = 0.6 * (1+R1/R2)

16SEPC100M

16SEPC100M

6PEPC470MX

RA : add RC for EMI(option)

EXT SATA POWER


2-3: AT mode


2-3: AT mode

16SEPC100M

C4181uFC4181uF

JP_AT/ATX_SEL2(1-2)

MINI-JUMPER

JP_AT/ATX_SEL2(1-2)

MINI-JUMPER

Q55FDD8880_NLQ55FDD8880_NL

G

D S

C44410pFC44410pF

R6852R6852

C421 0.22uFC421 0.22uF

R6832R6832

+

CE62470uF

+

CE62470uF

12

R68915K_1%R68915K_1%

R7036.98K_1%R7036.98K_1%

TP_+12VTP_+12V

1

R72410KR72410K

S_PWR1

2317SEH-03

S_PWR1

2317SEH-03

321

D431SR154-400D431SR154-400

AK

R708220KR708220K

C4171uFC4171uF

R697750R697750

C4410.1uFC4410.1uF

C420 0.22uFC420 0.22uF

C45410pFC45410pF

C4131uFC4131uF

C4301000pF/X

C4301000pF/X

R70910R70910

C4261000pFC4261000pF

F3 429007F3 4290071 2

C4401uFC4401uF

R6842R6842

R6932.2/XR6932.2/X

C4191uFC4191uF

C4312200pFC4312200pF

C4480.1uFC4480.1uF

JP_ATX_SEL2(3-4)

2228BG-RD-F1/X

JP_ATX_SEL2(3-4)

2228BG-RD-F1/X

R698 24K_1%R698 24K_1%

C4161uFC4161uF

R7051K/XR7051K/X

+

CE241000uF/16V

+

CE241000uF/16V

12

C4220.1uFC4220.1uF

R69024K_1%R69024K_1%

R7131MR7131M

R71510KR71510K

R706 1KR706 1K

R7161KR7161K

R7181KR7181K

U42

TPS3510D

U42

TPS3510D

PGI1

GND2

FPO3

PSON4 VS33 5VS5 6VDD 7PGO 8

C446 1uFC446 1uF

+CE59100uF

+CE59100uF

12

R710 20K_1%R710 20K_1%

C4251uFC4251uF

L61QT2012RL060HC6A-LFL61QT2012RL060HC6A-LF

R7121MR7121M

R702 33K_1%R702 33K_1%R700 28K_1%R700 28K_1%

C414 1uFC414 1uF

ISL6228

U41

ISL6228HRTZ

ISL6228

U41

ISL6228HRTZ

FSET1 6

VC

C1

4

VIN1 5

VO1 9

FB1 8

OCSET225

PGOOD1 7

EN1 11

UGATE1 13

PHASE1 12

BOOT1 14

LGATE1 16

PVCC1 15

GN

DG

1

LGATE219

BOOT221

PHASE223

UGATE222

EN224

PGOOD228

FSET21

VO226OCSET1 10

FB227

PGND1 17

VC

C2

3

VIN22

PVCC220

PGND218

U40

78L05L-S08-R

U40

78L05L-S08-R

VOUT 1

GND 2

GND 3

NC1 4

VIN8

GND7

GND6

NC25

+

CE60100uF

+

CE60100uF

12

R726100KR726100K

C4291000pF/XC4291000pF/X

R717 100R717 100

R719 100_1%R719 100_1%

JP_ATX_SEL1

2213S-04G-F2

JP_ATX_SEL1

2213S-04G-F2

13 4

2

C4451000pFC4451000pF

C4430.1uFC4430.1uF

C44210uFC44210uF

C4371uFC4371uF

+

CE63100uF

+

CE63100uF

12

+

CE61470uF

+

CE61470uF

12

DC12VDC12V4

32

1

C447 1uFC447 1uF

C4121uFC4121uF

C45210uFC45210uF

R711732K_1%R711732K_1%

C4231000pFC4231000pF

R72510KR72510K

R694750R694750

C4350.1uFC4350.1uF

R69632.4K_1%R69632.4K_1%

R687 0R687 0

C415 1uFC415 1uF

S_PWR2

2317SEH-03

S_PWR2

2317SEH-03

321

C433 0.01uFC433 0.01uFR7016.34K_1%R7016.34K_1%

C336

0.022uF

C336

0.022uF

C4322200pFC4322200pF

JP_ATX_SEL1(3-4)

2228BG-RD-F1/X

JP_ATX_SEL1(3-4)

2228BG-RD-F1/X

Q50FDS6680AS_NLQ50FDS6680AS_NL

S1

1

S2

2

S3

3

G4

D4

5D

36

D2

7D

18

R714 1KR714 1K

D42 BAT54CD42 BAT54C1

23

Q48FDS6690A_NLQ48FDS6690A_NL

4

61

723

8 5

C4530.1uFC4530.1uF

C4380.1uFC4380.1uF

R6882.2/XR6882.2/X

L58 BCIHP1040-4R7ML58 BCIHP1040-4R7M L59 BCIHP1040-4R7ML59 BCIHP1040-4R7M


21

3

C4511uFC4511uF

C4240.1uFC4240.1uF


21

3

R7074.7KR7074.7K

C449 10uFC449 10uF

Q49SI4914BDY-T1-GE3

Q49SI4914BDY-T1-GE31 2

87

3

4

65

C450 10uFC450 10uF

C4361uFC4361uF

R686 0R686 0

C4391000pFC4391000pF

C434 0.01uFC434 0.01uF

C4550.47uFC4550.47uF

R6822R6822

C4271uFC4271uF

R69547K_1%R69547K_1%

JP_ATX_SEL2(1-2)

2228BG-RD-F1/X

JP_ATX_SEL2(1-2)

2228BG-RD-F1/X

L60QT2012RL060HC6A-LFL60QT2012RL060HC6A-LF

Q532N7002

Q532N7002

G

DS

JP_ATX_SEL2

2213S-04G-F2

JP_ATX_SEL2

2213S-04G-F2

13 4

2

R699 15K_1%R699 15K_1%

R704 1KR704 1K

Q51APM4317KC-TRG

Q51APM4317KC-TRG

4

6172

3 8

5

C4280.015uFC4280.015uF

JP_AT/ATX_SEL3(1-2)

MINI-JUMPER

JP_AT/ATX_SEL3(1-2)

MINI-JUMPER

Q542N7002Q542N7002

GD

S

TP_+3V3TP_+3V3

1

JP_ATX_SEL1(1-2)

2228BG-RD-F1/X

JP_ATX_SEL1(1-2)

2228BG-RD-F1/X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+3.3V

+3.3V

AGND

+3.3V

+12V_VCC

AGND

Title


Date: Sheet of


COMEDB4

Mounting Holes


AC

Title


Date: Sheet of


COMEDB4

Mounting Holes


AC

Title


Date: Sheet of


COMEDB4

Mounting Holes


AC

VIA Confidential

For EMI

FOR COM EXPRESS MODULE

FIDUCIAL MARK

FOR Mini-PCIE MODULE

MH2MTH4mm

MH2MTH4mm

1234 5

678

9

C64 0.1uFC64 0.1uF

MH11MTH4mm

MH11MTH4mm

1234 5

678

9

C18 0.1uFC18 0.1uF

MH18MTH4mm

MH18MTH4mm

1234 5

678

9

MH16MTH4mm

MH16MTH4mm

1234 5

678

9

6mm

2.7mm

MH6

MH6_2.7

6mm

2.7mm

MH6

MH6_2.71

C109 0.1uFC109 0.1uF

MH12

N0204525A-B

MH12

N0204525A-B1

C111 0.1uFC111 0.1uF

FID3

FIDUCIAL

FID3

FIDUCIAL

1

MH15

N0204525A-B

MH15

N0204525A-B1C142 0.1uFC142 0.1uF

6mm

2.7mm

MH19

MH6_2.7

6mm

2.7mm

MH19

MH6_2.71

MH9MTH4mm

MH9MTH4mm

1234 5

678

9

C113 0.1uFC113 0.1uF

MH3MTH4mm

MH3MTH4mm

1234 5

678

9

C187 0.1uFC187 0.1uF

6mm

2.7mm

MH4

MH6_2.7

6mm

2.7mm

MH4

MH6_2.71

C206 0.1uFC206 0.1uF

6mm

2.7mm

MH7

MH6_2.7

6mm

2.7mm

MH7

MH6_2.71

MH17MTH4mm

MH17MTH4mm

1234 5

678

9

FID2

FIDUCIAL

FID2

FIDUCIAL

1

MH13

N0204525A-B

MH13

N0204525A-B1

C43 0.1uFC43 0.1uF

C317 0.1uFC317 0.1uF

C121 0.1uFC121 0.1uF

C145 0.1uFC145 0.1uF

6mm

2.7mm

MH5

MH6_2.7

6mm

2.7mm

MH5

MH6_2.71

C116 0.1uFC116 0.1uF

6mm

2.7mm

MH8

MH6_2.7

6mm

2.7mm

MH8

MH6_2.71

MH10MTH4mm

MH10MTH4mm

1234 5

678

9

MH14

N0204525A-B

MH14

N0204525A-B1

MH1MTH4mm

MH1MTH4mm

1234 5

678

9

FID1

FIDUCIAL

FID1

FIDUCIAL

1

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


COMEBD2

Block Diagram

1 29Wednesday, July 31, 2013

AC

Title


Date: Sheet of


COMEBD2

Block Diagram


AC

Title


Date: Sheet of


COMEBD2

Block Diagram


AC


ROW A-B ROW C-D

LPC BIOS

LPC BUS

LPC SIO

BIOS_DIS0#

HDA LINK

HD Codec

VT1211

VT2021

SATA

2 X SATA

4 X USB 2.0USB 2.0

1 X PCIE X 1PCIE

LVDSLVDS

USB 3.0

DDI2

HDMI

PCIE X 16PCIE X 4

VIA Confidential

SPI BIOSSPI BUS

BIOS_DIS1#

4 X USB 3.0

2 X Serial2 x Serial Interface Signals

DVP Port

DVP SLOT

DDI3

Display Port

GbE LANLAN

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWRBTN#

PWR_OK [4,27]

SUS_S3#, SUS_S4#, SUS_S5#

WAKE1#

SYS_RESET#

CB_RESET#

GPOn (4)

GPIn (4)

Title


Date: Sheet of


COMEBD2



AC

Title


Date: Sheet of


COMEBD2



AC

Title


Date: Sheet of


COMEBD2



AC

COME8X90COM-e Type 6 Module

VGA connector

LVDS connectorLVDS

HDA CODECVT2021

HDA

SPKR

X-FormerEthernet

Ethernet Port Eth Ctrlr & PhyVT6130

SEEPROM

USB 2.0 (4)

USB2_0/1 pin header

USB2_2/3 pin header

Mini-PCI-e socket

PCI-e SwitchPEX8604

PCI-e x1

PCI-e x1 Slot

PCI-e x1 Slot

PCI-e x1

PCI-e x1

SATA (2)

DDI2HDMI connector

PCI-e x4

SMBUS

I2C Bus

DVP

DDI3DP connector

PCI-e X16 Slot

SMBUS pin header

I2C Bus pin header

DVP Slot

FLASH BIOS

PCI-e x1

PCI-e x1

USB3_LAN connector

FLASH BIOS

SPI BusLP

C B

us

Super I/O

VT1211

Serial Ports (2)COM 1 connector

COM 2 pin header

LPT pin headerParallel Port

DIO2 pin headerGPIO (8)

UIC+12V, +5V, +3.3V, +5VSUS, +1.0VVoltage Sense

Serial 1 & 2General Purpose Serial Ports (2)

TX1/2, RX1/2

FLASH BIOS

FIRFIR pin header

VIA Confidential

DP1

DP2

USB3_0/1 Port

USB 3.0 HostVL800

PCI-e x1

USB3_2/3 connector

USB 3.0 (4)

Audio connector

GPIO/SDIO (8)

DIO1 pin header

SATA1 connector

SATA2 connector

Hardware MonitorF75308AR

USB2_Port 4 & 5

USB2_Port 6

USB2_Port 6 & 7

Rear I/O:

Rear I/O:

Rear I/O:

Rear I/O:

Rear I/O:

Rear I/O:

Rear I/O:

SDIO

SDIO connector DP RepeaterSN75DP120

HDMI RedriverTMDS141

SPI

LPC

PE1

PE2

PE16

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


COMEBD2

COVER SHEET


AC

Title


Date: Sheet of


COMEBD2

COVER SHEET


AC

Title


Date: Sheet of


COMEBD2

COVER SHEET


AC



Revision A

COMEDB2

TITLE

LVDS

7

ATX Power, VCCRTC

16

8

2

9

18


15

SHEET

HDMI ReDriver_TMDS141

25

DP ReDriver SN75DP120

LPC SIO VT1211

26

Block Diagram

HD Codec VT2021 / F_Audio

SATA, VGA, RESET

17

1

COM1, COM2

10

14

3

11

20

27

Cover Sheet

12

214

Printer Port, BIOS, LPC

5

USB 2.0_4 Ports

19

22

6

TITLE SHEET

13

24

CPU & System FAN

PEX 8604 Strapping

PCI-e X16 Slot

FPNL, DIO, SDIO

DVP Slot

VIA Confidential



USB 3.0_4 Ports

LPC Debug Port, LED

PEX 8604_PCI-e Switch

PCI-e X1 Slot & Mini-PCI-e

23

RJ45 & LAN LED

Audio Connectors

MOUNTING HOLES 29

System Power 28


A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CEM_5VSB

SER0_TX_SER0_RX_

SER1_TX_SER1_RX_

FAN_PWMOUT_FAN_TACHIN_

RSVD_A86RSVD_A87

RSVD_B98RSVD_B99

SER0_RX_

SER1_RX_ FAN_TACHIN_

SER0_TX_

SER1_TX_

FAN_PWMOUT_

MDI0+[18]MDI0-[18]

MDI1+[18]MDI1-[18]

LAN_-SP100[18]



-SUSC[15]

-SATA_LED[15]AZ_SYNC[6,10]-AZ_RST[6]

AZ_BITCLK[6,10]AZ_SDOUT[6]

COM_GPI0[15]

LPC_SERIRQ[8,10]

-PE_RST0[24,25]

USB2_DT0+[17]USB2_DT0-[17]-USB2_OC2_3[17]

USB2_DT2-[17]USB2_DT2+[17]


-USB_OC6_7[16]

USB_DT6-[16,24]USB_DT6+[16,24]

COM_GPO2 [15]

COM_GPO1 [15]

-SYS_RESET [15]

-PE_RST1 [23,24]

USB2_DT1- [17]USB2_DT1+ [17]

-USB2_OC0_1 [17]USB2_DT3+ [17]USB2_DT3- [17]

USB_DT5+ [16]USB_DT5- [16]-USB_OC4_5 [16]

USB_DT7- [16]USB_DT7+ [16]

SPKR [6,21]

AZ_SDIN0 [6]




-PW_BTN [15]SMB_CLK [12,15,24,25]SMB_DAT [12,15,24,25]

COM_GPI1[15]

COM_GPI2[15]PCIE_TX0+[22]PCIE_TX0-[22]


LVDS_A_CK+[14]LVDS_A_CK-[14]LVDS_I2C_CK[14]LVDS_I2C_DAT[14]COM_GPI3[15]


COM_GPO0[15]

PCIE_RX0- [22]

VGA_HSYNC [13]

CRT_SPD [13]

LVDS_B3+ [14]

LVDS_B_CK- [14]

VGA_R [13]

LVDS_B2- [14]

LVDS_B0+ [14]

LVDS_B1+ [14]

VGA_G [13]

COM_GPO3 [15]

PCIE_RX0+ [22]

CRT_SPCLK [13]

LVDS_B_CK+ [14]

LVDS_BKLT_EN [14]

LVDS_B0- [14]

LVDS_B2+ [14]

VGA_B [13]

VGA_VSYNC [13]

LVDS_B3- [14]

LVDS_B1- [14]

PWR_OK [27]

LPC_33_CLK [12]

I2C_DAT [11,15]I2C_CLK [11,15]

SATA_GND[13]

MDI3-[18]MDI3+[18]

LAN_-SP1000[18]MDI2-[18]MDI2+[18]

LAN_-ACT [18]

-CB_RESET [13]

-PE_WAKE [24,25]-WAKE1 [8]

BLT_CK [5,14,26]

-WDT_OUT [15]

VDDTXRX_LAN[18]



-SPI_SS0 [10]

-BIOS_DIS0[10]

-BIOS_DIS1 [10]

SDPOFF[15]

-SUSA[15]

SER0_RX[9]

SER1_RX[9] FAN_TACHIN[11]

SER0_TX[9]

SER1_TX[9]

FAN_PWMOUT[11]

+3.3VBAT

+5VSUS

+12V +12V

+3.3V

+3.3V

+3.3V

Title


Date: Sheet of


COMEDB2

COME_CONN(A-B)


AC

Title


Date: Sheet of


COMEDB2

COME_CONN(A-B)


AC

Title


Date: Sheet of


COMEDB2

COME_CONN(A-B)


AC

VIA Confidential


A4

A9A10

A12A13

A15A16A17

A19A20

A24

A28A29A30

A32A33A34

A36A37A38A39A40

A42A43A44A45A46

A48

A50

A54

B3B4B5B6B7B8B9B10

B12B13B14

B16B17

B19B20

B24

B27

B30

B32B33B34

B36B37B38B39B40

B42B43B44B45B46B47

B49

B54

B57

A63

A67A68A69

A71A72A73A74A75A76A77A78A79

A81A82A83A84A85

A88A89

A93

B63

B66

B68B69

B71B72B73B74B75B76B77B78B79

B81B82

B89

B91B92B93B94B95B96

B2A2A3

A5A6A7

B50

B67

B83

A14

A91A92

A94A95

B97

B88

B102B101

A102A101

A99A98

A18

Pin Protection Reclaim from VCC_12V Circuit

Q402N7002/XQ402N7002/X G

DS

R557 0R557 0

R5484.7K/XR5484.7K/X

Q392N7002/XQ392N7002/XG

DS

R176 0/0805R176 0/0805

R5474.7K/XR5474.7K/X

R618 0R618 0

Q412N7002/XQ412N7002/X G

DS

CON1A3-6318491-6CON1A3-6318491-6

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313 14 14

1515 16 16

1717 18 18

1919 20 20

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535 36 36

3737 38 38

3939 40 40

4141 42 42

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757 58 58

5959 60 60

6161 62 62

6363 64 64

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979 80 80

8181 82 82

8383 84 84

8585 86 86

8787 88 88

8989 90 90

9191 92 92

9393 94 94

9595 96 96

9797 98 98

9999 100 100

101101 102 102

103103 104 104

105105 106 106

107107 108 108

109109 110 110

111111 112 112

113113 114 114

115115 116 116

117117 118 118

119119 120 120

M1

G1

R5614.7K/XR5614.7K/X

R5500R5500

Q372N7002/XQ372N7002/XG

DS

Q382N7002/XQ382N7002/XG

DS

FB4 AA-600Y03102FB4 AA-600Y03102

R5490R5490

R304 0R304 0

R551 0R551 0

R5600R5600

R5544.7K/XR5544.7K/X

R558 1K/XR558 1K/X

R617 0R617 0

R5534.7K/XR5534.7K/X

R559 1K/XR559 1K/X R552 1K/XR552 1K/X

R5554.7K/XR5554.7K/X

Q422N7002/XQ422N7002/X G

DS

CON1B3-6318491-6CON1B3-6318491-6

121121 122 122

123123 124 124

125125 126 126

127127 128 128

129129 130 130

131131 132 132

133133 134 134

135135 136 136

137137 138 138

139139 140 140

141141 142 142

143143 144 144

145145 146 146

147147 148 148

149149 150 150

151151 152 152

153153 154 154

155155 156 156

157157 158 158

159159 160 160

161161 162 162

163163 164 164

165165 166 166

167167 168 168

169169 170 170

171171 172 172

173173 174 174

175175 176 176

177177 178 178

179179 180 180

181181 182 182

183183 184 184

185185 186 186

187187 188 188

189189 190 190

191191 192 192

193193 194 194

195195 196 196

197197 198 198

199199 200 200

201201 202 202

203203 204 204

205205 206 206

207207 208 208

209209 210 210

211211 212 212

213213 214 214

215215 216 216

217217 218 218

219219 220 220

G2

M2

R556 0R556 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RSVD_C17RSVD_C18

RSVD_D17RSVD_D18

RSVD_C27RSVD_C28

RSVD_D25RSVD_D24

RSVD_D28

RSVD_C35 RSVD_D35

RSVD_D38

RSVD_C45

RSVD_C48

RSVD_D45

RSVD_D48

RSVD_C63RSVD_C64

RSVD_C83

RSVD_C97 RSVD_D97

RSVD_D83

RSVD_D63RSVD_D64

-PEG_LANE_RV

RSVD_C63

RSVD_D63

DDC_AUX_SEL-TYPE0

-TYPE1

-PEG_LANE_RV

-TYPE2

USB3_SSRX3+[17]

PEG_RX0+[25]PEG_RX0-[25]

PEG_RX1-[25]PEG_RX1+[25]

PEG_RX2-[25]PEG_RX2+[25] PEG_TX2+ [25]

PEG_TX2- [25]

PEG_TX1- [25]PEG_TX1+ [25]

PEG_TX0- [25]PEG_TX0+ [25]


PEG_TX3- [25]

DVP1_D3 [26]DVP1_D1 [26]

DVP1_D7 [26]DVP1_D5 [26]

DVP1_D11 [26]DVP1_D9 [26]

DVP1_D15 [26]DVP1_D13 [26]

DVP1_CLK [26]

DVP1_BKLT_EN [26]DVP1_VDD_EN [26]

BLT_CK [4,14,26]

DVP1_D0[26]DVP1_D2[26]

DVP1_D4[26]DVP1_D6[26]

DVP1_D8[26]DVP1_D10[26]

DVP1_D12[26]DVP1_D14[26]

DVP1_DE[26]DVP1_VS[26]

DVP1_HS[26]DVP1_TVFLD[26]

DVP1_SPD[26]DVP1_SPCLK[26]

DVP1_TVCLKR [26]

-TYPE2 [27]

-TYPE0[27]

-TYPE1[27]

DDI_CTRLCLK[19]DDI_CTRLDATA[19]





USB3_SSRX3-[17]




DP2_TX0+ [19]DP2_TX0- [19]

DP2_TX1+ [19]DP2_TX1- [19]-DP2_HPD [19]

DP2_TX2+ [19]DP2_TX2- [19]

DP2_TX3+ [19]DP2_TX3- [19]

DP3_LANE0+[20]

DP3_AUX+[20]DP3_AUX-[20]

DP3_LANE0-[20]




-DP3_HPD[20]

VCP_DET[26]

DDC_AUX_SEL

+12V +12V

+3.3V

Title


Date: Sheet of


COMBED2

COME_CONN (C-D)


AC

Title


Date: Sheet of


COMBED2

COME_CONN (C-D)


AC

Title


Date: Sheet of


COMBED2

COME_CONN (C-D)


AC


C3C4

C6C7

C9C10

C12C13

C52C53

C55C56

C58C59

D3D4

D6D7

D9D10

D12D13

D39D40

D42D43D44

D46D47

D50

D52D53

D55D56

D58D59

C61C62

C78C79

C81C82

C85C86

C88C89

C91C92

C94C95

C98C99

D61D62

D78D79

D81D82

D85D86

D88D89

D91

D94

D98D99

D101

D57

C54

C57

VIA Confidential

C32C33

D49C49

C39C40

C42C43C44

C46C47

C50

C36C37

C101

C34

DDI Configuration:

DDI 1: NADDI 2: HDMI / DISPLAY PORTDDI 3: DISPLAY PORT

Note: Reserved for PCIe SI Measurement

R610 0/XR610 0/X

R616 4.7KR616 4.7KR612 0/XR612 0/X

CON2B3-6318491-6CON2B3-6318491-6

121121 122 122

123123 124 124

125125 126 126

127127 128 128

129129 130 130

131131 132 132

133133 134 134

135135 136 136

137137 138 138

139139 140 140

141141 142 142

143143 144 144

145145 146 146

147147 148 148

149149 150 150

151151 152 152

153153 154 154

155155 156 156

157157 158 158

159159 160 160

161161 162 162

163163 164 164

165165 166 166

167167 168 168

169169 170 170

171171 172 172

173173 174 174

175175 176 176

177177 178 178

179179 180 180

181181 182 182

183183 184 184

185185 186 186

187187 188 188

189189 190 190

191191 192 192

193193 194 194

195195 196 196

197197 198 198

199199 200 200

201201 202 202

203203 204 204

205205 206 206

207207 208 208

209209 210 210

211211 212 212

213213 214 214

215215 216 216

217217 218 218

219219 220 220

G2

M2

CON2A3-6318491-6CON2A3-6318491-6

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313 14 14

1515 16 16

1717 18 18

1919 20 20

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535 36 36

3737 38 38

3939 40 40

4141 42 42

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757 58 58

5959 60 60

6161 62 62

6363 64 64

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979 80 80

8181 82 82

8383 84 84

8585 86 86

8787 88 88

8989 90 90

9191 92 92

9393 94 94

9595 96 96

9797 98 98

9999 100 100

101101 102 102

103103 104 104

105105 106 106

107107 108 108

109109 110 110

111111 112 112

113113 114 114

115115 116 116

117117 118 118

119119 120 120

M1

G1

R611 0/XR611 0/X

R163 0R163 0

R614 0/XR614 0/X

R613 0/XR613 0/X

R615 0/XR615 0/X

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

LINE-R

CD_R

SD_IN0

MIC2_FR_L

AFILT4

MIC2_FR_R

MIC1_LMIC1_R

LINE-L

JD2

CD_L

MIC2_FRR

BIT_CLK

FNT_IO_SENSE

PC_BEEP

MIC2_FRL


MIC2_VREFO

JDREFVCAP

U19_45U19_46

U19_43U19_44

U19_41U19_39

U19_35U19_36

MIC2_JD

LINE2_JD

LINE2_RLINE2_L

HP_OUT_R

FNT_DET

HP_OUT_L

JD1

PC_BEEP

MIC2_FR_LMIC2_FR_R

FNT_IO_SENSE

MIC2_VREFO

LINE2_VREFO

HP_OUT_L

HP_OUT_R

AUDIO_VREF

AUDIO_VREF

JDREF

VREFOUT-C_L

VCAP

MIC2_JD

LINE2_JD

LINE2_VREFO

LINE1_IN_R[7]

AZ_SDOUT[4]

LINE1_IN_L[7]

AZ_SDIN0[4]

AZ_BITCLK[4,10]-AZ_RST[4]

AZ_SYNC[4,10]

MIC1_VREFO_L [7]


SIDESURR_JD[7]CEN_JD[7]

FRONT_JD[7]LINE1_JD[7]MIC1_JD[7]SURR_JD[7]

SIDESURR_OUT_L [7]SIDESURR_OUT_R [7]




SPKR[4,21]


CD_IN_R[7]

MIC1_VREFO_R [7]

SPDIFO [7]

DVP_SPDIF_HDMI [26]

+3.3VSUS

+3.3V

VDD3_AUDIO

AGND

+5VSUS

AGND AGNDAGND

+12V_VCC+5VAUDIO

AGND

AVDD5 +5VAUDIO

VDD3_AUDIO

AGND

AGND

+12V_VCC

AGND

+5VAUDIO

AGND

+12V_VCC

AGND

AGND

AGND

AGND

AGND

AGND

AGND

+5VDUAL

AGND

Title


Date: Sheet of


COMEDB2

HD Audio VT2021


AC

Title


Date: Sheet of


COMEDB2

HD Audio VT2021


AC

Title


Date: Sheet of


COMEDB2

HD Audio VT2021


AC

FRONT AUDIO

HD Audio Codec

+5VAUDIO

Close to VT1708S

VIA Confidential

connect standby power(for pop noise)

R258 for RealTek codec Jack detect.

R238 33R238 33

C2240.1uFC2240.1uF

R198 0 /XR198 0 /X

+CE15 10uF+CE15 10uF12

+CE17 10uF+CE17 10uF12

R212 39.2K_1%R212 39.2K_1%

R245 0R245 0

FB37QT1608RL300LF

FB37QT1608RL300LF U20

VT2021

U20

VT2021

DVDD11

SENSEA13 SPDIF_TX1 2

DVSS14

SDATA_OUT5

BIT_CLK6

DVSS27

SDATA_IN8

DVDD29

SYNC10

RESET11

PC_BEEP12

SENSEB34

PORT-E/Fr.HP-L14

PORT-E/Fr.HP-R15

PORT-F/Fr.MIC1-L16

PORT-F/Fr.MIC2-R17

CD_L18

CD_GND19

CD_R20

PORT-B/MIC1-L21

PORT-B/MIC2-R22

PORT-C/LINE IN-L23

PORT-C/LINE IN-R24

AVDD1 25

AVSS1 26

NC 37VREFOUT-E 31

CAP 33

GPIO 3

VREFOUT-C 29

VREFOUT-F_L 30

VREFOUT-B_L 28

VREFOUT-B_R 32

FRONT-OUT-L/PORT-D 35

FRONT-OUT-R/PORT-D 36

VREF 27

AVDD2 38

SURR-OUT-L/PORT-A 39

SURR-OUT-R/PORT-A 41

JDREF 40

AVSS2 42

CEN-OUT/PORT-G 43LEE-OUT/PORT-G 44

SIDESURR-OUT-R/PORT-H 46SIDESURR-OUT-L/PORT-H 45

S/PDIF_RX0/EAPD 47

S/PDIF_Tx0 48

+CE30 10uF+CE30 10uF1 2

+CE34 10uF+CE34 10uF1 2

+CE37 10uF+CE37 10uF1 2

C2360.1uFC2360.1uF

C220100pFC220100pF

+

CE2210uF

+

CE2210uF

12

R195 20K_1%R195 20K_1%

+

CE2910uF

+

CE2910uF

12

C216 1uFC216 1uF

R239 22R239 22

U19AMS1117-5.0U19AMS1117-5.0

V_INI

GN

DG

V_OUT O

R258 20K_1%/XR258 20K_1%/X

R196 3.3KR196 3.3K

C241 100pFC241 100pF

C239 10uF/XC239 10uF/X

R193 3.3KR193 3.3K

R244 33R244 33

R210 33R210 33

+CE13 10uF+CE13 10uF12

R21910KR21910KR218

10KR21810K

+CE19 220uF+CE19 220uF12

C2090.1uFC2090.1uF

R216 33R216 33

R211 20K_1%R211 20K_1%



13 4

2

5 67

14

9 1011 1213



R191 16R191 16

R205 10K_1%R205 10K_1%

C234 0.1uFC234 0.1uF


C2220.1uFC2220.1uF

C214 2.2uFC214 2.2uF

+CE31 10uF+CE31 10uF1 2

+

CE3210uF

+

CE3210uF

12

R2171KR2171K

C2080.1uFC2080.1uF

R233 22R233 22

+CE23 10uF+CE23 10uF1 2

C2150.1uFC2150.1uF

R257 5.1K_1%R257 5.1K_1%

R190 16R190 16

R223 33R223 33

R199 39.2K_1%R199 39.2K_1%

FB23 0FB23 0

C2130.1uFC2130.1uF

R197 3.3KR197 3.3K

FB41 0FB41 0

R194 3.3KR194 3.3K

C217 1uFC217 1uF

+CE14 10uF+CE14 10uF12

R214 10K_1%R214 10K_1%

R228 33R228 33

R209 33R209 33

R21510KR21510K

+CE20 220uF+CE20 220uF12

FB21 0FB21 0

R204 5.1K_1%R204 5.1K_1%

C204 0.1uFC204 0.1uF

R189 16R189 16

TP_+5VAUDIOTP_+5VAUDIO

1

FB24QT1608RL300LF

FB24QT1608RL300LF

+CE25 10uF+CE25 10uF1 2


R220 10KR220 10K

+

CE3610uF

+

CE3610uF

12

FB42 0FB42 0

+CE27 10uF+CE27 10uF1 2

+CE28 10uF+CE28 10uF1 2

C229 22pFC229 22pF

+

CE2610uF

+

CE2610uF

12

C218 100pFC218 100pF

C219 1uFC219 1uF

+CE35 10uF+CE35 10uF1 2

+

CE2110uF

+

CE2110uF

12

FB33 EBMS321611A520FB33 EBMS321611A520

C244 100pFC244 100pF

C203 0.1uFC203 0.1uF

+CE18 10uF+CE18 10uF12

R188 16R188 16

+CE16 10uF+CE16 10uF12

D33

SSM5817PT/X

D33

SSM5817PT/X

A K

FB260FB260

C227 0.1uFC227 0.1uF

C233 10pFC233 10pF

D32

BAT54A

D32

BAT54A

1

23

R213 5.1K_1%R213 5.1K_1%

R249 33R249 33

D31

BAT54A

D31

BAT54A

1

23

C2420.1uFC2420.1uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

MIC1_RE_L [6]

MIC1_RE_R [6]

MIC1_VREFO_R [6]

FRONT_OUT_L [6]

FRONT_OUT_R [6]

MIC1_JD [6]

FRONT_JD [6]

LINE1_JD [6]

LINE1_IN_L [6]

LINE1_IN_R [6]LFE_OUT [6]

CEN_OUT [6]

SURR_OUT_R [6]

SURR_OUT_L [6]

SIDESURR_OUT_R [6]

SIDESURR_OUT_L [6]

SIDESURR_JD [6]

SURR_JD [6]

CEN_JD [6]

CD_IN_R [6]


MIC1_VREFO_L [6]

SPDIFO [6]

AGND

AGND

AGND

AGND

AGND

AGND

AGND

+5V

Title


Date: Sheet of


COMEDB2

AUDIO CONNECTORS


AC

Title


Date: Sheet of


COMEDB2

AUDIO CONNECTORS


AC

Title


Date: Sheet of


COMEDB2

AUDIO CONNECTORS


AC

MIC_IN

LINE1_IN

FRONT_OUT

CD_IN

SIDESURR_OUT

SURR_OUT

CENTER/LFE

GREY

BLACK

ORANGE

GREEN

PINK

BLUE

VIA Confidential


AUDIO_JACK2B

ZJ388S-13B-SH

AUDIO_JACK2B

ZJ388S-13B-SH

242Q2P21

G3

G4

C228100pFC228100pF

R202 330R202 330

AUDIO_JACK2A

ZJ388S-13B-SH

AUDIO_JACK2A

ZJ388S-13B-SH

141Q1P115

G1

G2

C235100pFC235100pF

R203 3.3KR203 3.3K

AUDIO_JACK1B

ZJ388S-13B-PH

AUDIO_JACK1B

ZJ388S-13B-PH

242Q2P21

G3

G4

C232100pFC232100pF

C210100pFC210100pF

C240100pFC240100pF

C205100pFC205100pF

C207100pFC207100pF


C202100pFC202100pF

C243 0.1uFC243 0.1uF




R206100KR206100K


C221100pFC221100pF


R207100KR207100K

C212100pFC212100pF

C226100pFC226100pF

R2534.7KR2534.7K


R208100KR208100K

C211100pFC211100pF


CD_IN

209-90-04GB20

CD_IN

209-90-04GB20

1234

AUDIO_JACK1A

ZJ388S-13B-PH

AUDIO_JACK1A

ZJ388S-13B-PH

141Q1P115

G1

G2



SPDIF

209-90-03GB20

SPDIF

209-90-03GB20

123

R200 330R200 330

AUDIO_JACK1C

ZJ388S-13B-PH

AUDIO_JACK1C

ZJ388S-13B-PH

343Q3P31


R201 330R201 330

AUDIO_JACK2C

ZJ388S-13B-SH

AUDIO_JACK2C

ZJ388S-13B-SH

343Q3P31


R192 3.3KR192 3.3K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FANPWM2

FANIO2

HWMGND

+3.3V_IN

HWMVCC

+12V_IN

SIO_48M_CLK

SIRQ

HWMVCC

SIO_-DTR1

SIO_-RTS1

SIO_TXD1

+1.0V_IN

+12V_IN

HWMGND

+3.3V_IN+1.0V_IN

+5V_IN

+5V_IN+5VSUS_IN +5VSUS_IN

IRRX

HWMGND

48_CLK

IRTX

IRRXIRRX1

DTDNDTDP

SIO_48M_CLK

-PME

DTDP

DTDN

IRTX

-PME

IRRX1

SIO_33_CLK[12]

-LPC_FRAME[4,10,21]

LPC_AD2[4,10,21]LPC_AD3[4,10,21]

LPC_AD1[4,10,21]LPC_AD0[4,10,21]

-LPC_DRQ0[4]

-SIO_RESET[13]

FANPWM1[11]

FANIO1[11]

LPC_SERIRQ[4,10]

SIO_GPO32 [15]

SIO_GPO30 [15]

SIO_GPO33 [15]

SIO_GPO31 [15]

SIO_GPI35 [15]SIO_GPI36 [15]

SIO_GPI34 [15]

SIO_GPI37 [15]

LP_D3[10]LP_D2[10]LP_D1[10]LP_D0[10]

LP_D7[10]LP_D6[10]LP_D5[10]

LP_D4[10]

LP_PE[10]LP_BUSY[10]

-LP_ACK[10]-LP_ERR[10]-LP_SLIN[10]

-LP_INIT[10]-LP_AFD[10]

-LP_STB[10]

SIO_-RI1[9]

SIO_-CTS1[9]

SIO_-DTR1[9]SIO_-RTS1[9]SIO_-DSR1[9]

SIO_TXD1[9]SIO_RXD1[9]

SIO_-DCD1[9]

SIO_-DCD2 [9]SIO_-RI2 [9]

SIO_-CTS2 [9]

SIO_-DTR2 [9]SIO_-RTS2 [9]SIO_-DSR2 [9]

SIO_TXD2 [9]

SIO_RXD2 [9]

LP_SLCT[10]

-PLED [15]

-RF_ON [16]

-WAKE1 [4]-W_DISABLE[24]

+3.3V

+3.3V

+3.3V+1.0V +5V +12V_VCC

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO

+3.3VSIO

+5VSUS

+3.3V

+5V

+3.3VSIO

Title


Date: Sheet of


COMEDB2

VT1211 COM3/ COM4/ LPT/ HW monitor


AC

Title


Date: Sheet of


COMEDB2



AC

Title


Date: Sheet of


COMEDB2



AC

VIA Confidential

VT1211

VT1211 Decoupling Caps.

0: Enable ROM I/F as GPIO

0:Normal Opreation

1:Enable Flash Rom

1:Test Mode

HWM_AVCC/ HWM_AGND= 12 mils

(2E)

Voltage Sense

FIRThermal Sensor

R95 0R95 0

C960.1uFC960.1uF

U11

VT1211

U11

VT1211

DSEL0#1

INDEX#2

MTRA#3

DRVB#4

VCC5

DRVA#6

MTRB#7

DIR#8

STEP#9

WDATA#10

WGATE#11

TRCAK0#12

WPT#13

RDATA#14

HEAD#15

DSKCHG#16

CLKIN17

GND18

PCICLK19

LDRQ#20

SERIRQ21

VCC22

LAD323

LAD224

LAD125

LAD026

LFRAME#27

LRESET#28

SLCT29

PE30

BUSY31

ACK#32

ERR#33

SLIN#34

PD735

PD636

PD537

PD438

PD

339

PD

240

PD

141

PD

042

INIT

#43

AF

D#

44

VC

C45

ST

B#

46

CT

S1#

47

DS

R1#

48

RT

S1#

49

DT

R1#

50

SIN

151

SO

UT

152

DC

D1#

53

RL1

#54

GP

77/V

ID4/

CT

S2#

55

GP

76/V

ID3/

DS

R2#

56

GP

75/V

ID2/

RT

S2#

57

GP

74/V

ID1/

DT

R2#

58

GP

73/V

ID0/

SIN

259

GN

DD

60

GP

72/S

MB

CK

/SO

UT

261

GP

71/S

MB

DT

/DC

D2#

62

GP

70/R

I2#/

ITM

ON

_OF

F63

IRR

X64

IRTX 65XA18/GP62 66XA17/GP61 67XA16/GP60 68XA15/GP57 69XA14/GP56 70XA13/GP55 71XA12/GP54 72XA11/GP53 73XA10/GP52 74

VCC 75XA9/GP51 76XA8/GP50 77XA7/GP47 78XA6/GP46 79XA5/GP45 80XA4/GP44 81XA3/GP43 82XA2/GP42 83XA1/GP41 84XA0/GP40 85XD7/GP37 86XD6/GP36 87XD5/GP35 88XD4/GP34 89

GNDD 90XD3/GP33 91XD2/GP32 92XD1/GP31 93XD0/GP30 94

ROMCS#/GP27 95MEMR#/GP26 96

MEMW#/GP25 97SMI#//PME# 98GNDD//VSB 99

IRRX/GP24//CIRRX 100COPEN/OVER_FAN/GP23/ATEST 101

PLED/ITMOFF/GP22/OVER_VOLT//VBAT 102

UIC

110

3U

IC2

104

VC

CA

105

VR

EF

106

UIC

310

7U

IC4

108

UIC

510

9D

TD

N11

0D

TD

P11

1G

ND

A11

2F

AN

IO2

113

FA

NIO

1/D

TE

ST

114

FA

NO

UT

2/G

P21

115

FA

NO

UT

1/G

P20

116

OV

TE

MP

#/S

MI#

(W)

117

BE

EP

118

MS

I/O

VE

R_F

AN

(GP

51)/

WD

TO

119

MS

O/O

VE

R_V

OLT

(PLE

D)/

DS

EL1

(GP

50)

120

JAB

2/G

P17

121

JBB

2/G

P16

122

JAC

Y/G

P15

123

JBC

Y/P

16/G

P14

124

JBC

X/P

15/G

P13

125

JAC

X/P

14/G

P12

126

JBB

1/P

13/G

P11

127

JAB

1/P

12/G

P10

128


R8715K_1%R8715K_1%

FIR

2211S-05G-F2

FIR

2211S-05G-F2

12345

C5310uFC5310uF

OSC1

48MHz

OSC1

48MHz

Tri-State1

GND2 OUT 3

VDD 4

R48 10KR48 10K

R374.7KR374.7K

R9310K_1%R9310K_1%

C941uFC941uF

SYS_SENSYS_SEN

21

3

R8110K_1%R8110K_1%

C5210uFC5210uF

FB7QT1608RL300

FB7QT1608RL300

R36 0R36 0

R94 4.7KR94 4.7K

C930.1uFC930.1uF

R9810K_1%R9810K_1%

R38 22R38 22

C892200pFC892200pF

R7847K_1%R7847K_1%

R49 2.2K/XR49 2.2K/X

R7910K_1%R7910K_1%


C560.1uFC560.1uF

CN5470pFCN5470pF

12

34

56

78

R82 4.7K/XR82 4.7K/X

C580.1uFC580.1uF

R63 1KR63 1K

R806.8K_1%R806.8K_1%

TP_FANPWM2TP_FANPWM2 1

R53 10K/XR53 10K/X

R9215K_1%R9215K_1%

TP_FANIO2TP_FANIO2 1

C750.1uFC750.1uF

R54 1KR54 1K

R8610K_1%R8610K_1%


Q11MMBT3904/XQ11MMBT3904/X

B

EC

R62 10K/XR62 10K/X

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

COM_DCD1

COM_RI1

COM_RTS1

COM_DTR1

COM_DSR1COM_DCD1

COM_CTS1COM_TXD1

COM_RXD1

COM_TXD2

COM_CTS2COM_DSR2


COM_RI2COM_RTS2COM_TXD2

-XRI2

COM_DSR2

COM_DTR2

COM_RXD2

COM_DCD2

COM_RTS2

COM_CTS2

COM_CTS1

COM_RTS1

COM_DTR1

COM_TXD1

COM_RXD1COM_DSR1

-XRI1

SER0_RX_CON

SER0_TX_CON

SER1_RX_CON

SER1_TX_CON

-XRI2

COM_RI2

-XRI1

COM_RI1

SER1_RX_CON


SER1_TX_CON

SIO_-DSR1[8]SIO_RXD1[8]SIO_-RTS1[8]SIO_TXD1[8]

SIO_-DCD1[8]

SIO_-CTS1[8]SIO_-DTR1[8]SIO_-RI1[8]

SIO_TXD2[8]

SIO_-DCD2[8]

SIO_-RI2[8]

SIO_RXD2[8]

SIO_-CTS2[8]

SIO_-RTS2[8]

SIO_-DTR2[8]

SIO_-DSR2[8]

SER1_TX[4]SER0_TX[4]

SER1_RX[4]SER0_RX[4]

-12V

+5V +12V_VCC

+12V_VCC+5V

-12V

+5V +5V

+5V +12V_VCC

+5V +12V_VCC

Title


Date: Sheet of


COMEBD2

COM1,COM2


AC

Title


Date: Sheet of


COMEBD2

COM1,COM2


AC

Title


Date: Sheet of


COMEBD2

COM1,COM2


AC

COM 1

COM 2

VIA Confidential

General Purpose

Serial Ports

JP_COM2_VSEL

1-2

2-3

+5V

+12V

VOLTAGE

JP_COM1_VSEL

1-2

2-3

+5V

+12V

VOLTAGE

Normal *

3-4

Normal *

3-4

JP_COM2_VSEL

2211S-04G-BK-F2

JP_COM2_VSEL

2211S-04G-BK-F2

1

34

2

C3370.1uFC3370.1uF

CN

4A22

0pF

CN

4A22

0pF

21

CN

1D22

0pF

CN

1D22

0pF

87

CN

3A22

0pF

CN

3A22

0pF

21

CN

2A22

0pF

CN

2A22

0pF

21

CN

3B22

0pF

CN

3B22

0pF

43

C870.1uFC870.1uF

C1030.1uFC1030.1uF

SER_PORT

2213S-10G-E10-F2

SER_PORT

2213S-10G-E10-F2

13 4

2

5 67 89

CN

4C22

0pF

CN

4C22

0pF

65

C680.1uFC680.1uF

CN

2B22

0pF

CN

2B22

0pF

43

JP_COM1_VSEL(2-3)

MINI-JUMPER

JP_COM1_VSEL(2-3)

MINI-JUMPER

CN

3C22

0pF

CN

3C22

0pF

65

JP_COM1_VSEL

2211S-04G-BK-F2

JP_COM1_VSEL

2211S-04G-BK-F2

1

34

2

CN

2C22

0pF

CN

2C22

0pF

65

CN

3D22

0pF

CN

3D22

0pF

87

F1SMD0805P050TF

F1SMD0805P050TF

1 2

CN

2D22

0pF

CN

2D22

0pF

87

C1060.1uFC1060.1uF

CN

4D22

0pF

CN

4D22

0pF

87

R20 0R20 0

C1070.1uFC1070.1uF

COM2

2213S-10G-E10-F2

COM2

2213S-10G-E10-F2

13 4

2

5 67 89

U13

GD75232PWR

U13

GD75232PWR

V+ 1

DIN116

DIN215

DIN313

ROUT119

ROUT218

ROUT317

ROUT414

ROUT512

V- 10GND11RIN5 9

RIN4 7

RIN3 4RIN2 3RIN1 2

DOUT3 8

DOUT2 6DOUT1 5

VCC20

C5410uFC5410uF

CN

1A22

0pF

CN

1A22

0pF

21

U10

GD75232PWR

U10

GD75232PWR

V+ 1

DIN116

DIN215

DIN313

ROUT119

ROUT218

ROUT317

ROUT414

ROUT512

V- 10GND11RIN5 9

RIN4 7

RIN3 4RIN2 3RIN1 2

DOUT3 8

DOUT2 6DOUT1 5

VCC20

C1000.1uFC1000.1uF

C6510uFC6510uF

U15

MAX232DR

U15

MAX232DR

T1IN11T2IN10R1O12R2O9

T1O 14T2O 7

R1IN 13R2IN 8

VCC16

GND15

C1+1

C1-3

C2+ 4

C2- 5

V+ 2

V- 6

C1080.1uFC1080.1uF

CN

1B22

0pF

CN

1B22

0pF

43

C850.1uFC850.1uF

R41 0R41 0

F2SMD0805P050TF

F2SMD0805P050TF

1 2C670.1uFC670.1uF

VGA_COM1A

C020388-2

VGA_COM1A

C020388-2

C1C6C2C7C3C8C4C9C5

G1

G2

CN

4B22

0pF

CN

4B22

0pF

43

JP_COM2_VSEL(2-3)

MINI-JUMPER

JP_COM2_VSEL(2-3)

MINI-JUMPERC860.1uFC860.1uF

CN

1C22

0pF

CN

1C22

0pF

65

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

-LP_STB

-LP_STB

-LP_ACK

LP_PE

LP_D2

LP_BUSY

LP_BUSY

LP_SLCTLP_PE

LP_D4

-LP_ERR

-LP_ACK

LP_D5

LP_D1

-LP_INIT

LPT

_VC

C

LP_SLCT

-LP_AFD

LP_D7

-LP_SLIN

LP_D6

LP_D3

LP_D0

LP_D6

-LP_ACK

LP_D4

LP_D2LP_D1 -LP_INIT

-LP_ERR-LP_STB

LP_D5

LP_BUSY

-LP_AFD

LP_SLCT

-LP_SLIN

LP_D7

LP_PE

LP_D0

LP_D3

ROM_A5

LCLK_ROM2

ID1

LPC_AD2

CE

-BIOS_DIS0

-LPC_FRAME

ROM_A6

-ROM_OE

ID2

ROM_NC

ROM_CLK

LPC_AD1LPC_AD0

ROM_A7ROM_A8

ROM_A4

ROM_A9

LPC_AD3

ROM_A10

-LP_ERR

LP_D4LP_D5

LP_D7LP_D6

LP_D0LP_D1

LP_D3LP_D2

-SPI_SS0SPI_DI

SPI_VCC

-SPI_HOLD-SPI_WP

SPI_DOSPI_CLK

-SPI_HOLD

ROM_OE

-LP_SLIN

-LP_AFD-LP_INIT

ID0

ID3

-ROM_OE

-ROM_OE

-LP_STB[8]


LP_SLCT[8]LP_PE[8]

LCLK_ROM2[12]-ROM_RESET[13]

LPC_SERIRQ[4,8]-LPC_FRAME [4,8,21]LPC_AD3 [4,8,21]

LPC_AD0[4,8,21]

LPC_HEADER [12]LPC_AD1[4,8,21]-LPC_RESET[13]

-LPC_DRQ1[4]

LPC_AD2[4,8,21]

-BIOS_DIS0 [4]

-LP_ERR[8]

LP_D4[8]LP_D5[8]

LP_D7[8]LP_D6[8]

LP_D0[8]LP_D1[8]

LP_D3[8]LP_D2[8]

RST_SW [15]


SPI_VCC[4]


-BIOS_DIS1 [4]

AZ_SYNC [4,6]

AZ_BITCLK [4,6]-LP_SLIN[8]

-LP_AFD[8]-LP_INIT[8]

+5V

+3.3V

+3.3V

+5V

+3.3V+3.3V

+3.3V

+3.3V+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

Printer Port

LPC FLASH ROM


KEY

LPC HEADER


1 - 2 *

CARRIER LPC BIOS

MODULE SPI BIOS

BIOS_DIS0

1 - 2 *

BIOS Selection Table Pitch 2.54mm

SPI ROM

VIA Confidential

CARRIER SPI BIOS 2 - 3 2 - 3

2 - 31 - 2

BIOS DISABLE

MODULE LPC BIOS 1 - 2 2 - 3

BIOS Type Selection Table

LPC BIOS

1 - 2 *

1 - 2

BIOS_TypeBIOS_SEL1

2 - 3 *SPI BIOS

BIOS_SEL0

2 - 3

AZ_SYNCAZ_BITCLK

RN62.7KRN62.7K

1 23 45 67 8

BIOS_DIS0(1-2)

MINI-JUMPER

BIOS_DIS0(1-2)

MINI-JUMPER

RN82.7KRN82.7K

1 23 45 67 8

BIOS_DIS1

HEADER_1X3

BIOS_DIS1

HEADER_1X3

21

3

SPI

2213S-08G-E7-F2

SPI

2213S-08G-E7-F2

13 4

2

5 68

RN92.7KRN92.7K

1 23 45 67 8

BIOS_SEL1

HEADER_1X3

BIOS_SEL1

HEADER_1X3

21

3

R1824.7KR1824.7K

BIOS_SEL0

HEADER_1X3

BIOS_SEL0

HEADER_1X3

21

3

C28 180pFC28 180pF

Q252N7002Q252N7002G

DS

BIOS_SEL1(2-3)

MINI-JUMPER

BIOS_SEL1(2-3)

MINI-JUMPER

C90.1uFC90.1uF

C26 180pFC26 180pF

C27 180pFC27 180pF

LPT

2213S-26G-E26-F2

LPT

2213S-26G-E26-F2

13 4

2

5 67 89 10

11 1213 1415 1617 1819 2021 2223 2425

U5

PCT25VF080B-80-4C-S2AE

U5

PCT25VF080B-80-4C-S2AE

CE#1

SO2

WP#3

VSS4 SI 5SCK 6

HOLD# 7VDD 8

BIOS_DIS0

HEADER_1X3

BIOS_DIS0

HEADER_1X3

21

3

C22 180pFC22 180pF

C29 180pFC29 180pF

R34 2.7KR34 2.7K

C130.1uFC130.1uF

RN72.7KRN72.7K

1 23 45 67 8

C23 180pFC23 180pF

C51 180pFC51 180pF

C24 180pFC24 180pFC25 180pFC25 180pF

BIOS_SEL0(1-2)

MINI-JUMPER

BIOS_SEL0(1-2)

MINI-JUMPER

C30 180pFC30 180pF

C33 180pFC33 180pFC34 180pFC34 180pF

R180 4.7KR180 4.7K

C31 180pFC31 180pFC32 180pFC32 180pF

C35 180pFC35 180pF

R1834.7KR1834.7K

R178 4.7KR178 4.7K

C36 180pFC36 180pF

Q232N7002Q232N7002G

DS

BIOS_DIS1(1-2)

MINI-JUMPER

BIOS_DIS1(1-2)

MINI-JUMPER

R1754.7KR1754.7K

C37 180pFC37 180pF

RN1C 10KRN1C 10K5 6

R1774.7KR1774.7K

RN1B 10KRN1B 10K3 4

RN1D 10KRN1D 10K7 8

RN1A 10KRN1A 10K1 2

R1 10KR1 10KR2 10KR2 10K

C45 22pF /XC45 22pF /X

U7A


U7A


VDD32

WE/LFRAME23

DQ721

DQ620

DQ519

DQ418

LCLK31

RST2

OE/INIT24

MODE29

GND16

NC127

NC/GND26

NC2 22

A1/ID1 11

A0/ID0 12

LAD1 14

LAD2 15

LAD3 17

A10/GPI4 30

A9/GPI3 3

A8/GPI2 4

A7/GPI1 5

A6/GPI0 6

NC3 1

LAD0 13

VDD25

A5/WP 7

A4/TBL 8

A3/ID3 9

A2/ID2 10

NC/CE28

RN2B 10KRN2B 10K3 4

R3 10KR3 10K

R29 10 /XR29 10 /X

C44 0.1uFC44 0.1uF

RN2C 10KRN2C 10K5 6

RN2A 10KRN2A 10K1 2

R28 0 /XR28 0 /X

R594.7KR594.7K

RN2D 10KRN2D 10K7 8

R27 0 /XR27 0 /X

R513 0R513 0

R614.7KR614.7K

Q82N7002Q82N7002G

DS

R604.7KR604.7K

Q92N7002Q92N7002G

DS

R512 0/XR512 0/X

R584.7KR584.7K

C210.1uFC210.1uFR26

4.7KR264.7K

LPC

2208S-20G-BK-E01-F2

LPC

2208S-20G-BK-E01-F2

13 4

2

5 67 89 10

11 1213 1415 1617 1819

R22 4.7KR22 4.7K

D5RLS4148D5RLS4148

U7

6601-32-01-F6

U7

6601-32-01-F6

A012

A111

A210

A39

A48

A57

A66

A75

A827

A926

A1023

A1125

A124

A1328

A1429

A153

A162

A1730CE 22

OE 24

WE 31

D0 13

D1 14

D2 15

D3 17

D4 18

D5 19

D6 20

D7 21

A181

+5V 32

GND 16

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

OP+_IN FAN_PWRFAN_IO2

FAN_PWM2TR_BASE

OP_OUT

FAN_IN1

TR_IN

OP+_IN FAN_P

EEPROM_AX

EEPROM_WP

OP_OUT

FANPWM1[8]

FAN_PWMOUT[4]

FAN_TACHIN [4]

FANIO1 [8]

I2C_CLK [4,15]I2C_DAT [4,15]

+3.3V

+3.3V

+12V_VCC+12V_VCC

+12V_VCC

+12V_VCC+12V_VCC+3.3V

+3.3V

+3.3V

+12V_VCC

+12V_VCC

Title


Date: Sheet of


COMBED2

CPU & SYSTEM FAN


AC

Title


Date: Sheet of


COMBED2

CPU & SYSTEM FAN


AC

Title


Date: Sheet of


COMBED2

CPU & SYSTEM FAN


AC

SYSTEM FAN

16V SMD

VIA Confidential

CPU FANEEPROM

+3.3V Write Protect

GND Normal Operation *EEPROM Write Protect

Device Address = 0x57(0xAE)

Q7HM772Q7HM772

1

32

C8410uFC8410uF

R89 1KR89 1KR96 15K_1%R96 15K_1%

+

-

U14ALM393DR

+

-

U14ALM393DR

3

21

84

C6622pFC6622pF

R560/XR560/X

C8222pFC8222pF

R57 1KR57 1K

D9RLS4148D9RLS4148

R974.7KR974.7K

C5010uFC5010uF

R65 57.6K_1%R65 57.6K_1%

C7022pFC7022pF

CPUFAN

2417SJ-03-01

CPUFAN

2417SJ-03-01

123

D15 RLS4148D15 RLS4148

R6622KR6622K

R454.7KR454.7K

R901KR901K

R881KR881K

R5210K/XR5210K/X

C4910uFC4910uF

R50 27KR50 27K


B

CE

SYSFAN

FAN_CONN

SYSFAN

FAN_CONN

12

3

R7415K_1%R7415K_1%

R5110KR5110K

R54510KR54510KR73

4.7K/XR734.7K/X

C720.1uFC720.1uF

R910/XR910/X

U9

AT24C04N-10SU-1.8

U9

AT24C04N-10SU-1.8

A01

A12

A23

GND4 SDA 5SCL 6WP 7

VCC 8R47 0R47 0

R75 47K_1%R75 47K_1%

C8310uFC8310uF

R42 0R42 0

+

-

U14BLM393DR

+

-

U14BLM393DR

5

67

84

R54610KR54610K

C33822uFC33822uF

C9522pFC9522pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LCLK_ROM2

LCLK_AK2001

LPC_HEADER

SIO_33_CLK

LPCCLK2LPCCLK1

LPCCLK5

LPCCLK4LPCCLK3

SRC_IN-SRC_IN

SDATASCLK

IREF


-HIGH_BW

OE_INV

-BYPASS

-SRC_DIV-SRC_STOP

+3.3VCLK_BF

-CLK_PD

PECLK0+PECLK0-

PECLK1+PECLK1-

PECLK2+PECLK2-

PECLK3+PECLK3-

PECLK4+PECLK4-

PEX8604_CLK-

PCIE_CLK1+

PCIE_CLK1-

PCIE_CLK4+

PCIE_CLK4-

PCIE_CLK5+

PCIE_CLK5-

PCIE_CLK6+

PCIE_CLK6-

PEX8604_CLK+

OE_INV

-HIGH_BW

-BYPASS

-SRC_DIV

-SRC_STOP

-CLK_PD

LCLK_AK2001 [21]LPC_HEADER [10]

SIO_33_CLK [8]

LCLK_ROM2 [10]

LPC_33_CLK[4]

PEX8604_CLK+ [22]PEX8604_CLK- [22]






SMB_CLK[4,15,24,25]SMB_DAT[4,15,24,25]

-PEREQ_1[24]

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

PCIE CLOCK BUFFER

VIA Confidential

LPC CLOCK BUFFER

TO PE1 SLOT

TO PE2 SLOT

TO Mini PCI-e

TO PEX8604

TO PE3 SLOT

meet Zdif=49.9 ohm

R226 22R226 22

R237 49.9_1%R237 49.9_1%

TP_CKG_LOCKTP_CKG_LOCK1R261 0R261 0

TP_LPC_CLK4TP_LPC_CLK41

R582 10KR582 10K

R44 22R44 22


C2250.1uFC2250.1uF

R241 49.9_1%R241 49.9_1%

R572 10K/XR572 10K/X

R221 0R221 0

R235 49.9_1%R235 49.9_1%

R567 10K/XR567 10K/X


R252 49.9_1%R252 49.9_1%

R251 22R251 22

C23010uFC23010uF

R232 49.9_1%R232 49.9_1%

FB8 AA-600Y03102FB8 AA-600Y03102

R576 10KR576 10K

R231 22R231 22

R30 22R30 22

R227 49.9_1%R227 49.9_1%

R573 10KR573 10K

R246 10KR246 10K

R570 10K/XR570 10K/X

R248 49.9_1%R248 49.9_1%

C2450.1uFC2450.1uF

R579 10KR579 10K

R229 49.9_1%R229 49.9_1%

R250 10K/XR250 10K/X

R225 22R225 22


R224 49.9_1%R224 49.9_1%

R581 10KR581 10K

R574 10KR574 10K

C7122pF/XC7122pF/X

U32

ICS9DB801BGLF

U32

ICS9DB801BGLF

SCLK23

SDATA24

VDD12

VDD211

VDD319

GNDA 47

VDD539

SRC_IN4

DIF_0 8

DIF_0# 9

DIF_1 12

DIF_1# 13

DIF_2 16

DIF_2# 17

DIF_3 20

DIF_3# 21

DIF_4 30

DIF_4# 29

DIF_5 34

DIF_5# 33

SRC_IN#5

GND2 10

GND3 18

GND4 25

GND5 32

VDDA48

GND1 3

VDD431

DIF_6 38

DIF_6# 37

DIF_7 42

DIF_7# 41

OE_06

OE_114

OE_215

OE_37

OE_443

OE_535

OE_636

OE_744

OE_INV40

SRC_DIV#1

BYPASS#/PLL22

SRC_STOP#27

PD#26

HIGH_BW#28

IREF46

LOCK 45

R568 10KR568 10K

R43 22R43 22

R255 475_1%R255 475_1%

C2230.1uFC2230.1uF

C590.1uFC590.1uF

C2370.1uFC2370.1uF

R247 22R247 22

R259 10K/XR259 10K/X

R256 0R256 0

FB35 AA-600Y03102FB35 AA-600Y03102

R234 22R234 22

R575 10KR575 10K

R236 22R236 22R571 10KR571 10K


C2380.1uFC2380.1uF

C6010uFC6010uF

R242 22R242 22

R578 10KR578 10K

R230 22R230 22

R222 0R222 0

R254 10KR254 10K

R40 22R40 22

R262 0R262 0

U6

CY23S05SXC-1

U6

CY23S05SXC-1

REF1

CLK2 2CLK1 3

GND4

CLKOUT 8

CLK4 7

VDD6

CLK3 5

+

CE331000uF/10V

+

CE331000uF/10V

12

R243 49.9_1%R243 49.9_1%

R240 22R240 22

R577 10K/XR577 10K/X

R580 10KR580 10K

R569 10KR569 10K

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CON_R

CON_G

CON_VS

CON_B

CON_HS

V_SYNC

H_SYNC

CRTSPCLK

CRTSPD

SATA_GND

VGA_PS

CRT_SPCLK [4]

CRT_SPD [4]VGA_G[4]

VGA_R[4]

VGA_B[4]

VGA_VSYNC[4]

VGA_HSYNC[4]

SATA_GND[4]

SATA0_RX+[4]

SATA0_TX-[4]

SATA0_RX-[4]

SATA0_TX+[4]

SATA1_TX+[4]SATA1_TX-[4]


-CB_RESET[4]

-SIO_RESET [8]

-ROM_RESET [10]

-LPC_RESET [10]

-80_PORT_RESET [21]

-SLOT_RST [26]

+5VCRT

+3.3V

+5VCRT

+3.3V

+3.3V

+5VCRT

+5VCRT

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+5V

+5VCRT

+5VCRT

+12V_VCC

Title


Date: Sheet of


COMBED2

SATA & VGA


AC

Title


Date: Sheet of


COMBED2

SATA & VGA


AC

Title


Date: Sheet of


COMBED2

SATA & VGA


AC


VGA

VIA Confidential

SATA

2A

D1BAT54SD1BAT54S

2

3

1

D2BAT54SD2BAT54S

2

3

1

D8

BAT54S

D8

BAT54S

2

3

1

R55 22R55 22

U12E

SN74LV04ADR

U12E

SN74LV04ADR

11 10

147

Q62N7002Q62N7002 G

D S

L6 CB-47CJ02101L6 CB-47CJ02101

U2

74AHCT1G08GV

U2

74AHCT1G08GV

12

43

5

C1012pFC1012pF

FB1

QT2012RL600HC2ALF

FB1

QT2012RL600HC2ALF

C6210pFC6210pF

U12C

SN74LV04ADR

U12C

SN74LV04ADR

5 6

147

R46150_1%R46150_1%

R72 22R72 22

D3BAT54SD3BAT54S

2

3

1

SATA2

WATF-07DBN6SB1UW

SATA2

WATF-07DBN6SB1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

C7310pFC7310pF

Q52N7002Q52N7002

G

D S


G

DS

C10.1uFC10.1uF

D6BAT54SD6BAT54S

2

3

1U3

74AHCT1G08GV

U3

74AHCT1G08GV

12

43

5

C4210pFC4210pF

C1712pFC1712pF

U12F

SN74LV04ADR

U12F

SN74LV04ADR

13 12

147

R39150_1%R39150_1%

R85 22R85 22

D4

BAT54S

D4

BAT54S

2

3

1

C6110pFC6110pF

R141.5KR141.5K

U12A

SN74LV04ADR

U12A

SN74LV04ADR

1 2

147

R11 22R11 22

R191.5KR191.5K

L8 CB-47CJ02101L8 CB-47CJ02101

U12D

SN74LV04ADR

U12D

SN74LV04ADR

9 8

147

R77 22R77 22

R25150_1%R25150_1%

C4110pFC4110pF

R351.5KR351.5K

C800.1uFC800.1uF

D7

BAT54S

D7

BAT54S

2

3

1

R17 22R17 22

PS1

SMD1206P150TF_1.5A

PS1

SMD1206P150TF_1.5A

12

R211.5KR211.5K

U12B

SN74LV04ADR

U12B

SN74LV04ADR

3 4

147

L7 CB-47CJ02101L7 CB-47CJ02101

VGA_COM1B

C020388-2

VGA_COM1B

C020388-2

V6

G3

V1V7V2V8V3V9V4

V10

G4

V5

V11

V12

V13

V14

V15

SATA1

WATF-07DBN6SB1UW

SATA1

WATF-07DBN6SB1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

C7410pFC7410pF

R510 22R510 22

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

-A7_L

A0_L

A7_L

A3_L

CLK1_L

-A6_L

-A5_L

-CLK1_L

SPCLK_R

-CLK1_L

-A2_L

-A4_L

-A1_LA5_L

SPD_R

A6_L

-CLK2_L

-A7_L

-A4_L

A6_L

CLK2_L

A2_L

CLK1_L

A7_L

A4_L

A2_L

-A5_L

-A3_L

-A6_L

-A0_L

CLK2_L-CLK2_L

-A1_L

A4_L

-A3_L

-A0_L

A3_L

A1_L

-A2_L

A0_L

A5_LA1_L

BAKLITE

IVDD_GND

LVDS_I2C_DAT

-BKLT_EN

IVDD_IN

LVDS_I2C_CK

BLT_CTRL

PVDD_SEL

VDD_EN

PVDD_ON

-VDD_EN

PVDD

IVDD_SEL

BKLT_EN

PVDD_TR

PVDD

LVDS_A0+[4]

LVDS_A0-[4]

LVDS_A1+[4]

LVDS_A1-[4]

LVDS_A2+[4]

LVDS_A2-[4]

LVDS_A3+[4]

LVDS_A3-[4]

LVDS_A_CK+[4]

LVDS_A_CK-[4]

LVDS_B0+[4]

LVDS_B2+[4]

LVDS_B1-[4]

LVDS_B_CK+[4]

LVDS_B_CK-[4]

LVDS_B1+[4]

LVDS_B3+[4]

LVDS_B3-[4]

LVDS_B2-[4]

LVDS_B0-[4]

LVDS_I2C_CK[4]LVDS_I2C_DAT[4]

LVDS_BKLT_EN[4]

LVDS_VDD_EN[4]

BLT_CK[4,5,26]

+5V

+5V

+12V_VCC

+5V +3.3V

+5V

+5V

+5V

Title


Date: Sheet of


COMBED2

LVDS


AC

Title


Date: Sheet of


COMBED2

LVDS


AC

Title


Date: Sheet of


COMBED2

LVDS


AC

+12V *

IVDD_SEL

+5V Pin 1,2 : Close

Pin 2,3 : Close



+5V

Pin 2,3 : Close

PVDD

Pin 1,2 : Close

+3.3V *

LVDS CONNECTOR


VIA Confidential


B

EC

IVDDHEADER_1X3

IVDDHEADER_1X3

2 13

L33 ACM2012-900-2P-T002L33 ACM2012-900-2P-T002

1 4

32

FB2BLM21PG300SN1D

FB2BLM21PG300SN1D

Q42N7002Q42N7002G

DS

L31 ACM2012-900-2P-T002L31 ACM2012-900-2P-T0021 4

32

C184 0.1uFC184 0.1uF

PVDD(2-3)

MINI-JUMPER

PVDD(2-3)

MINI-JUMPER

C50.1uFC50.1uF

Q22SI2301BDS-T1-E3Q22

SI2301BDS-T1-E3G

DS

L29 ACM2012-900-2P-T002L29 ACM2012-900-2P-T002

1 4

32

U1

AD5301BRTZ

U1

AD5301BRTZ

GND1

A0 5

VOUT 4SCL3SDA2

VDD 6


B

EC

L27 ACM2012-900-2P-T002L27 ACM2012-900-2P-T002

1 4

32

L35 ACM2012-900-2P-T002L35 ACM2012-900-2P-T0021 4

32

C2 0.1uFC2 0.1uFR17933R17933

R5 0R5 0

R185 0R185 0

C1630.1uFC1630.1uF

INVERTER

1251S-08-SM1-TR-F5

INVERTER

1251S-08-SM1-TR-F5

11

22

33

44

55

66

8877

M1M1

M2M2

C160.1uFC160.1uF

C19 0.1uFC19 0.1uF

R164.7KR164.7K

IVDD(2-3)

MINI-JUMPER

IVDD(2-3)

MINI-JUMPER

L28 ACM2012-900-2P-T002L28 ACM2012-900-2P-T0021 4

32

R184 1KR184 1K

L37 ACM2012-900-2P-T002L37 ACM2012-900-2P-T002

1 4

32

L25 ACM2012-900-2P-T002L25 ACM2012-900-2P-T0021 4

32

+

CE147uF

+

CE147uF

12

R6470_1%R6470_1%

R1814.7KR1814.7K

L40 ACM2012-900-2P-T002L40 ACM2012-900-2P-T002

1 4

32

C1970.1uFC1970.1uF

LVDS

20031-040U-01

LVDS

20031-040U-01

2 14 36 58 7

10 912 1114 1316 1518 1720 1922 2124 2326 2528 2730 2932 3134 3336 3538 3740 39

Q242N7002Q242N7002G

DS


PVDDHEADER_1X3

PVDDHEADER_1X32

1 3

FB19BLM21PG300SN1D

FB19BLM21PG300SN1D

R15 1KR15 1K

R4 0/XR4 0/X

L26 ACM2012-900-2P-T002L26 ACM2012-900-2P-T0021 4

32

R186 0R186 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

5V_DIO1 12V_DIO1

-PLED_2

GND

-SLEEP_LED

Q22_B

Q11_Q

12

-PLED_2

FP_1_3 FP_2

FP_7

Q21_G

GND

FP_14

-PW_BTN

RST_SW

-PLED_2FP_1_3 -SATA_LEDFP_2

RST_SW

5V_DIO2 12V_DIO2

-SYS_RESET

-PW_BTN-RST1

COM_GPO0

COM_GPI2COM_GPI3COM_GPO1

COM_GPI0COM_GPI1COM_GPO3COM_GPO2

-RST2

COM_GPO1[4]COM_GPI2 [4]

COM_GPO3[4] COM_GPI3 [4]COM_GPO2[4]

COM_GPO0[4]COM_GPI1 [4]COM_GPI0 [4]

-SATA_LED [4]

SPEAK[21]

-PW_BTN [4]

-SUSC[4]

-PLED[8]

RST_SW [10]

-WDT_OUT[4]

-SYS_RESET [4]



SIO_GPI34 [8]SIO_GPI35 [8]SIO_GPI36 [8]SIO_GPI37 [8]

SMB_CLK [4,12,24,25]SMB_DAT [4,12,24,25] I2C_CLK [4,11]

I2C_DAT [4,11]

SDPOFF[4]

-SUSA[4]

+12V_VCC+5V

+5V

+5VDUAL +3.3V

+5V

+3.3VSUS

+3.3V

+3.3V

+5V +12V_VCC

+3.3V

+5VSUS+5VSUS

SDIO_PWR

+3.3VSUS

+5VSUS

SDIO_PWR+3.3VSUS

Title


Date: Sheet of


COMEBD2

FPNL, DIO, SMBUS, I2C & MFX


AC

Title


Date: Sheet of


COMEBD2



AC

Title


Date: Sheet of


COMEBD2



AC

SPEAK

FRONT PANEL

RESET

PW-BN

HD-LED

PW-LED PWRBTN

SMBUS

RESET_BTN

Digital I/O

VIA Confidential

RESET_IC

I2C_BUS SDIO

COM_GPI2COM_GPI3

COM_GPI0COM_GPI1

COM_GPO2COM_GPO3

COM_GPO0COM_GPO1

SD_D0SD_D1SD_D2SD_D3SD_CLKSD_CMDSD_WPSD_CD#

GPIO SDIO

R356 0/XR356 0/X

RST_BTN

PT-002-E1

RST_BTN

PT-002-E1

1

2

3

4



1 2

PWR_LED

LED LAMP GREEN

PWR_LED

LED LAMP GREEN

1 2

SMBUS

HEADER_1X3

SMBUS

HEADER_1X3

21

3

R366 2.2KR366 2.2K

R3554.7K/XR3554.7K/X

F_PANEL

2213S-16G-E15-F2

F_PANEL

2213S-16G-E15-F2

13 4

2

5 67 89 10

11 1213 14

16

R511 2.2KR511 2.2K

R345 0R345 0

R563 10KR563 10K

R3574.7K /XR3574.7K /X

R349 330R349 330

C2790.01uFC2790.01uF

R358 2.2K/XR358 2.2K/X

R353 68R353 68

R3394.7K /XR3394.7K /X

SDC009-A0-0000

SDIO

SDC009-A0-0000

SDIO

DAT2/RSV SD_9

DAT3/CD/CS SD_1

CMD/DI SD_2

VSS1 SD_3

VDD SD_4

CLK/SLK SD_5

VSS2 SD_6

DAT0 SD_7

DAT1 SD_8

SD_WP SD_11

GND G1

SD_CDT SD_10

GND G2

GND G3

GND G4

U31

MIC6315-44D4UY/X

U31

MIC6315-44D4UY/X

VC

C4

RST 2

GN

D1

MR3

R367330R367330

U30

MIC6315-44D4UY/X

U30

MIC6315-44D4UY/X

VC

C4

RST 2

GN

D1

MR3

DIO2

2213S-12G-F2

DIO2

2213S-12G-F2

13 45 67 89 10

11 12

2

R564 4.7KR564 4.7K

I2C_BUS

HEADER_1X3

I2C_BUS

HEADER_1X3

21

3

R359330R359330

HDD_LED

17-21VRC/TR8

HDD_LED

17-21VRC/TR8

1 2

U28

NC7SZ08M5X_NL/X

U28

NC7SZ08M5X_NL/X

12

43

5

TP_SLEEP_LEDTP_SLEEP_LED1

PWR_BTN

PT-002-E1

PWR_BTN

PT-002-E1

1

2

3

4

PS7SMD1206P050TF/15

PS7SMD1206P050TF/15

1 2

R3404.7KR3404.7K

PS6SMD1206P050TF/15

PS6SMD1206P050TF/15

1 2



1 2

R341 0/XR341 0/X

R3301M/XR3301M/X

DIO1

2213S-12G-F2

DIO1

2213S-12G-F2

13 45 67 89 10

11 12

2


B

EC

R319 1KR319 1K

Q28APM4463KC-TRGQ28APM4463KC-TRG

4

61

72 3

85

Q322N7002Q322N7002

G

DS

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VUSB6

USBD_T6+

-ROC6_7

USBD_T6- USBD_T7-USBD_T7+

USBH_DT6-

USBH_DT6+

USBD_T6-

USBD_T6+

VUSB4_5

USBD_T4+USBD_T4-

USBD_T5+USBD_T5-

-ROC4_5

USBD_T5-

USBD_T4-

USB_DT5-USBD_T5+USB_DT5+

USB_DT4-USB_DT4+ USBD_T4+

USBD_T4-

USBD_T4+

USBD_T5-

USBD_T5+

USBD_T7+

USBD_T7-

USBH_DT6+USBH_DT6-

-USB_OC6_7[4]

W_LESS_LED [18]

-USB_OC4_5[4]

-RF_ON [8]

USB_DT4-[4]

USB_DT5-[4]

USB_DT4+[4]

USB_DT5+[4]

USB_DT6-[4,24]USB_DT6+[4,24]

USB_DT7+[4]

USB_DT7-[4]

+5VDUAL

+5VDUAL

Title


Date: Sheet of


COMBED2

USB 2.0_4 Ports


AC

Title


Date: Sheet of


COMBED2

USB 2.0_4 Ports


AC

Title


Date: Sheet of


COMBED2

USB 2.0_4 Ports


AC

VIA Confidential

USB 2.0 Port 2/3

USB 2.0 Port 0/1

1. VUSB4(+5VDUAL)

5. W_LESS_LED

6. -RF_ON

Active High

VNT

4. GND

3. USBD_T5+

USBD_T5- , USBD_T5+for VNT 6656

2. USBD_T5-

Active Low

VNT Connector: 1x6 2.54mm

USB2 0/1


R23 68KR23 68K

JP_USB2_SEL(3-4)

MINI-JUMPER

JP_USB2_SEL(3-4)

MINI-JUMPER

C381uFC381uF

C60.1uFC60.1uF

USB2_2/3

USB_CONN

USB2_2/3

USB_CONN

13 4

2

5 67 8

10

C70.1uFC70.1uF

R24 68KR24 68K

RN31 0/XRN31 0/X1 23 4

USB2_0/1

2208S-12G-E09-F2

USB2_0/1

2208S-12G-E09-F2

13 4

2

5 67 8

1011 12

PS22APS22A

12

C40.1uFC40.1uF

+

CE3220uF

+

CE3220uF

12


C391uFC391uF

C471000pFC471000pF

R7 0R7 0

+

CE2220uF

+

CE2220uF

12

RN30 0/XRN30 0/X1 23 4


L3ACM2012-900-2P-T002L3ACM2012-900-2P-T002

1 4

32

C481000pFC481000pF

JP_USB2_SEL

2213S-04G-F2

JP_USB2_SEL

2213S-04G-F2

13 4

2

R3182KR3182K

L1ACM2012-900-2P-T002L1ACM2012-900-2P-T002

1 4

32

PS32APS32A

12

R3282KR3282K

L4ACM2012-900-2P-T002L4ACM2012-900-2P-T002

1 4

32

JP_USB2_SEL(1-2)

MINI-JUMPER

JP_USB2_SEL(1-2)

MINI-JUMPER

L2ACM2012-900-2P-T002L2ACM2012-900-2P-T002

1 4

32

C30.1uFC30.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SS_TX1+SS_TX1-

SS_RX1+SS_RX1-

USB2_HP1+USB2_HP1-

5V_DP0

SS_RX0+SS_RX0-

5V_DP1

USB3_SSRX0+

SS_TX0-

USB3_SSTX0+_


USB3_SSRX0-

USB3_SSTX0-_

SS_TX0+

SS_RX0-

SS_TX0-SS_RX0+

SS_TX0+USB3_SSTX1-_

USB3_SSTX1-_

SS_TX1+

USB3_SSTX1+_

USB3_SSTX1+_

SS_TX1-

USB2_HP1+

USB2_HP1-

USB2_DT1-USB2_DT1+

SS_TX1+

USB2_HP1-

SS_TX1-

USB2_HP1+

SS_TX3-

USB2_HP3+USB2_HP3-

5V_DP2

SS_TX3+

SS_RX3+SS_RX3-

SS_TX2+SS_TX2-

SS_RX2+SS_RX2-

5V_DP3USB2_HP2-USB2_HP2+

USB3_SSRX2+USB3_SSRX2-

USB2_HP2-

USB2_HP2+

USB2_DT2-USB2_DT2+

SS_RX2-

USB2_HP2+USB2_HP2-

SS_RX2+USB3_SSRX3-USB3_SSRX3+SS_RX3+

SS_RX3-

USB3_SSTX0+_


USB3_SSTX1+_

USB3_SSTX3-_

USB3_SSTX3+_

USB3_SSTX2-_

USB3_SSTX2+_

SS_RX2-

SS_RX2+

SS_RX3-

SS_RX3+

SS_RX0-

SS_RX0+

SS_TX0+SS_TX0-

SS_RX1-

SS_RX1+

SS_RX1-SS_RX1+


SS_TX2+SS_TX2- SS_TX3-

SS_TX3+USB3_SSTX2-_USB3_SSTX2+_

USB3_SSTX3-_USB3_SSTX3+_

USB2_DT3-USB2_DT3+

USB2_HP3-USB2_HP3+

SS_TX2-

SS_TX2+

USB3_SSTX2-_

USB3_SSTX2+_

SS_TX3-

SS_TX3+

USB3_SSTX3-_

USB3_SSTX3+_

USB2_HP3-

USB2_HP3+

USB2_HP0+USB2_HP0-

USB2_HP0-

USB2_HP0+

USB2_HP0-USB2_HP0+

USB2_DT0-USB2_DT0+

USB2_DT1+ [4]

USB2_DT1- [4]

USB2_DT2+ [4]

USB2_DT2- [4]

USB3_SSTX0+ [5]

USB3_SSTX0- [5]

USB3_SSTX1+ [5]

USB3_SSTX1- [5]

USB3_SSTX3+ [5]

USB3_SSTX3- [5]

USB3_SSTX2+ [5]

USB3_SSTX2- [5]

USB3_SSRX2- [5]

USB3_SSRX2+ [5]

USB3_SSRX3- [5]

USB3_SSRX3+ [5]

USB3_SSRX0+ [5]

USB3_SSRX0- [5]

USB3_SSRX1- [5]

USB3_SSRX1+ [5]

-USB2_OC2_3[4]

-USB2_OC0_1[4]

USB2_DT3+ [4]

USB2_DT3- [4]

USB2_DT0+ [4]

USB2_DT0- [4]

+5V_DP0

+5V_DP2

+5V_DP2

+5V_DP3 USB3_+5V

+3.3VSUS

+5V_DP0

+5V_DP1 USB3_+5V

+3.3VSUS

+5V_DP3

+5V_DP1

Title


Date: Sheet of


COMBED2

USB 3.0_4 Ports


AC

Title


Date: Sheet of


COMBED2

USB 3.0_4 Ports


AC

Title


Date: Sheet of


COMBED2

USB 3.0_4 Ports


AC

USB 3.0 Port 0 & 1

Co-Layout

VIA Confidential

Co-Layout

USB 3.0 Port 2 & 3

Co-Layout Co-Layout



1.5A

1.5A

1.5A

1.5A

RN13 0/XRN13 0/X

1 23 4

D16 AZ

C19

9-02

S.R

7GD

16 AZ

C19

9-02

S.R

7G

1 23

+

CE8100uF

+

CE8100uF

12

C77 0.1uFC77 0.1uF

R63010KR63010K

R6214.7KR6214.7K

R61910KR61910K

C98 0.1uFC98 0.1uF



Line-3 4Line-4 5NC6

NC7

NC9

NC10

RN12 0/XRN12 0/X1 23 4

RN14 0/XRN14 0/X

1 23 4

R6204.7KR6204.7K

C35010uF /XC35010uF /X

R6244.7KR6244.7K

D19 AZ

C19

9-02

S.R

7GD

19 AZ

C19

9-02

S.R

7G

1 23

RN18 0/XRN18 0/X1 23 4

R62210KR62210K


U34

AIC1528-0GSTR

U34

AIC1528-0GSTR

CTLA1

FLGA2

FLGB3

CTLB4 OUTB 5GND 6

IN 7OUTA 8

USB3_LANA

05-000730003-1

USB3_LANA

05-000730003-1

U9U8U7U6

U18U17U16U15

G1 G3G2

U5

U1U2U3U4

U14

U10U11U12U13

G4

R6234.7KR6234.7K

D13L15ESDL5V0NA-4

D13L15ESDL5V0NA-4


NC 7

NC 9

NC 10

L14 ACM2012-900-2P-T002L14 ACM2012-900-2P-T002

1 4

32

+

CE7100uF

+

CE7100uF

12

RN16 0/XRN16 0/X1 23 4

U35

AIC1528-0GSTR

U35

AIC1528-0GSTR

CTLA1

FLGA2

FLGB3

CTLB4 OUTB 5GND 6

IN 7OUTA 8

D14 AZ

C19

9-02

S.R

7GD

14 AZ

C19

9-02

S.R

7G1 2

3

RN20 0/XRN20 0/X

1 23 4

R62810KR62810K

RN10 0/XRN10 0/X1 23 4

L17 W2012B-900NPL17 W2012B-900NP1 4

32

RN19 0/XRN19 0/X

1 23 4

C34910uF /XC34910uF /X

C97 0.1uFC97 0.1uF

L9 W2012B-900NPL9 W2012B-900NP1 4

32

RN11 0/XRN11 0/X

1 23 4

RN21 0/XRN21 0/X

1 23 4

FB9BLM18PG300SN1D FB9BLM18PG300SN1D



Line-3 4Line-4 5NC6

NC7

NC9

NC10

L20 ACM2012-900-2P-T002L20 ACM2012-900-2P-T002

1 4

32

L10 W2012B-900NPL10 W2012B-900NP

1 4

32

D17L15ESDL5V0NA-4

D17L15ESDL5V0NA-4


NC 7

NC 9

NC 10

RN15 0/XRN15 0/X

1 23 4

+

CE6100uF

+

CE6100uF

12

C101 0.1uFC101 0.1uF

R62910KR62910K


L13 ACM2012-900-2P-T002L13 ACM2012-900-2P-T002

1 4

32

RN17 0/XRN17 0/X

1 23 4

L18 W2012B-900NPL18 W2012B-900NP

1 4

32

L15 W2012B-900NPL15 W2012B-900NP1 4

32

FB46 BLM18PG300SN1DFB46 BLM18PG300SN1D

C91 0.1uFC91 0.1uF

+

CE5100uF

+

CE5100uF

12

L11 W2012B-900NPL11 W2012B-900NP1 4

32

L16 W2012B-900NPL16 W2012B-900NP

1 4

32

L19 ACM2012-900-2P-T002L19 ACM2012-900-2P-T002

1 4

32

C76 0.1uFC76 0.1uF

FB45 BLM18PG300SN1DFB45 BLM18PG300SN1D FB10BLM18PG300SN1D FB10BLM18PG300SN1D

R63110KR63110K

C99 0.1uFC99 0.1uF

L12 W2012B-900NPL12 W2012B-900NP

1 4

32

USB3_2/3U33-10000003USB3_2/3U33-10000003

VBUS 1

D- 2

D+ 3

GND 4

SSRX- 5SSRX+ 6

GND 7SSTX- 8SSTX+ 9

G1

G1

G2

G2

SSTX+18

SSTX-17

GND16

SSRX+15

SSRX-14

VBUS10

D-11

D+12

GND13

G3

G3

G4

G4

D20 AZ

C19

9-02

S.R

7GD

20 AZ

C19

9-02

S.R

7G1 2

3

C88 0.1uFC88 0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LAN_-ACT

T_CT1

T_CT4

T_CT3

T_CT2

MCT2

MCT1

MCT0

-SP1000

-SP100

-ACT

-MDI0+MDI0

+MDI2-MDI2

-MDI3+MDI3

+MDI1

-MDI1

MCT3

MDI2-

MDI3+

MDI3-

MDI0+

MDI0-

MDI1+

MDI1-

MDI2+

-MDI3+MDI3

+MDI2-MDI2

-MDI1+MDI1

+MDI0-MDI0

W_LESS_LED[16]

LAN_-SP100 [4]

LAN_-SP1000 [4]

LAN_-ACT [4]

MDI0- [4]MDI0+ [4]

MDI1- [4]MDI1+ [4]

MDI3- [4]MDI3+ [4]

MDI2- [4]MDI2+ [4]

VDDTXRX_LAN [4]

+3.3VSUS

+3.3VSUS

RJ45_CGND

RJ45_CGND

RJ45_CGND

RJ45_CGND

Title


Date: Sheet of


COMBED2

RJ45/ LAN LED


AC

Title


Date: Sheet of


COMBED2

RJ45/ LAN LED


AC

Title


Date: Sheet of


COMBED2

RJ45/ LAN LED


AC

VIA Confidential

RJ45

1st : LAN LED


FRONT LAN LED

GST5009 LF / LG-2413S-1 / P1012


99G26-07053299G26-070542

99G26-07056F

99G26-07053J

VT6122 / VT6130

BothhandGST5009 LF

LG-2413S-1

P1012(001-00)

TST1284A LF

LF-H6442S-1

VT6107

P1212(007-00)

T1

LANKOM

UDE

VT6130 / RTL8111E T1 install GST5009 LFVT6107 T1 install TST1284A LF

RTL8111E /

VT6122 /

O:mount X:unmount

VT6107

RTL8111E

VT6122

GST5009 LF99G26-070532

TST1284A LF99G26-070542

T1 C124,C115

99G26-070532GST5009 LF

FB17 C118,C112,C105,C102(6.8pFx4)

O

X

X

O

O

X

X

Bi-Tripple-color mode

L9_LED1

LEDS1,LEDS0

Note:

01=100M Link(Green)

LED Selection

LED2,LED1=

Link/Act (Yellow)

RJ45 Link status GMTI_9711-8814-S0L30-E-A for VT6107

0,1

L10_LED2

00=Link off(Darkless)

11=10M Link(Darkless)

Link: LED on

L12_LED0

CASE_1

R111

O O

R104, R109

O X

X X

C104C110

0.01uF

0.1uF

X X

O X X

O

99G26-07055F

99G26-07058J

VT6130GST5009 LF99G26-070532 O O 0.1uF O O O X

R128 330R128 330

R11875R11875

C1040.1uFC1040.1uF

C114 0.1uFC114 0.1uF

Yellow/R

Green/L

Yellow/L

TX_D1+TX_D1-

BI_D3+

BI_D4-

BI_D3-RX_D2-BI_D4+

RX_D2+

USB3_LANB05-000730003-1

Yellow/R

Green/L

Yellow/L

TX_D1+TX_D1-

BI_D3+

BI_D4-

BI_D3-RX_D2-BI_D4+

RX_D2+

USB3_LANB05-000730003-1

R1R2R3R4R5R6

R8R7

G5G6

G7

G8L4L3L2L1

C1186.8pF/XC1186.8pF/X

T1

GST5009 LF

T1

GST5009 LF

TCT1 1

TD1+ 2

TD1- 3

TCT2 4

TD2+ 5

TD2- 6

TCT3 7

TD3+ 8

TD3- 9

TCT4 10

TD4+ 11

TD4- 12

MCT124

MX1+23

MX1-22

MCT221

MX2+20

MX2-19

MCT318

MX3+17

MX3-16

MCT415

MX4+14

MX4-13

R127 330R127 330

FLAN_LED

2208S-10G-E09-F2

FLAN_LED

2208S-10G-E09-F2

134

2

567

108

R100 330R100 330

R10875R10875

R1040R1040

C1126.8pF/XC1126.8pF/X

C1100.1uFC1100.1uF

R126 330R126 330


C1150.1uFC1150.1uF

C1056.8pF/XC1056.8pF/X

R99 330R99 330

R10675R10675

R1090R1090

C1240.1uFC1240.1uF


R110 330R110 330

C1026.8pF/XC1026.8pF/X

R10175R10175

R1110R1110

R129 330R129 330

C125 1000pF/2KVC125 1000pF/2KV

FB17CBG201209-260FB17CBG201209-260

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

P17P18

P19P16P15

P17

DP1TX_3+_

DP1TX_0-_

DP1TX_1+_DP1TX_1-_

DP1TX_2+_

DP1TX_3-_

P14

DP1TX_2-_DP1TX_0+_

P13P18

P15P16

P13P14

DP1TX_2+_

DP1TX_1+_ DP1TX_3+_DP1TX_3-_

DP1TX_0+_DP1TX_0-_ DP1TX_2-_

DP1TX_1-_

P19

DP1TX1-

PWR_Select

P16

P14P15

DP1TX3+

DP1TX2+

P17

DP1TX1+

DP1TX0+

DDI_CTRL_DATA

DP1TX2-

DP1TX3-

DP1TX_0-_DP1TX0-

DDI_CTRL_CLK

-DP1HPD

P15

P16 P19

DP1TX_1-_

DP1TX_1+_

DP1TX0+DP1TX0-

DP1TX1+DP1TX1-

DP1TX2+DP1TX2-

DP1TX3+DP1TX3-

DDI_CTRL_CLKDDI_CTRL_DATA

OVS

-OEBPRE

VSADJ

DP1TX_1+_

DP1TX_0+_DP1TX_0-_

DP1TX_1-_DP1TX1-

DP1TX0-DP1TX1+

DP1TX0+

DP1TX_3+_

DP1TX_2+_DP1TX_2-_

DP1TX_3-_DP1TX3-

DP1TX2-DP1TX3+

DP1TX2+

DDI_CTRLCLK

DDI_CTRLDATA

TMDS_RX0+TMDS_RX0-

TMDS_RX1+TMDS_RX1-

TMDS_RX2+TMDS_RX2-

TMDS_RXC+TMDS_RXC-

TMDS_RX2-

TMDS_RXC-

TMDS_RX1+

TMDS_RXC+

TMDS_RX0-

TMDS_RX2+TMDS_RX1-

TMDS_RX0+

P13

DP1TX2-

DP1TX1+

DP1TX1-

DP1TX2+

DP1TX0+

DP1TX3+

DP1TX3-

DP1TX0-

DP1TX_0+_

DP1TX_2+_

DP1TX_2-_DP1TX_3+_

DP1TX_3-_

-DP2_HPD[5]

DP2_TX2+[5]DP2_TX2-[5]

DP2_TX3+[5]DP2_TX3-[5]

DP2_TX0+[5]DP2_TX0-[5]

DP2_TX1+[5]DP2_TX1-[5]

DDI_CTRLCLK[5]DDI_CTRLDATA[5]

+12V

HDMI_PWR

HDMI_PWR

+3.3V+2.5V

+3.3V

+3.3V

+3.3V

+3.3V+3.3V

+3.3V

+5V

+3.3V

+3.3V

Title


Date: Sheet of


COMBED2

HDMI ReDriver TMDS141


AC

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

VIA Confidential

ESD


19

TMDS CLK+

H.P. Detect

Reserved

181716

TMDS D0+

TMDS D2-

GND ShieldTMDS D1-

SCL

TMDS D0-

DDC/CEC GND

14

2

20

CEC

GND Shield

5

GND Shield

+5V Power

12

6

SDA

4

7

3

TMDS CLK-

TMDS D1+

GND Shield

11

13

TMDS D2+HDMI

109

15

8

1

HPD

Vgs must lessthan 2.5V

0.5A for layout reference

DDC_AUX_SEL = 0, DP selectedDDC_AUX_SEL = 1, HDMI selected

HDMICLK

HDMIT2

HDMIT1

HDMIT0

HDMI

OVS TSCL/TSDA Output voltage select

I2CEN I2C Repeater enableLow: High-ZHigh: Active

OE TMDS Output enableLow: ActiveHigh: High-Z

PRE TMDS Output de-emphasis adjustmentLow: 0 dBHigh: 3.5 dB

NC, VOL is typically 0.5 VGND, VOL is typically 0.65 VVCC, VOL is typically 0.8 V

Note: Please place close to U33 TMDS141.

For HDMI; close to TMDS141

HDMIC022034HDMIC022034

123456789

10111213141516171819

G1

G2

G4

G3

R599 620_1%R599 620_1%

C1470.01uFC1470.01uF

R590 10K/XR590 10K/X

Q362N7002Q362N7002

G

DS

C188 0.1uFC188 0.1uF

L36 W2012B-900NPL36 W2012B-900NP1 4

32

C1480.01uFC1480.01uF


G

DS

R601 620_1%R601 620_1%

C186 0.1uFC186 0.1uF

R5350R5350


2

G1

34

1

56

78

C1500.01uFC1500.01uF

L34 W2012B-900NPL34 W2012B-900NP1 4

32

C1671uFC1671uF

C194 0.1uF/XC194 0.1uF/X


2

G1

34

1

56

78

R526 200/XR526 200/X

C185 0.1uFC185 0.1uF

R584 10K/XR584 10K/X

C1510.01uFC1510.01uF

Q352N7002Q352N7002

G

DS

C183 0.1uFC183 0.1uF

C1530.01uFC1530.01uF

L32 W2012B-900NPL32 W2012B-900NP1 4

32

R583 10KR583 10K


2

G1

34

1

56

78

R524 0R524 0

R596 620_1%R596 620_1%

C182 0.1uFC182 0.1uF

U33

TMDS141RHAR

U33

TMDS141RHAR

TX1# 13

GN

D14

RX2#1

I2CEN5

VC

C11

VC

C27

VC

C24

RX22

OE#6 PRE 7

TX2 9

TX2# 10

GN

D20

TXC# 19

GN

D3

RSDA28

VC

C4

TXC 18

TSDA 23TSCL 22

GN

D8

GN

D21

OVS25

TX1 12

TX0# 16TX0 15V

CC

17

GN

D26

RSCL29

VSADJ 30

GN

D31

RXC33

RXC#32

VC

C34

RX036

RX0#35

GN

D37

RX139

RX1#38

VC

C40

G1

G1

C1550.01uFC1550.01uF

C192 0.1uF/XC192 0.1uF/X

Q34FDC6301N/XQ34FDC6301N/X

G1

1

S2

2

G2

3D

24

S1

5

D1

6

R586 10K/XR586 10K/X

C181 0.1uFC181 0.1uF

C1580.01uFC1580.01uF

C191 0.1uF/XC191 0.1uF/X

D37 BAV99D37 BAV99

2

3

1

R589 10KR589 10K

L30 W2012B-900NPL30 W2012B-900NP1 4

32

R598 620_1%R598 620_1%R592 1.65K_1%R592 1.65K_1%

R591 1.65K_1%R591 1.65K_1%


2

G1

34

1

56

78

C179 0.1uFC179 0.1uF

R5364.7KR5364.7K

R528 4.7KR528 4.7K

R600 620_1%R600 620_1%

R530 4.7KR530 4.7K

RN23 0/XRN23 0/X1 23 4

R585 10KR585 10K

R542 1KR542 1K

FB20

ACMS160808A6001A

FB20

ACMS160808A6001A

R495 300_1%/XR495 300_1%/X

RN25 0/XRN25 0/X

1 23 4

R587 10KR587 10K

R525 0R525 0R527 200/XR527 200/X

R493 300_1%/XR493 300_1%/X

C193 0.1uF/XC193 0.1uF/X

R543100KR543100K

R595 620_1%R595 620_1%

RN22 0/XRN22 0/X1 23 4

R494 300_1%/XR494 300_1%/X

R594 620_1%R594 620_1%

C189 0.1uFC189 0.1uF

R593 10KR593 10K

PS10

SMD1206P150TF_1.5A

PS10

SMD1206P150TF_1.5A

1 2

R597 620_1%R597 620_1%

Q432N7002Q432N7002

G

DS

R500 300_1%/XR500 300_1%/X

RN24 0/XRN24 0/X

1 23 4

R5384.7KR5384.7K

R588 4.3K_1%R588 4.3K_1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-LP DP_ADJ_AUX_IN+

ML_IN0+_DPML_IN0-_DP


AUX_IN-

ML_IN2+_DP

VCC3_DP118_LF

ML_IN2-_DP


CA_DET_DP2DP2_HPD

CAD_INV

DP2TX2-

DP2TX3-

DP2TX_0-_

DP2TX_0+_

DP2TX0-

DP2TX_2+_DP2TX_1-_

DP2TX_1+_


DP2TX1-

DP2_P15

DP2_P17

DP2TX0+_

DP2TX_3+_DP2TX3+

DP2TX2+

DP2_P13

DP2TX2+_

DP2_P14

DP2TX1-_

DP2TX2-_DP2TX3+_

DP2TX1+_DP2TX0-_

DP2_P16

DP2_P19

DP2_P17DP2_P18

DP2_P15

DP2TX1+ DP2_P16

DP2_P18

DP2TX0+

DP2TX3-_DP2TX_3-_

DP2TX3+_

DP2TX0-_

DP2TX1+_DP2TX1-_

DP2TX2+_

DP2TX3-_




DP2TX1-_

DP2_HPD

CAD_OUT

DP_ADJ_AUX_IN+DP2_P17DP2_P15

DP2_P13

DP2_P14

CA_DET_DP2

DP2_P17 DP2_P17

DP2_PWR_

DP2_P15 DP2_P15

DP2_P18 DP2_P18DP2_P13 DP2_P13

DP2TX_1+_

DP2TX_0+_DP2TX_0-_

DP2TX_1-_DP2TX1-

DP2TX0-DP2TX1+

DP2TX0+

DP2TX_3+_

DP2TX_2+_DP2TX_2-_

DP2TX_3-_DP2TX3-

DP2TX2-DP2TX3+

DP2TX2+

DP2TX0+DP2TX0-

DP2TX3+DP2TX3-

DP2TX1+DP2TX1-

DP2TX2+DP2TX2-

-DP3_HPD[5]

DP3_AUX+[5]

DP3_AUX-[5]





+3.3V

+3.3V

DP2_PWR

DP2_PWR

+2.5V+5V

+3.3V

+12V_VCC

DP2_PWR

Title


Date: Sheet of


COMBED2

DP reDriver SN75DP120


AC

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

VIA Confidential

DP reDriver

HPD 19

ML_Lane0-

1817 AUX_CH-16

GNDML_Lane3+

14

H.P. Detect

2

20

GND

5

ML_Lane0+GND

AUX_CH+

12

6

4

7

3

DP_PWR_Return

ML_Lane1+

GND

GND

GND

11

13

ML_Lane2-10

ML_Lane2+

9

ML_Lane3-

15

8

DisplayPort

1

GND

ML_Lane1-

DP_PWR

ESD


LP Mode


75DP120 *75DP118

Install

Remove

RA

RB

RA, RB

RC

RC

RC

RA, RB

75DP118 75DP120

FB1

FB2

FB1 FB2Install

Remove FB2 FB1

Rev A

R124 0R124 0


G

DS

C146 0.1uFC146 0.1uF

U16

SN75DP120RHHT

U16

SN75DP120RHHT

VC

C1

4

CAD_INV31

GN

D2

7

LP33

HPD_OUT11CAD_OUT12

VC

C2

16

GN

D3

13

ML_OUT3- 19

VC

C3

24

ML_OUT2+ 23

ML_OUT2- 22

GN

D4

21

ML_OUT1+ 26

ML_OUT1- 25

VC

C4

28

ML_OUT0+ 30

ML_OUT0- 29

HP

D_I

NV

27

CAD_IN 14

HPD_IN 15


GN

D6

32V

CC

536

ML_IN3+8

ML_IN3-9

ML_IN2+5

ML_IN2-6

ML_IN1+2

ML_IN1-3

VD

D10

ML_IN0+34

ML_IN0-35

G1

G1

GN

D1

1

ML_OUT3+ 20

C1191uFC1191uF

R632 0R632 0

C140 0.1uFC140 0.1uF

FB14 AA-600Y03102/XFB14 AA-600Y03102/X

C157 0.1uFC157 0.1uF


2

G1

34

1

56

78

C1350.1uFC1350.1uF

R633 0R633 0

R116 0R116 0

R134 100KR134 100K

C137100pFC137100pF

C162 0.1uFC162 0.1uF


2

G1

34

1

56

78

L21 W2012B-900NPL21 W2012B-900NP1 4

32

PS8

SMD1812P160TF/8(4L)

PS8

SMD1812P160TF/8(4L)

1 2

C144 0.1uFC144 0.1uF

C127 0.1uFC127 0.1uF

C132 0.1uFC132 0.1uF

R131 0R131 0

RN29 0/XRN29 0/X

1 23 4

R125100KR125100K

C139 0.1uFC139 0.1uF

R115 0R115 0

C129 0.1uFC129 0.1uF

C1201uFC1201uF

R113 0R113 0R138 4.7KR138 4.7K

C1330.1uFC1330.1uF

R1146.49K_1%/XR1146.49K_1%/X

L23 W2012B-900NPL23 W2012B-900NP1 4

32

R1420R1420

FB15 AA-600Y03102FB15 AA-600Y03102

R136 100KR136 100K

C1360.01uFC1360.01uF

R117 100K/XR117 100K/X

C159 0.1uFC159 0.1uF

DP

47272-0001

DP

47272-0001

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

M1 M1

G1

G1

G2

G2

G3

G3

G4

G4

R137 0/XR137 0/X

R122 0_0805/XR122 0_0805/X


2

G1

34

1

56

78

C126 0.1uFC126 0.1uF

C152 0.1uFC152 0.1uF

C134 0.1uFC134 0.1uF

C154 0.1uFC154 0.1uF

C3420.01uFC3420.01uF

L24 W2012B-900NPL24 W2012B-900NP1 4

32

C3410.1uFC3410.1uF

C1310.1uFC1310.1uF

RN28 0/XRN28 0/X

1 23 4

R112 0R112 0

C130 0.1uFC130 0.1uF

R140 100KR140 100K

RN27 0/XRN27 0/X1 23 4

L22 W2012B-900NPL22 W2012B-900NP1 4

32 C149 0.1uFC149 0.1uF

C1220.01uFC1220.01uF

RN26 0/XRN26 0/X1 23 4

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-DGHLED_B

LED_ELED_C

LED_G

LED_DLED_FLED_A

-DGL

LED_E

LED_A

LED_G

LED_C

LED_B

LED_F

LED_D

-DGH

-DGL

LCLK_AK2001 [12]

-LPC_FRAME [4,8,10]

LPC_AD0 [4,8,10]

LPC_AD1 [4,8,10]

LPC_AD2 [4,8,10]

LPC_AD3 [4,8,10]

-80_PORT_RESET [13]

SPKR [4,6]

SPEAK [15]

+3.3V

+3.3V

+3.3V

+3.3V

+3.3VSUS

+5VDUAL

+5V

-12V

+12V_VCC

+5V

+5V

Title


Date: Sheet of


COMBED2

LPC Debug Port & LED


AC

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

LPC DEBUG PORT

LED

=R 30mA

V- Vf------------


BUZZER

VIA Confidential

R18 33R18 33

PORT_80


PORT_80


DG1

DA3

DF4


SEL1# 10

R36868R36868

R360 51R360 51

C15 0.1uFC15 0.1uF

+3_3V_LED

LED LAMP GREEN

+3_3V_LED

LED LAMP GREEN

1 2

R363 360R363 360

+12V_VCC_LED

LED LAMP GREEN

+12V_VCC_LED

LED LAMP GREEN

1 2

+5V_DUAL_LED

LED LAMP GREEN

+5V_DUAL_LED

LED LAMP GREEN

1 2

C20 0.1uFC20 0.1uF

R347 1KR347 1K

R33 33R33 33


B

EC

BUZZ

KC-1206

BUZZ

KC-1206

12

R362 110R362 110

+5V_LED

LED LAMP GREEN

+5V_LED

LED LAMP GREEN

1 2

R351 22R351 22

R365 360R365 360

C40 10uFC40 10uF

R350 4.7KR350 4.7K

C3331uFC3331uF

R361 51R361 51

+3_3VSUS_LED

LED LAMP GREEN

+3_3VSUS_LED

LED LAMP GREEN

1 2

-12V_LED

LED LAMP GREEN

-12V_LED

LED LAMP GREEN

12

U4

AK2001-G

U4

AK2001-G

DGH#1

GND2

LEDA3

LEDB4

LEDC5

LEDD6

LEDE7

LEDF8

LEDG9

VCC110 DGL# 11

GND 12

PCICLK 13

LFRAME# 14

LAD0 15

LAD1 16

LAD2 17

LAD3 18

PCIRST# 19

VCC2 20

R364 110R364 110

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PEX_PETn0PEX_PETp0PEX_CLK+

PEX_CLK- PCIE_RX0+ [4]PCIE_RX0- [4]

PCIE_TX0- [4]PCIE_TX0+ [4]


PEX_PETp4 [24]PEX_PETn4 [24]



PEX8604_CLK+[12]PEX8604_CLK-[12]



Title


Date: Sheet of


COMEDB2

PEX8604 PCI-e Switch/ClockBuffer


AC

Title


Date: Sheet of


COMEDB2



AC

Title


Date: Sheet of


COMEDB2



AC

Port1 to PE1 slot

Port4 to PE2 slot

Port5 to Mini-PCIe

Port0 from VX900

VIA Confidential

PEX 8604/8608

C261 0.1uFC261 0.1uFC260 0.1uFC260 0.1uF

R2741.43K_1%R2741.43K_1%

C339 0.1uFC339 0.1uF

PEX 8604

U24A

PEX8604-BA50BC G

PEX 8604

U24A

PEX8604-BA50BC G

PEX_PETp0 P4

PEX_PETp1 P6

N/C P9

N/C P11

PEX_PETp4 A11

PEX_PETp5 A9

N/C A6

N/C A4

PEX_PETn0 N4

PEX_PETn1 N6

N/C N9

N/C N11

PEX_PETn4 B11

PEX_PETn5 B9

N/C B6

N/C B4

PEX_PERp0 P3

PEX_PERp1 P5

N/C P10

N/C P12

PEX_PERp4 A12

PEX_PERp5 A10

N/C A5

N/C A3

PEX_PERn0 N3

PEX_PERn1 N5

N/C N10

N/C N12

PEX_PERn4 B12

PEX_PERn5 B10

N/C B5

N/C B3

PEX_REFCLKpN8

PEX_REFCLKnP8

REXT_A0P7

REXT_B0N7

REXT_A1B8

REXT_B1A8

PEX_REFCLK_CFCpB7

PEX_REFCLK_CFCnA7

N/CM8

N/CC7

R3351.43K_1%R3351.43K_1%

C340 0.1uFC340 0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PEX_LANE_GOOD0-

PEX_INTA-

PEX_LANE_GOOD1-

FATAL_ERR-

PEX_LANE_GOOD4-

SHPC_INT-

STRAP_NT_P2P_EN-

STRAP_SPAER0-STRAP_SPAER1-

PEX_LANE_GOOD5-

STRAP_UPCFG_TIMER_EN-STRAP_SMBUS_EN-

STRAP_RESERVED17-

PERST_PCIe_SWITCH-PEX_NT_RESET-

JTAG_TRST-

JTAG_TMSJTAG_TCK

JTAG_TDOJTAG_TDI

EE_CS-PEX8604A

EE_DO-PEX8604AEE_DI-PEX8604A

EE_SK-PEX8604A

STRAP_UPSTRM_PORTSEL1STRAP_UPSTRM_PORTSEL2

STRAP_UPSTRM_PORTSEL0

STRAP_UPSTRM_PORTSEL3

STRAP_NT_UPSTRM_PORTSEL0

STRAP_NT_UPSTRM_PORTSEL2STRAP_NT_UPSTRM_PORTSEL1

STRAP_NT_ENABLE-

STRAP_FAST_BRINGUP-

STRAP_PLL_BYPASS-STRAP_SSC_ISO_ENABLE-

STRAP_TESTMODE3

STRAP_TESTMODE1STRAP_TESTMODE0

STRAP_TESTMODE2

I2C_SCL0

I2C_ADDR1I2C_ADDR0

I2C_ADDR2

STRAP_SERDES_MODE_EN-


STRAP_PROBE_MODE-STRAP_DEBUG_SEL0

STRAP_PORTCFG1STRAP_PORTCFG0

I2C_SDA1I2C_SCL1

I2C_SDA0

PERST_PCIe_SWITCH-

EE_SK-PEX8604A

EE_CS-PEX8604A

EE_DI-PEX8604A

STRAP_UPCFG_TIMER_EN-



STRAP_NT_ENABLE-



STRAP_NT_P2P_EN-

STRAP_PORTCFG0

STRAP_PORTCFG1

EE_DO-PEX8604A

-PE_RST1[4,24]

+1.0V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

VCC2_5_PCIe

+3.3V

+3.3V

+3.3V+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+1.0V

+1.0VVCC2_5_PCIe

VCC2_5_PCIe+2.5V

Title


Date: Sheet of


COMBED2

PEX8604 Strapping


AC

Title


Date: Sheet of


COMBED2

PEX8604 Strapping


AC

Title


Date: Sheet of


COMBED2

PEX8604 Strapping


AC

/8608PEX 8604

STRAP_RESERVED17-Note: Hi: PCIe Gen2

Low: PCIe Gen1

*:

AT25128B-SSHL-T

VIA ConfidentialC280

0.01uF

C280

0.01uF

TP_PEX_LANE_GD1-TP_PEX_LANE_GD1-1

C252

1uF

C252

1uF

R309 0R309 0


C301

1000pF

C301

1000pF

TP_PEX_NT_RESET-TP_PEX_NT_RESET- 1

PEX 8604

U24B

PEX8604-BA50BC G

PEX 8604

U24B

PEX8604-BA50BC G

VS

SM

11V

SS

M10

VS

SM

9V

SS

M6

VS

SM

5V

SS

K10

VS

SK

9V

SS

K8

VS

SK

6V

SS

K5

VS

SK

7

VS

SJ1

0V

SS

J9V

SS

J8V

SS

J7V

SS

J6V

SS

J5V

SS

H10

VS

SH

9V

SS

H8

VS

SH

7V

SS

H6

VS

SH

5V

SS

H3

VS

SG

10V

SS

G9

VS

SG

8V

SS

G7

VS

SG

6V

SS

G5

VS

SF

10V

SS

F9

VS

SF

8V

SS

F7

VS

SF

6V

SS

F5

VS

SE

10V

SS

E9

VS

SE

8V

SS

E7

VS

SE

6V

SS

E5

VS

SC

10V

SS

C9

VS

SC

6V

SS

C5

VD

D25

D4

VD

D25

D11

VD

D25

L4

VD

D25

L11

VD

D25

AC

8

VD

D25

AG

3

VD

D25

AG

12

VD

D25

AM

7

VD

D10

D5

VD

D10

D6

VD

D10

D9

VD

D10

D10

VD

D10

E4

VD

D10

E11

VD

D10

G4

VD

D10

G11

VD

D10

H4

VD

D10

H11

VD

D10

K4

VD

D10

K11

VD

D10

L5

VD

D10

L6

VD

D10

L9

VD

D10

AD

7

VD

D10

AD

8

VD

D10

AL7

VD

D10

AL8

PEX_PERST#H13

PEX_NT_RESET#L13

JTAG_TRST#C13

JTAG_TCKE13

JTAG_TMSD14

JTAG_TDID12

JTAG_TDOE12

EE_SKJ14

EE_CSJ13

EE_DIK14

EE_DOH14

STRAP_PORTCFG0A1

STRAP_PORTCFG1B2

STRAP_UPSTRM_PORTSEL0F3

STRAP_UPSTRM_PORTSEL1F1

STRAP_UPSTRM_PORTSEL2H2

STRAP_UPSTRM_PORTSEL3G2

STRAP_NT_ENABLE#H12

STRAP_NT_UPSTRM_PORTSEL0J3

STRAP_NT_UPSTRM_PORTSEL1J2

STRAP_NT_UPSTRM_PORTSEL2K3

STRAP_NT_UPSTRM_PORTSEL3M3

STRAP_SERDES_MODE_EN#C4

STRAP_PROBE_MODE#K13

STRAP_DEBUG_SEL0J11

STRAP_FAST_BRINGUP#C3

STRAP_RESERVED17#F4

STRAP_PLL_BYPASS#M12

STRAP_SSC_ISO_ENABLE#M4

STRAP_TESTMODE0P13

STRAP_TESTMODE1N14

STRAP_TESTMODE2M14

STRAP_TESTMODE3N13

I2C_ADDR0G13

I2C_ADDR1F11

I2C_ADDR2G14

I2C_SCL0F14

I2C_SDA0F12

I2C_SCL1F13

I2C_SDA1E14

STRAP_RESERVED16 D13

N/C N1

PEX_INTA# J12

FATAL_ERR# B13

THERMAL_DIODEp A13

THERMAL_DIODEn C12

SHPC_INT# C14

PEX_LANE_GOOD0# P14

PEX_LANE_GOOD1# M13

N/C L14

N/C L12

PEX_LANE_GOOD4# B1

PEX_LANE_GOOD5# B14

N/C A14

N/C C2

VD

D10

L10

GPIO0 D2

GPIO1 D1

GPIO2 E3

GPIO3 E2

GPIO4 E1

GPIO5 F2

GPIO6 J4

GPIO7 J1

GPIO8 H1

GPIO9 K1

GPIO10 M1

GPIO11 P2

GPIO12 P1

GPIO13 L3

GPIO14 M2

GPIO15 N2

GPIO16 K12

GPIO29 D3

GPIO30 A2

STRAP_SPARE0# K2

STRAP_SPARE1# L2

STRAP_NT_P2P_EN# G1

STRAP_UPCFG_TIMER_EN# C1

STRAP_SMBUS_EN# L1

VS

SC

11

R30210K/XR30210K/X


R291 5.1KR291 5.1K

R276 5.1KR276 5.1K

R307 10KR307 10K

C262

1000pF

C262

1000pF

R320 1KR320 1K

C256

0.1uF

C256

0.1uF

R289 5.1KR289 5.1K

C303

1uF

C303

1uF


R279 0/XR279 0/X

R317 0/XR317 0/X

C269

0.01uF

C269

0.01uFC3220.1uFC3220.1uF

R332 5.1K/XR332 5.1K/X

R312 5.1KR312 5.1K

C289

1000pF

C289

1000pF

R303 0R303 0

R299 0/XR299 0/X

R287390R287390

C277

0.1uF

C277

0.1uF

C275

1uF

C275

1uF

C304

1uF

C304

1uF

R273 5.1KR273 5.1K

C293

1000pF

C293

1000pF

R311 2.26K_1%R311 2.26K_1%

U22

AT25128B-SSHL-T/X

U22

AT25128B-SSHL-T/X

CE#1

SO2

WP#3

VSS4 SI 5SCK 6

HOLD# 7VDD 8

R292 0/XR292 0/X

R316 1KR316 1K

R284 5.1KR284 5.1K

C291

1000pF

C291

1000pF

C278

1uF

C278

1uF

C254

0.1uF

C254

0.1uF

R323 5.1KR323 5.1K

C264

1uF

C264

1uF

+

CE46470uF/16V

+

CE46470uF/16V

12

R314 0R314 0

R329 0R329 0

R27210K/XR27210K/X

C276

1000pF

C276

1000pF

R282 5.1KR282 5.1K

R298 5.1KR298 5.1K

C282

1uF

C282

1uF

R290 5.1KR290 5.1K

R321 1.5KR321 1.5K

R277 5.1KR277 5.1K

C307

1uF

C307

1uF

R275 5.1KR275 5.1K

TP_JTAG_TDOTP_JTAG_TDO 1

C267

1000pF

C267

1000pF

R308 2.26K_1%R308 2.26K_1%

R296 5.1KR296 5.1K

R333 1.5KR333 1.5K

R293 5.1KR293 5.1K

C292

1000pF

C292

1000pF

C281

0.01uF

C281

0.01uF

R322 0/XR322 0/XC300

0.1uF

C300

0.1uF

C295

1000pF

C295

1000pF

R288 5.1KR288 5.1K

R310 5.1KR310 5.1K

R313 0R313 0

R328 5.1K/XR328 5.1K/X

C266

1000pF

C266

1000pF

R294 0/XR294 0/X

U25

NC7SZ08M5X_NL

U25

NC7SZ08M5X_NL

12

43

5

R283 5.1KR283 5.1K

C249

22uF

C249

22uF

R297 5.1KR297 5.1K

C294

0.1uF

C294

0.1uF

R318 5.1KR318 5.1K

C257

1000pF

C257

1000pF

R325 5.1KR325 5.1K

R295 0/XR295 0/X

C286

1000pF

C286

1000pF

C265

0.01uF

C265

0.01uF

C250

22uF

C250

22uF

R331 5.1KR331 5.1K

R3015.1K/XR3015.1K/X

R306 0/XR306 0/X

R278 5.1KR278 5.1K

R315 10KR315 10K

C263

1000pF

C263

1000pF

C302

1uF

C302

1uF

R285 5.1KR285 5.1K

C251

0.1uF

C251

0.1uF

C290

0.01uF

C290

0.01uF

R324 1KR324 1K

R326 0R326 0


C253

1000pF

C253

1000pF

R327 5.1KR327 5.1K

R300 5.1KR300 5.1K

R334390R334390

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-PE1PRT2_2-PE1PRT2_2

-PE_RST1-PE_WAKE

SMB_DATSMB_CLK

-PE1PRT2_2

USB_MEDT6+

USB_ME_T6-

USB_ME_T6+


-CLKR

USB_MEDT6-

PCIE_TX1+PCIE_TX1-

PCIE_TX4+PCIE_TX4-

PCIE_TX5+PCIE_TX5-

SMB_CLK[4,12,15,25]SMB_DAT[4,12,15,25]


-PE_RST1 [4,23]-PE_WAKE[4,25]

PCIE_RX1+ [22]

PCIE_CLK1- [12]

PCIE_RX1- [22]

PCIE_CLK1+ [12]

-PE_RST0 [4,25]

SMB_CLK [4,12,15,25]SMB_DAT [4,12,15,25]

PCIE_RX5-[22]PCIE_RX5+[22]

PEX_PETn5[22]PEX_PETp5[22]

PCIE_CLK5-[12]PCIE_CLK5+[12]

-PE_WAKE[4,25]

-PEREQ_1[12]

-W_DISABLE [8]

USB_DT6+[4,16]USB_DT6-[4,16]

PEX_PETn4[22]PEX_PETp4[22]


PEX_PETp1[22]PEX_PETn1[22]

+3.3VSUS

+3.3V +12V_VCC

+12V_VCC

+3.3V+3.3V

+12V_VCC

+3.3VSUS

+12V_VCC

+3.3V+3.3V

+3.3VSUS

+12V_VCC+12V_VCC

+3.3V

+3.3V

+3.3VSUS

+1.5V

+3.3VSUS

+3.3VSUS

+3.3VSUS

+1.5V

+3.3VSUS

Title


Date: Sheet of


COMBED2

PCI Express x1 -2 & Express Card


AC

Title


Date: Sheet of


COMBED2



AC

Title


Date: Sheet of


COMBED2



AC

#2 PCIE X 1 SLOT#1 PCIE X 1 SLOT

VIA Confidential

Mini PCIE Socket

C308 0.1uFC308 0.1uF

TP6TP61

+CE47 470uF/16V+CE47 470uF/16V1 2

C283 0.1uFC283 0.1uF

+CE49 100uF+CE49 100uF1 2

C298 0.1uFC298 0.1uF

+CE45 100uF+CE45 100uF1 2

C296 0.1uFC296 0.1uF

JP_USBME_SEL

2213S-04G-F2

JP_USBME_SEL

2213S-04G-F2

13 4

2

TP4TP41

+CE44 100uF+CE44 100uF1 2

Mechanical Key

PCI_Express_x1


PE2

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE2

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

TP7TP71

TP3TP31

C258 0.1uFC258 0.1uF

MINICARD CONN

MINI_PCIE

0710A0BA68B

MINICARD CONN

MINI_PCIE

0710A0BA68B

+3.3VAUX 52

GND 50

+1.5V 48

LED_WPAN# 46

LED_WLAN# 44

LED_WWAN# 42

GND 40

USB_D+ 38

USB_D- 36

GND 34

SMB_DATA 32

SMB_CLK 30

+1.5V 28

GND 26

+3.3VAUX 24

PERST# 22

W_DISABLE# 20

GND 18

UIM_VPP 16

UIM_RESET 14

UIM_CLK 12

UIM_DATA 10

UIM_PWR 8

+1.5V 6

GND 4

+3.3VAUX 2WAKE#1

Reserved51

Reserved49

Reserved47

Reserved45

GND43

+3.3VAUX41

+3.3VAUX39

GND37

GND35

PETp033

PETn031

GND29

GND27

PERp025

PERn023

GND21

Reserved(UIM_C4)19

Reserved(UIM_C8)17

GND15

REFCLK+13

REFCLK-11

GND9

CLKREQ#7

COEX25

COEX13

G1

G2

M1

M2

C309 0.1uFC309 0.1uF

TP5TP51

R305 2.2KR305 2.2K

C313 4.7uFC313 4.7uF

C315 0.1uFC315 0.1uF

C312 4.7uFC312 4.7uF

L44ACM2012-900-2P-T002L44ACM2012-900-2P-T002

1 4

32

C314 0.1uFC314 0.1uF

C311 4.7uFC311 4.7uF

C316 0.1uFC316 0.1uF

Mechanical Key

PCI_Express_x1


PE1

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE1

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

C299 0.1uFC299 0.1uF

+CE48 100uF+CE48 100uF1 2

C297 0.1uFC297 0.1uF

C285 0.1uFC285 0.1uF

C310 0.1uFC310 0.1uF

C259 0.1uFC259 0.1uF

D35

RB751V-40/X

D35

RB751V-40/X

A K

C284 0.1uFC284 0.1uF

JP_USBME_SEL(3-4)/X

MINI-JUMPER

JP_USBME_SEL(3-4)/X

MINI-JUMPER

+CE43 470uF/16V+CE43 470uF/16V1 2

JP_USBME_SEL(1-2)/X

MINI-JUMPER

JP_USBME_SEL(1-2)/X

MINI-JUMPER

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

PSN2_1

PSN2_2

PEG_TX0+[5]PEG_TX0-[5]




PEG_RX0+ [5]PEG_RX0- [5]




SMB_CLK[4,12,15,24]SMB_DAT[4,12,15,24]

-PE_WAKE[4,24]


-PE_RST0 [4,24]

+3.3V

+12V_VCC

+3.3VSUS

+3.3V

+3.3V

+12V_VCC+12V_VCC

+3.3V +3.3V

+3.3VSUS

+3.3V

+3.3V

Title


Date: Sheet of


COMBED2

PCI Express x16


AC

Title


Date: Sheet of


COMBED2

PCI Express x16


AC

Title


Date: Sheet of


COMBED2

PCI Express x16


AC

PCI Express x16, +12V 300mil width.


VIA Confidential

PCIE X 16

C246 0.1uFC246 0.1uF

R265 0R265 0

R270 2.2KR270 2.2K

Mechanical Key

PCI_Express_x16





PE16

WPES-164AN41B22UWS

Mechanical Key

PCI_Express_x16





PE16

WPES-164AN41B22UWS

+12VB1

+12VB2

+12VB3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#1B17

GNDB18

PRSNT1# A1

+12V A2

+12V A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V A9

+3.3V A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

PETP1B19

PETN1B20

GNDB21

GNDB22

PETP2B23

PETN2B24

GNDB25

GNDB26

PETP3B27

PETN3B28

GNDB29

RSVD3B30

PRSNT2#2B31

GNDB32

RSVD5 A19

GND A20

PERP1 A21

PERN1 A22

GND A23

GND A24

PERP2 A25

PERN2 A26

GND A27

GND A28

PERP3 A29

PERN3 A30

GND A31

RSVD6 A32

PETP4B33

PETN4B34

GNDB35

GNDB36

PETP5B37

PETN5B38

GNDB39

GNDB40

PETP6B41

PETN6B42

GNDB43

GNDB44

PETP7B45

PETN7B46

GNDB47

PRSNT2#3B48

GNDB49

RSVD7 A33

GND A34

PERP4 A35

PERN4 A36

GND A37

GND A38

PERP5 A39

PERN5 A40

GND A41

GND A42

PERP6 A43

PERN6 A44

GND A45

GND A46

PERP7 A47

PERN7 A48

GND A49

PETP8B50

PETN8B51

GNDB52

GNDB53

PETP9B54

PETN9B55

GNDB56

GNDB57

PETP10B58

PETN10B59

GNDB60

GNDB61

PETP11B62

PETN11B63

GNDB64

GNDB65

PETP12B66

PETN12B67

GNDB68

GNDB69

PETP13B70

PETN13B71

GNDB72

GNDB73

PETP14B74

PETN14B75

GNDB76

GNDB77

PETP15B78

PETN15B79

GNDB80

PRSNT2#4B81

RSVD4B82

RSVD8 A50

GND A51

PERP8 A52

PERN8 A53

GND A54

GND A55

PERP9 A56

PERN9 A57

GND A58

GND A59

PERP10 A60

PERN10 A61

GND A62

GND A63

PERP11 A64

PERN11 A65

GND A66

GND A67

PERP12 A68

PERN12 A69

GND A70

GND A71

PERP13 A72

PERN13 A73

GND A74

GND A75

PERP14 A76

PERN14 A77

GND A78

GND A79

PERP15 A80

PERN15 A81

GND A82

+CE41 100uF+CE41 100uF1 2

R268 0R268 0

+CE40 100uF+CE40 100uF1 2

+CE39 470uF/16V+CE39 470uF/16V1 2

R2664.7KR2664.7K

R264 4.7KR264 4.7K

+CE38 470uF/16V+CE38 470uF/16V1 2

R271 2.2KR271 2.2K

R269 4.7KR269 4.7K

C248 0.1uFC248 0.1uF

R2674.7KR2674.7K

+CE50 100uF+CE50 100uF1 2

C247 0.1uFC247 0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DVP1_TVCLKR

DVP1_VDD_EN[5]

DVP1_TVFLD [5]

DVP1_SPD [5]DVP1_SPCLK [5]

DVP_SPDIF_HDMI [6]

-SLOT_RST[13]

DVP1_HS [5]DVP1_VS [5]

DVP1_TVCLKR [5]

DVP1_D2 [5]DVP1_D3 [5]

DVP1_D6 [5]DVP1_D7 [5]

DVP1_D9 [5]

DVP1_D12 [5]DVP1_D13 [5]

DVP1_CLK [5]

DVP1_DE [5]

DVP1_BKLT_EN[5]

DVP1_D0[5]DVP1_D1[5]


DVP1_D8[5]

DVP1_D10[5]DVP1_D11[5]

DVP1_D14[5]DVP1_D15[5]

BLT_CK[4,5,14]

+5V+3.3V

+5V

+3.3V

+5V +3.3V

Title


Date: Sheet of


COMBED2

DVP SLOT


AC

Title


Date: Sheet of


COMBED2

DVP SLOT


AC

Title


Date: Sheet of


COMBED2

DVP SLOT


AC

DVP SLOT

10V 080510V 0805

VIA ConfidentialPlug detection from DVP2-3*

TTL/TV from DVP

DVP1TVCLKR function selectionTV_DVP_SEL

1-2

+CE54 470uF/16V+CE54 470uF/16V1 2

TV_DVP_SEL

HEADER_1X3

TV_DVP_SEL

HEADER_1X3

21

3

R3544.7KR3544.7K

C331 10uFC331 10uF C330 10uFC330 10uF

TV_DVP_SEL(2-3)

MINI-JUMPER

TV_DVP_SEL(2-3)

MINI-JUMPER

+CE53 470uF/16V+CE53 470uF/16V1 2Mechanical Key

PCI_Express_x4



DVP_SLOT

EE03200S-CP3

Mechanical Key

PCI_Express_x4



DVP_SLOT

EE03200S-CP3

+5V B1+5V B2NC B3

GND B4SPCLK1 B5

SPD1 B6GND B7

+3.3V B8TVFLD B9+3.3V B10

DE B11

CLOCK B12GND B13D13 B14D12 B15

GND B16D9 B17

GND B18

RST#A1+5VA2+5VA3GNDA4NCA5TS1ERRA6VCP1VSYNCA7VCP1HSYNCA8+3.3VA9+3.3VA10INTA11

GNDA12D15A13D14A14GNDA15D11A16D10A17GNDA18

D7 B19D6 B20

GND B21GND B22

D3 B23D2 B24

GND B25GND B26

VSYNC B27HSYNC B28

GND B29DET/TVCLKR B30

TVCLKR B31GND B32

D8A19GNDA20D5A21D4A22GNDA23GNDA24D1A25D0A26GNDA27GNDA28ENBLTA29ENVDDA30GNDA31NCA32

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PSON

PW_OK

PWR_OK

TYPE1_2

TYPE0_

Q5_B

SUSB_PASS

SUSBSUSB

SUSB

EN_3S

PWR_OK [4]

-TYPE2[5]

-TYPE1[5]

-TYPE0[5]

-SUSB[4]

-SUSB [4]

+5V

+5VSUS

+3.3V

+12V_VCC

-12V +5V

+5V

+3.3VBAT

+5VSUS

+12V_VCC

+5VDUAL+5VSUS

+5V

+5VSUS

+5VSUS+3.3VSUS

+12V +12V_VCC +12V_VCC+12V

+12V

+5VSUS+5VSUS

+5VSUS

+12V_VCC+12V+5VSUS

+5VSUS

+3.3VSUS

Title


Date: Sheet of


COMBED227 29Wednesday, July 31, 2013

AC

ATX POWERTitle


Date: Sheet of



AC

ATX POWERTitle


Date: Sheet of



AC

ATX POWER

ATX POWER

VCC_RTC

ENABLE

NORMAL

FUNCTION

2 - 3

1 - 2

CLEAR_CMOS +3.3VSUS+5VDUAL

*

VIA Confidential

Discharge Circuit

0

10

S4/S5

S111 S3

Pstate-SUSC0

-SUSB

Iout Max = 2A

Vout = 0.8 * (1+R2/R1)


3.3V 2A~

R1

R2


Adjust this R-C todelay +3.3VSUS tosync VSUSVDDsequence

VCC

GND

U17A

74HCT08D/X

VCC

GND

U17A

74HCT08D/X

1

23

147

TP_+5VSUSTP_+5VSUS

1

C3190.1uFC3190.1uF

AUX12VAUX12V4

32

1

D10

SSM5817PT

D10

SSM5817PT

A K

R68 1KR68 1K

C19010uFC19010uF

+

CE91000uF/10V

+

CE91000uF/10V

12

R12022R12022

+

CE12470uF/16V

+

CE12470uF/16V

12

C780.1uFC780.1uF

R3373.32K_1%R3373.32K_1%


1

+

CE111000uF/16V

+

CE111000uF/16V

12

R11922R11922

C1800.1uFC1800.1uF

JP4

OpenPad-1x2.5

JP4

OpenPad-1x2.5

1 2

C1170.1uFC1170.1uF

BATAAA-BAT-014-K01BATAAA-BAT-014-K01

12

C9010uFC9010uF

R1621KR1621K

Q152N7002Q152N7002

G

DS

R67200_1%R67200_1%

ATXPWR

ATP12120-F0D8H

ATXPWR

ATP12120-F0D8H

3V3-113

-12V14

GND15

PS-ON16

GND17

GND18

GND19

-5V20

5V121

5V222

3V3-2 1

3V3-3 2

GND 3

5V4 4

GND 5

5V5 6

GND 7

PW-OK 8

5VSB 9

12V1 10

5V323

GND2412V2 11

3V3-4 12

TP_+5VDUALTP_+5VDUAL

1

JP3

OpenPad-1x2.5

JP3

OpenPad-1x2.5

1 2

R76 1KR76 1K

C1560.1uFC1560.1uF

C810.1uFC810.1uF

C1280.1uFC1280.1uF

C1990.1uFC1990.1uF

TP_+12VTP_+12V

1

+

CE41000uF/10V

+

CE41000uF/10V

12

R1334.7KR1334.7K

TP_+5VTP_+5V

1

U26

UP0105PSW8

U26

UP0105PSW8

POK1

EN2

VIN3

CNTL4 NC 5

VOUT 6

FB 7

GND 8

PG

ND

G1

TP_+3_3VTP_+3_3V

1

R139 1KR139 1K

C32310uFC32310uF

R8410KR8410K

R1234.7K/XR1234.7K/X

R1434.7K/XR1434.7K/X

VCC

GND

U17C

74HCT08D/X

VCC

GND

U17C

74HCT08D/X

9

108

147

VCC

GND

U17B

74HCT08D/X

VCC

GND

U17B

74HCT08D/X

4

56

147

Q122N7002Q122N7002

G

DS

C3054.7uF_X5RC3054.7uF_X5R

C320 0.033uF/XC320 0.033uF/X

C1230.1uFC1230.1uF

C17610uFC17610uF

CLEAR_CMOS(1-2)

MINI-JUMPER

CLEAR_CMOS(1-2)

MINI-JUMPER

Q10

AP4800AGM

Q10

AP4800AGM

S11

S22

S33

G4 D4 5D3 6D2 7D1 8

R711KR711K

C3061uFC3061uF

Q172N7002Q172N7002G

DS

JP2

OpenPad-1x2.5

JP2

OpenPad-1x2.5

1 2


1

R1583.48K_1%R1583.48K_1%

Q162N7002Q162N7002G

DS

C32110uFC32110uF

+

CE241000uF/16V

+

CE241000uF/16V

12

R69 0 /XR69 0 /X

JP1

OpenPad-1x2.5

JP1

OpenPad-1x2.5

1 2

BATA

BAT_3V

BATA

BAT_3V

1 2

R121100KR121100K

R70470_1%R70470_1%

R338 10.7K_1%R338 10.7K_1% TP_+3_3VSUSTP_+3_3VSUS

1

R1566.65K_1%R1566.65K_1%

D12BAT54CD12BAT54C

1

23

+

CE10470uF/16V+

CE10470uF/16V1

2


21

3

R83 10KR83 10K

R641KR641K

C19810uFC19810uF

Q192N7002Q192N7002G

DS

R141100K/XR141100K/X

R135 0R135 0

R336 1KR336 1K

R1324.7K/XR1324.7K/X


B

EC

TP_-12VTP_-12V

1

R1304.7K/XR1304.7K/X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.0V_FB

1.0V_PHASE

1.0V_OCSET

1.5V_FB

1.5V_PHASE

1.5V_UGATE

1.5V_LGATE

1.5V_OCSET

1.0V_UGATE

1.0V_LGATE

1.5V_BOOT

1.0V_BOOT

+3.3V

+2.5V

+5V

+5V

+1.0V

+5V

+1.5V+5V

+5V

USB3_+5V

+12V_VCC

Title


Date: Sheet of


COMBD2

System Power


AC

Title


Date: Sheet of


COMBD2

System Power


AC

Title


Date: Sheet of


COMBD2

System Power


AC

VIA Confidential

Iout Max = 3A

+2.5V

10.8VR348

+= )

L45 MAX. 6.5A

+1.0VR346

------------(

10.8VR280

+= )

L43 MAX. 6.5A

+1.5VR281

------------(

+1.0V

+1.5V

For Mini-PCIe Slot +1.5V

For PEX8604 +1.0V

For SN75DP120 & PEX8604 +2.5V Vout =0.805( 1+(R626/R627 )5V= 0.805( 1+(40.2/7.68) )

USB3_+5V

USB3_+5V = +5.12VIout Max = 4A

For USB3 Connector +5V

U27

APL5913KAC-TRG

U27

APL5913KAC-TRG

GND 1FB 2

VOUT1 3VOUT2 4VIN5

VCNTL6

POK7

EN8

VIN

1G

1

C2701uFC2701uF

C3290.1uFC3290.1uF

R62641.2K_1%R62641.2K_1%

C3280.01uFC3280.01uF

R280100_1%R280100_1%

+

CE51100uF/6.3V

+

CE51100uF/6.3V

12

C33510uFC33510uF

R6277.68K_1%R6277.68K_1%

C274 0.1uFC274 0.1uF

+

CE52100uF/6.3V

+

CE52100uF/6.3V

12

C2880.1uFC2880.1uF

C34622uFC34622uF

C26810uFC26810uF


17 8

U36

FR9808SPGTR

U36

FR9808SPGTR

VIN1 SW1 2

SW2 3

BS

4G

ND

8

VCC7

FB 6

EN

5

GN

DG

1

C2720.01uFC2720.01uF

R352 20K_1%R352 20K_1%

R625 100KR625 100K

D36 RB551V-30D36 RB551V-30AK


17 8

C34722uFC34722uF

C3431uFC3431uF

R34424K_1%R34424K_1%

R34627_1%R34627_1%

TP_1_0VTP_1_0V

1

C3320.1uFC3320.1uF

C3240.1uFC3240.1uF

D34 RB551V-30D34 RB551V-30AK

TP_+2_5VTP_+2_5V

1

C326 30pFC326 30pF

U29

RT9202GS

U29

RT9202GS

PHASE8

OCSET7

FB6

VCC5

BOOT 1

UGATE 2

GND 3

LGATE 4

R348100_1%R348100_1%

R286 20K_1%R286 20K_1%

+

CE42100uF/6.3V

+

CE42100uF/6.3V

12

C2730.1uFC2730.1uF

L45WSRPG0603-4R7M-L

L45WSRPG0603-4R7M-L

C3480.1uFC3480.1uF

C334 0.1uFC334 0.1uF

R343 51K_1%R343 51K_1%

R28188.7_1%R28188.7_1%

C3180.1uFC3180.1uF

C344 0.1uFC344 0.1uF

L43WSRPG0603-4R7M-L

L43WSRPG0603-4R7M-L

U23

RT9202GS

U23

RT9202GS

PHASE8

OCSET7

FB6

VCC5

BOOT 1

UGATE 2

GND 3

LGATE 4


4

35 6

C3251uFC3251uF

L46

PCMB104E-4R7MS

4.7uHL46

PCMB104E-4R7MS

4.7uH

C2710.1uFC2710.1uF

TP_USB3_+5VTP_USB3_+5V

1

TP_1_5VTP_1_5V

1


4

35 6

C34522uFC34522uFR342 10KR342 10K

C3361uFC3361uF

C3271uFC3271uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+3.3V

+3.3V

AGND

+3.3V

+12V_VCC

AGND

Title


Date: Sheet of


COMBD2

Mounting Holes


AC

Title


Date: Sheet of


COMBD2

Mounting Holes


AC

Title


Date: Sheet of


COMBD2

Mounting Holes


AC

VIA Confidential

For EMI


FIDUCIAL MARK

FOR Mini-PCIE MODULE

MH2MTH4mm

MH2MTH4mm

1234 5

678

9

C18 0.1uFC18 0.1uF

C141 0.1uFC141 0.1uF

MH11MTH4mm

MH11MTH4mm

1234 5

678

9

C64 0.1uFC64 0.1uF

MH18MTH4mm

MH18MTH4mm

1234 5

678

9

C287 0.1uFC287 0.1uF

C109 0.1uFC109 0.1uF

6mm

2.7mm

MH6

MH6_2.7

6mm

2.7mm

MH6

MH6_2.71

MH16MTH4mm

MH16MTH4mm

1234 5

678

9

C111 0.1uFC111 0.1uF

MH12

N0204525A-B

MH12

N0204525A-B1

MH15

N0204525A-B

MH15

N0204525A-B1

C161 0.1uFC161 0.1uF

FID3

FIDUCIAL

FID3

FIDUCIAL

1

C14 0.1uFC14 0.1uF

MH9MTH4mm

MH9MTH4mm

1234 5

678

9

6mm

2.7mm

MH19

MH6_2.7

6mm

2.7mm

MH19

MH6_2.71

C142 0.1uFC142 0.1uF

6mm

2.7mm

MH4

MH6_2.7

6mm

2.7mm

MH4

MH6_2.71

C187 0.1uFC187 0.1uF

MH3MTH4mm

MH3MTH4mm

1234 5

678

9

C113 0.1uFC113 0.1uF

6mm

2.7mm

MH7

MH6_2.7

6mm

2.7mm

MH7

MH6_2.71C206 0.1uFC206 0.1uF

MH13

N0204525A-B

MH13

N0204525A-B1

FID2

FIDUCIAL

FID2

FIDUCIAL

1

MH17MTH4mm

MH17MTH4mm

1234 5

678

9

C121 0.1uFC121 0.1uF

C317 0.1uFC317 0.1uF

C43 0.1uFC43 0.1uF

C255 0.1uFC255 0.1uF

C145 0.1uFC145 0.1uF

C116 0.1uFC116 0.1uF

6mm

2.7mm

MH5

MH6_2.7

6mm

2.7mm

MH5

MH6_2.71

MH10MTH4mm

MH10MTH4mm

1234 5

678

9

6mm

2.7mm

MH8

MH6_2.7

6mm

2.7mm

MH8

MH6_2.71

FID1

FIDUCIAL

FID1

FIDUCIAL

1

MH1MTH4mm

MH1MTH4mm

1234 5

678

9

MH14

N0204525A-B

MH14

N0204525A-B1

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


COMEBD1

Block Diagram


A1C

Title


Date: Sheet of


COMEBD1

Block Diagram


A1C

Title


Date: Sheet of


COMEBD1

Block Diagram


A1C


ROW A-B ROW C-D

BIOS

LPC BUS

SIO

BIOS_DISABLE#

HDA LINK

HD Codec

Fintek F81865

VT1708S

SATA

4 X SATA

8 X USBUSB

5 X PCIE X 1PCIE

LVDSLVDS

IDE

IDE

PCI

PCI SLOT

PCIE X 16PCIE X 8

DVP Port

DVP SLOT

VIA Confidential

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


COMEBD1

COVER SHEET


A1C

Title


Date: Sheet of


COMEBD1

COVER SHEET


A1C

Title


Date: Sheet of


COMEBD1

COVER SHEET


A1C



Revision A

COMEDB1

TITLE

PRINTER PORT, BIOS, LPC HEADER

7

ATX Power Connector / Reset / OTHERS DC-DC Converters

16

8

2

9

18

COM1, COM2 PORTS

15

SHEETUSB 7/8 PORT

25

LPC DEBUG PORT, LED

LPCSIO F81865

26

Block Diagram

HD Codec (VT1708S) / F_Audio

COM3, COM4 PORTS

17

PCI-E / PCI CLOCK BUFFER

1

PS2 KB / MS, VGA CONNECTOR

10

14

3

11

20

27

Cover Sheet

12

214

IDE, CF CARD CONNECTOR

5

FPNL, DIO & MFX HEADER

19

22

6

TITLE SHEET

13

24

SATA, FAN CONNECTOR

PCI-E X16 SLOT

PCI SLOT 1 & 2

LVDS CONNECTOR

PCI SLOT 3

Impedance Trace / MOUNTING HOLES

VIA Confidential



USB 1/2, 3/4 & 5/6 PORTS

PCI-E X1 SLOT 1, 2, 3

PCI-E X1 SLOT 4, 5, 6

DVP SLOT

23

28

RJ45 & LAN LED

Audio Connectors

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SATA_GNDSATA_GND

CEM_5VSB

MDI0+[19]MDI0-[19]

MDI1+[19]MDI1-[19]

LAN_-SP100[19]



SATA2_TX-[11]SATA2_TX+[11]

-SUSC[16]SATA2_RX+[11]SATA2_RX-[11]

-SATA_LED[10]AZ_SYNC[5,14]-AZ_RST[5]

AZ_BITCLK[5,14]AZ_SDOUT[5]


PCIE_TX4-[22]PCIE_TX4+[22]COM_GPI0[16]

LPC_SERIRQ[7,14]

-PE_RST0[21,23]

USB_DT0+[17]USB_DT0-[17]-USB_OC2[17]



-USB_OC6[18]



COM_GPO2 [16]


COM_GPO1 [16]

-SYS_RESET [16]

-PE_RST1 [22]

USB_DT1- [17]USB_DT1+ [17]

-USB_OC0 [17]USB_DT3+ [17]USB_DT3- [17]

USB_DT5+ [17]USB_DT5- [17]-USB_OC4 [17]

USB_DT7- [18]USB_DT7+ [18]

SPKR [5,20]

AZ_SDIN0 [5]

SATA3_RX+ [11]SATA3_RX- [11]

SATA3_TX+ [11]SATA3_TX- [11]




-PW_BTN [7,16]SMB_CLK [8,16,21,22,23]SMB_DAT [8,16,21,22,23]

PCIE_TX2+[22]PCIE_TX2-[22]COM_GPI1[16]


COM_GPI2[16]PCIE_TX0+[21]PCIE_TX0-[21]


LVDS_A_CK+[15]LVDS_A_CK-[15]SPCLK1[15]SPD1[15]COM_GPI3[16]


COM_GPO0[16]

PCIE_RX0- [21]

PCIE_RX1+ [21]

VGA_HSYNC [9]

CRT_SPD [9]

LVDS_B3+ [15]

LVDS_B_CK- [15]

VGA_R [9]

LVDS_B2- [15]

LVDS_B0+ [15]

LVDS_B1+ [15]

VGA_G [9]

COM_GPO3 [16]

PCIE_RX0+ [21]

CRT_SPCLK [9]

LVDS_B_CK+ [15]

LVDS_BKLT_EN [15]

LVDS_B0- [15]

LVDS_B2+ [15]

VGA_B [9]

PCIE_RX1- [21]

PCIE_RX2- [22]

VGA_VSYNC [9]

PCIE_RX2+ [22]

LVDS_B3- [15]

LVDS_B1- [15]

PWR_OK [27]

LPC_33_CLK [8]

I2C_DAT [16]I2C_CLK [16]

-KB_RST[7]KB_A20G[7]

SATA_GND[11]

MDI3-[19]MDI3+[19]

LAN_-SP1000[19]MDI2-[19]MDI2+[19]

LAN_-ACT [19]

-CB_RESET [7]

-PE_WAKE [21,22,23]-WAKE1 [7]

-SMBALRT [7]

BLT_CK [4,15,24]

-WDT_OUT [7,16]

VDDTXRX_LAN[19]



-SPI_SS0 [14]

-BIOS_DIS0[14]

-BIOS_DIS1 [14]

+3.3VBAT

+5VSUS

+12V +12V

Title


Date: Sheet of


COMEDB1

COME_CONN(A-B)


A1C

Title


Date: Sheet of


COMEDB1

COME_CONN(A-B)


A1C

Title


Date: Sheet of


COMEDB1

COME_CONN(A-B)


A1C

VIA Confidential


A4

A9A10

A12A13

A15A16A17

A19A20

A22A23A24A25A26

A28A29A30

A32A33A34

A36A37A38A39A40

A42A43A44A45A46

A48

A50

A54A55A56

A58A59

B3B4B5B6B7B8B9B10

B12B13B14

B16B17

B19B20

B22B23B24B25B26B27

B30

B32B33B34

B36B37B38B39B40

B42B43B44B45B46B47

B49

B54B55B56B57B58B59

A61A62A63A64A65

A67A68A69

A71A72A73A74A75A76A77A78A79

A81A82A83A84A85A86A87A88A89

A93

B61B62B63B64B65B66

B68B69

B71B72B73B74B75B76B77B78B79

B81B82

B89

B91B92B93B94B95B96

B2A2A3

A5A6A7

B50

B67

B15

B83

A14

A91A92

A94A95

B97

B88

FB10 AA-600Y03102FB10 AA-600Y03102

J8A3-6318491-6J8A3-6318491-6

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313 14 14

1515 16 16

1717 18 18

1919 20 20

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535 36 36

3737 38 38

3939 40 40

4141 42 42

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757 58 58

5959 60 60

6161 62 62

6363 64 64

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979 80 80

8181 82 82

8383 84 84

8585 86 86

8787 88 88

8989 90 90

9191 92 92

9393 94 94

9595 96 96

9797 98 98

9999 100 100

101101 102 102

103103 104 104

105105 106 106

107107 108 108

109109 110 110

111111 112 112

113113 114 114

115115 116 116

117117 118 118

119119 120 120

M1

G1

J8B3-6318491-6J8B3-6318491-6

121121 122 122

123123 124 124

125125 126 126

127127 128 128

129129 130 130

131131 132 132

133133 134 134

135135 136 136

137137 138 138

139139 140 140

141141 142 142

143143 144 144

145145 146 146

147147 148 148

149149 150 150

151151 152 152

153153 154 154

155155 156 156

157157 158 158

159159 160 160

161161 162 162

163163 164 164

165165 166 166

167167 168 168

169169 170 170

171171 172 172

173173 174 174

175175 176 176

177177 178 178

179179 180 180

181181 182 182

183183 184 184

185185 186 186

187187 188 188

189189 190 190

191191 192 192

193193 194 194

195195 196 196

197197 198 198

199199 200 200

201201 202 202

203203 204 204

205205 206 206

207207 208 208

209209 210 210

211211 212 212

213213 214 214

215215 216 216

217217 218 218

219219 220 220

G2

M2

R288 0/0805R288 0/0805

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCI_M66EN

IDE_D7[10]IDE_D6[10]IDE_D3[10]IDE_D15[10]IDE_D8[10]IDE_D9[10]IDE_D2[10]IDE_D13[10]IDE_D1[10]

IDE_D14[10]IDE_IORDY[10]-IDE_IOR[10]

IDE_D5 [10]IDE_D10 [10]IDE_D11 [10]IDE_D12 [10]IDE_D4 [10]IDE_D0 [10]IDE_REQ [10]-IDE_IOW [10]-IDE_ACK [10]

IDE_IRQ14 [10]IDE_A0 [10]IDE_A1 [10]IDE_A2 [10]-IDE_CS1 [10]-IDE_CS3 [10]-IDE_RST [10]

-PCI_PME[7,25,26]-PCI_GNT2[25,26]-PCI_REQ2[25,26]

-PCI_REQ1[25]-PCI_GNT1[25]

-PCI_GNT0[25]

-PCI_REQ0[25]-PCI_RESET[26]PCI_AD0[25,26]PCI_AD2[25,26]PCI_AD4[25,26]PCI_AD6[25,26]PCI_AD8[25,26]PCI_AD10[25,26]PCI_AD12[25,26]

PCI_AD14[25,26]PCI_-CBE1[25,26]-PCI_PERR[25,26]

-PCI_DEVSEL[25,26]-PCI_IRDY[25,26]PCI_-CBE2[25,26]PCI_AD17[25,26]PCI_AD19[25,26]

PCI_AD21[25,26]PCI_AD23[25,26]PCI_-CBE3[25,26]PCI_AD25[25,26]PCI_AD27[25,26]PCI_AD29[25,26]PCI_AD31[25,26]-PCI_INT_A[24,25,26]-PCI_INT_B[25,26]

PEG_RX0+[23]PEG_RX0-[23]



PEG_TX2- [23]

PEG_TX1- [23]PEG_TX1+ [23]

PEG_TX0- [23]PEG_TX0+ [23]

PCI_33_CLK [8]

-PCI_INT_C [25,26]-PCI_INT_D [25,26]

PCI_AD30 [25,26]PCI_AD28 [25,26]PCI_AD26 [25,26]PCI_AD24 [25,26]

PCI_AD22 [25,26]PCI_AD20 [25,26]PCI_AD18 [25,26]PCI_AD16 [25,26]-PCI_FRAME [25,26]-PCI_TRDY [25,26]-PCI_STOP [25,26]-PCI_SERR [25,26]PCI_PAR [25,26]

PCI_AD15 [25,26]PCI_AD13 [25,26]PCI_AD11 [25,26]PCI_AD9 [25,26]PCI_-CBE0 [25,26]PCI_AD7 [25,26]PCI_AD5 [25,26]PCI_AD3 [25,26]PCI_AD1 [25,26]

-PCI_REQ3 [25]-PCI_GNT3 [25]


PEG_TX3- [23]

DVP1_D3 [24]DVP1_D1 [24]

DVP1_D7 [24]DVP1_D5 [24]

DVP1_D11 [24]DVP1_D9 [24]

DVP1_D15 [24]DVP1_D13 [24]

DVP1_CLK [24]

DVP1_BKLT_EN [24]DVP1_VDD_EN [24]

BLT_CK [3,15,24]

DVP1_DET [24]

-IDE_CBLID [10]DVP1_D0[24]DVP1_D2[24]

DVP1_D4[24]DVP1_D6[24]

DVP1_D8[24]DVP1_D10[24]

DVP1_D12[24]DVP1_D14[24]

DVP1_DE[24]DVP1_VS[24]

DVP1_HS[24]DVP1_TVFLD[24]

DISP_CLKO0[24]DISP_CLKI0[24]

DVP1_TVCLKR [24]





PEG_TX4+ [23]PEG_TX4- [23]

PEG_TX5+ [23]PEG_TX5- [23]

PEG_TX6+ [23]PEG_TX6- [23]

PEG_TX7+ [23]PEG_TX7- [23]

-TYPE2 [27]

-TYPE0[27]

-TYPE1[27]

+12V +12V

Title


Date: Sheet of


COMBED1

COME_CONN (C-D)


A1C

Title


Date: Sheet of


COMBED1

COME_CONN (C-D)


A1C

Title


Date: Sheet of


COMBED1

COME_CONN (C-D)


A1C


C2C3C4C5C6C7C8C9C10

C12C13C14C15C16C17C18C19C20

C22C23C24C25C26C27C28C29C30

C32C33C34

C36C37C38C39C40

C42C43C44C45C46C47C48C49C50

C52C53

C55C56

C58C59

D2D3D4D5D6D7D8D9D10

D12D13D14D15D16D17D18D19D20

D22D23D24D25D26D27D28D29D30

D32D33D34D35D36D37D38D39D40

D42D43D44D45D46D47

D50

D52D53

D55D56

D58D59

C61C62

C78C79

C81C82

C85C86

C88C89

C91C92

C94C95

C98C99

D61D62

D77D78D79

D81D82

D85D86

D88D89

D91

D94

D97D98D99

D101

D75

C65C66

C68C69

C71C72

C74C75

D65D66

D68D69

D71D72

D74

D57

C54

C57

VIA Confidential

J9B3-6318491-6J9B3-6318491-6

121121 122 122

123123 124 124

125125 126 126

127127 128 128

129129 130 130

131131 132 132

133133 134 134

135135 136 136

137137 138 138

139139 140 140

141141 142 142

143143 144 144

145145 146 146

147147 148 148

149149 150 150

151151 152 152

153153 154 154

155155 156 156

157157 158 158

159159 160 160

161161 162 162

163163 164 164

165165 166 166

167167 168 168

169169 170 170

171171 172 172

173173 174 174

175175 176 176

177177 178 178

179179 180 180

181181 182 182

183183 184 184

185185 186 186

187187 188 188

189189 190 190

191191 192 192

193193 194 194

195195 196 196

197197 198 198

199199 200 200

201201 202 202

203203 204 204

205205 206 206

207207 208 208

209209 210 210

211211 212 212

213213 214 214

215215 216 216

217217 218 218

219219 220 220

G2

M2

J9A3-6318491-6J9A3-6318491-6

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313 14 14

1515 16 16

1717 18 18

1919 20 20

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535 36 36

3737 38 38

3939 40 40

4141 42 42

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757 58 58

5959 60 60

6161 62 62

6363 64 64

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979 80 80

8181 82 82

8383 84 84

8585 86 86

8787 88 88

8989 90 90

9191 92 92

9393 94 94

9595 96 96

9797 98 98

9999 100 100

101101 102 102

103103 104 104

105105 106 106

107107 108 108

109109 110 110

111111 112 112

113113 114 114

115115 116 116

117117 118 118

119119 120 120

M1

G1

R101 4.7KR101 4.7K

R96 0R96 0

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

LINE-R

CD_R

SD_IN0

MIC2_FR_L

AFILT4

MIC2_FR_R

MIC1_LMIC1_R

LINE-L

JD2

CD_L

MIC2_FRR

BIT_CLK

FNT_IO_SENSE

PC_BEEP

MIC2_FRL


MIC2_VREFO

JDREF

DCVOL

LINE2_VREFO

U19_45U19_46

U19_43U19_44

U19_41U19_39

U19_35U19_36

MIC2_JD

LINE2_JD

LINE2_RLINE2_L

HP_OUT_R

FNT_DET

HP_OUT_L

JD1

PC_BEEP

MIC2_FR_LMIC2_FR_R

FNT_IO_SENSE

MIC2_VREFO

LINE2_VREFO

HP_OUT_L

HP_OUT_R

VREF_FILTER

VREF_FILTER

JDREF

DCVOL

LINE2_JD

MIC2_JD

LINE1_IN_R[6]

AZ_SDOUT[3]

LINE1_IN_L[6]

AZ_SDIN0[3]

AZ_BITCLK[3,14]-AZ_RST[3]

AZ_SYNC[3,14]

MIC1_VREFO_L [6]


SIDESURR_JD[6]CEN_JD[6]

FRONT_JD[6]LINE1_JD[6]MIC1_JD[6]SURR_JD[6]

SIDESURR_OUT_L [6]SIDESURR_OUT_R [6]




SPDIF-HDMI [24]

SPKR[3,20]


CD_IN_R[6]

MIC1_VREFO_R [6]

SPDIFO [6]

+3.3VSUS

+3.3V

VDD3_AUDIO

AGND

+5VSUS

AGND AGNDAGND

+12V_VCC+5VAUDIO

AGND

AVDD5 +5VAUDIO

VDD3_AUDIO

AGND

AGND

+12V_VCC

AGND

+5VAUDIO

AGND

+12V_VCC

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

Title


Date: Sheet of


COMEDB1

HD Audio VT1708A


A1C

Title


Date: Sheet of


COMEDB1

HD Audio VT1708A


A1C

Title


Date: Sheet of


COMEDB1

HD Audio VT1708A


A1C

FRONT AUDIO

HD Audio Codec

+5VAUDIO

Close to VT1708S

VIA Confidential

+CE35 220uF+CE35 220uF12

+

CE2710uF

+

CE2710uF

12

+

CE3710uF

+

CE3710uF

12

+CE23 10uF+CE23 10uF1 2

U18

VT1708B/S

U18

VT1708B/S

DVDD11

SENSEA(JD1)13 GPIO0/GPIO2 2

DVSS14

SDATA_OUT5

BIT_CLK6

DVSS27

SDATA_IN8

DVDD29

SYNC10

RESET11

PC_BEEP12

SENSEB(JD2)34

LINE2-L14

LINE2-R15

MIC2-L16

MIC2-R17

CD_L18

CD_GND19

CD_R20

MIC1-L21

MIC1-R22

LINE1-L23

LINE1-R24

AVDD1 25

AVSS1 26

LINE1-VREFO-R/MONO-OUT 37LINE2-VREFO 31

DCVOL 33

GPIO1/GPIO3 3

LINE1-VREFO-L 29

MIC2-VREFO 30

MIC1-VREFO-L 28

MIC1-VREFO-R 32

FRONT-OUT-L/LINE-OUT-L 35

FRONT-OUT-R/LINE-OUT-R 36

VREF 27

AVDD2 38

SURR-OUT-L/HP-OUT-L 39

SURR-OUT-R/HP-OUT-R 41

JDREF 40

AVSS2 42

CEN-OUT/GPIO0 43LEE-OUT/GPIO1 44

SIDESURR-OUT-R/NC 46SIDESURR-OUT-L/NC 45

SPDIFI/EAPD 47

SPDIFO 48+CE26 10uF+CE26 10uF12

C1910.1uF /XC1910.1uF /X

5VAUDIO5VAUDIO

1

R138 16R138 16

C1590.1uFC1590.1uF

R171 5.1K_1%R171 5.1K_1%

C168 1uFC168 1uF

D19

BAT54A

D19

BAT54A

1

23

+CE39 220uF+CE39 220uF12

R135 3.3KR135 3.3K

+CE25 10uF+CE25 10uF1 2

C155 0.1uF /XC155 0.1uF /X

+CE28 10uF+CE28 10uF12

C161 0.1uFC161 0.1uF

C1950.1uF /XC1950.1uF /X

R168 10K_1%R168 10K_1%

R18310KR18310K

C179 10pFC179 10pF

R169 5.1K_1%R169 5.1K_1%

C158 100pF/XC158 100pF/X

+CE12 10uF+CE12 10uF1 2

+

CE4010uF

+

CE4010uF

12

R13410KR13410K

+

CE4510uF /X

+

CE4510uF /X

12

R170 20K_1%R170 20K_1%

R164 33R164 33

C184100pFC184100pF

C156 0.1uFC156 0.1uF

C165 100pFC165 100pF

C1640.1uFC1640.1uF

R166 39.2K_1%R166 39.2K_1%

+CE15 10uF+CE15 10uF1 2

C1750.1uFC1750.1uF

FB30QT1608RL300LF

FB30QT1608RL300LF

R185 39.2K_1%R185 39.2K_1%

R144 3.3KR144 3.3K

R140 16R140 16

R181 22R181 22

FB36 EBM321611A520 /XFB36 EBM321611A520 /X



R137 16R137 16

C160 0.1uF/XC160 0.1uF/X

+CE24 10uF+CE24 10uF12

C1770.1uFC1770.1uF

C166 1uFC166 1uF

R174 5.1K_1%R174 5.1K_1%

FB15 0FB15 0

C157 10uF/XC157 10uF/X

R136 3.3KR136 3.3K

+CE34 10uF+CE34 10uF1 2

FB210FB210

+CE30 10uF+CE30 10uF12

+CE21 10uF+CE21 10uF12

C1860.1uFC1860.1uF

C180 22pFC180 22pF

D18

BAT54A

D18

BAT54A

1

23

+CE22 10uF+CE22 10uF1 2

R19010KR19010K

R139 16R139 16

C181 1uFC181 1uF

+

CE3810uF

+

CE3810uF

12

R165 33R165 33

R172 10K_1%R172 10K_1%

R2021KR2021K

C169 100pF/XC169 100pF/XR177 20K_1%R177 20K_1%

FB31 0FB31 0

R167 0 /XR167 0 /X

C167 2.2uFC167 2.2uF

FB16 0FB16 0

+CE36 10uF+CE36 10uF1 2R182 22R182 22

+CE20 10uF+CE20 10uF1 2



13 4

2

5 67

14

9 1011 1213

R133 3.3KR133 3.3K

+CE31 10uF+CE31 10uF12

FB32 0FB32 0

U20AMS1117-5.0 /XU20AMS1117-5.0 /X

V_INI

GN

DG

V_OUT O

FB33QT1608RL300LF

FB33QT1608RL300LF

+

CE2910uF

+

CE2910uF

12

C1760.1uFC1760.1uF

D20

SSM5817PT

D20

SSM5817PT

A K

+CE13 10uF+CE13 10uF1 2

R203 10KR203 10K

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

MIC1_RE_L [5]

MIC1_RE_R [5]

MIC1_VREFO_R [5]

FRONT_OUT_L [5]

FRONT_OUT_R [5]

MIC1_JD [5]

FRONT_JD [5]

LINE1_JD [5]

LINE1_IN_L [5]

LINE1_IN_R [5]

SPDIFO [5]

LFE_OUT [5]

CEN_OUT [5]

SURR_OUT_R [5]

SURR_OUT_L [5]

SIDESURR_OUT_R [5]

SIDESURR_OUT_L [5]

SIDESURR_JD [5]

SURR_JD [5]

CEN_JD [5]

CD_IN_R [5]


MIC1_VREFO_L [5]

+5V

AGND

AGND

AGND

AGND

AGND

AGND

AGND

Title


Date: Sheet of


COMEDB1

AUDIO CONNECTORS


A1C

Title


Date: Sheet of


COMEDB1

AUDIO CONNECTORS


A1C

Title


Date: Sheet of


COMEDB1

AUDIO CONNECTORS


A1C

MIC_IN

LINE1_IN

FRONT_OUT

CD_IN

SIDESURR_OUT

SURR_OUT

CENTER/LFE

SPDIF


GREY

BLACK

ORANGE

GREEN

PINK

BLUE

VIA Confidential

R141 3.3KR141 3.3K

C143100pFC143100pF

R148100KR148100K

R2734.7K/XR2734.7K/X


C145100pFC145100pF

R154 330R154 330

R132 3.3KR132 3.3K

C135100pFC135100pF

C139100pFC139100pF

C136100pFC136100pF

CD_IN

CD_IN_CONN

CD_IN

CD_IN_CONN

1234

C228 0.1uFC228 0.1uF

J1B

P21-110-0007

J1B

P21-110-0007

22232425

G3G4

C141100pFC141100pF


R152100KR152100K

C149100pFC149100pF

C138100pFC138100pF

C137100pFC137100pF

R150100KR150100K

R151 330R151 330





FB23 QT1608RL300LFFB23 QT1608RL300LFFB27 QT1608RL300LFFB27 QT1608RL300LF



FB19 QT1608RL300LFFB19 QT1608RL300LFFB25 QT1608RL300LFFB25 QT1608RL300LF

J1A

P21-110-0007

J1A

P21-110-0007

23451

G1G2

C150100pFC150100pF

J2C

P21-1A0-0007

J2C

P21-1A0-0007

32333435

G5

C142100pFC142100pF

J2A

P21-1A0-0007

J2A

P21-1A0-0007

23451

G1G2

R149 330R149 330

C134100pFC134100pF

J2B

P21-1A0-0007

J2B

P21-1A0-0007

22232425

G3G4

J1C

P21-110-0007

J1C

P21-110-0007

32333435

G5

SPDIF

C151803-5

SPDIF

C151803-5

123

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VIN2

-LRESET

VIN1

D2+_SYS

SIO_VREFVIN3

CASEOPEN

ATXPG_IN

VIN2

SIO_24_CLK

VIN1-OVT

VIN0

DIO_GPIO62DIO_GPIO63

AGND_D-

D2+_SYSDIO_GPIO54DIO_GPIO55DIO_GPIO56DIO_GPIO57DIO_GPIO50DIO_GPIO51DIO_GPIO52DIO_GPIO53

DIO_GPIO27DIO_GPIO26DIO_GPIO25

-PCI_PME

DIO_GPIO61DIO_GPIO60

-PLED

24_CLK SIO_24_CLK

RTC_VBAT

RTC_X1RTC_X2

RTC_X1

SIO_24_CLK

AGND_D-

SIO_VREF

SIO_TXD2

SIO_TXD1

SIO_-RTS2

SIO_-DTR1

SIO_-DTR2

SIO_-RTS1

IR_RX

IR_TX

IR_RXIR_TX

-LRESET

SIO_VREF

VIN3

VIN0

-RF_ON

-CF_DET

-KB_RST

-WDT_OUT

KB_A20G

-SMBALRT

ATXPG_IN-OVT

DIO_GPIO24

RTC_X2

DIO_GPIO54[16]DIO_GPIO55[16]

DIO_GPIO26 [16]

DIO_GPIO56[16]

DIO_GPIO25 [16]

LPC_AD1 [3,14,20]

LP_D3[14]LP_D2[14]LP_D1[14]LP_D0[14]

DIO_GPIO57[16]

LP_D7[14]LP_D6[14]LP_D5[14]

LP_D4[14]

DIO_GPIO24 [16]

LPC_AD0 [3,14,20]-LPC_FRAME [3,14,20]

LP_SLCT[14]

LPC_AD3 [3,14,20]

LP_PE[14]LP_BUSY[14]

-LP_ACK[14]

-LP_ERR[14]

-LP_SLIN[14]-LP_INIT[14]

-LP_AFD[14]-LP_STB[14]

DIO_GPIO50[16]

LPC_AD2 [3,14,20]DIO_GPIO51[16]DIO_GPIO52[16]DIO_GPIO53[16]

DIO_GPIO27 [16]

DIO_GPIO62[16]

DIO_GPIO60[16]DIO_GPIO61[16]

DIO_GPIO63 [16]

SIO_-RTS4 [13]SIO_-DTR4 [13]

SIO_-DTR3 [13]SIO_-RTS3 [13]

KB_A20G [3]-KB_RST [3]

KB_CLK [9]KB_DATA [9]MS_CLK [9]MS_DATA [9]

-PLED [16]FANIO2[11]FANPWM2[11]

SIO_33_CLK [8]

-LPC_DRQ0 [3]LPC_SERIRQ [3,14]

LPC_48_CLK[14]

SIO_-DCD1[12]SIO_-RI1[12]SIO_-CTS1[12]SIO_-DTR1[12]SIO_-RTS1[12]SIO_-DSR1[12]SIO_TXD1[12]SIO_RXD1[12]

SIO_-DCD2[12]SIO_-RI2[12]SIO_-CTS2[12]SIO_-DTR2[12]SIO_-RTS2[12]SIO_-DSR2[12]SIO_TXD2[12]SIO_RXD2[12]

SIO_-DCD3 [13]SIO_-RI3 [13]SIO_-CTS3 [13]

SIO_-DSR3 [13]SIO_TXD3 [13]SIO_RXD3 [13]SIO_-DCD4 [13]SIO_-RI4 [13]SIO_-CTS4 [13]

SIO_-DSR4 [13]SIO_TXD4 [13]SIO_RXD4 [13]

-CF_DET [10]

-PCI_RST1[14,24,26]

-CB_RESET[3]

-WDT_OUT [3,16]

-SMBALRT [3]

-RF_ON [17]

-WAKE1 [3]-PCI_PME [4,25,26]

-PW_BTN [3,16]

+3.3VSUS

+3.3VBAT

+3.3V

+3.3V

+3.3V

+3.3V

+5V

+12V_VCC

+3.3V+3.3V

+3.3VSUS

+3.3V

+3.3V

+3.3VBAT

+5V

-12V

+5VDUAL

+3.3VSUS

Title


Date: Sheet of


COMEDB1

F81865F


A1C

Title


Date: Sheet of


COMEDB1

F81865F


A1C

Title


Date: Sheet of


COMEDB1

F81865F


A1C

System Temperature

VIA Confidential

SMD

SIO_TXD2

SIO_TXD1

SIO_-RTS2

SIO_-RTS1

SIO_-DTR2

SIO_-DTR1 : On : FAN 100% Off : FAN 60%

On : SPI as a Primary BIOS Off : SPI as a Back up BIOS

On : IC2 5A Off : IC2 5C

On : DAC Off : PWM

On : Config 2E Off : Config 4E

On : SPI Enable Off : SPI DisableSIR

Rev: 2

R532MR532M

OSC1

24MHz

OSC1

24MHz

E/D1

GND2 OUT 3

VDD 4

R33 47K_1%R33 47K_1%

R66 0 /XR66 0 /X

R281 0R281 0

C4410pFC4410pF

C410.1uFC410.1uF

R29 560 /XR29 560 /X

X132

.768

KH

zX1

32.7

68K

Hz

12 3

4

C560.1uFC560.1uF

RN14 4.7K RN14 4.7K

12345678

RN124.7K RN124.7K

12

34

56

78

RT

C_V

BA

TR

TC

_VB

AT

1

SIR

SIR_Header

SIR

SIR_Header

1

345

SYS_SENSYS_SEN

21

3

R69 0/XR69 0/X

R39 47K_1%R39 47K_1%

R60 0R60 0

R11 0 /XR11 0 /X

C28 0.1uFC28 0.1uF

RN114.7K RN114.7K

12

34

56

78

R43 200K_1%R43 200K_1%

R22 1K /XR22 1K /X

C580.1uFC580.1uF

RN64.7K RN64.7K

12

34

56

78

R25 1KR25 1K

R49 10K_1% /XR49 10K_1% /X

R71 0R71 0

C390.1uFC390.1uF

Q3MMBT3904 /XQ3MMBT3904 /X

B

EC

R19 1KR19 1K

F81865

U8

F81865F-I (REV. LAC)

F81865

U8

F81865F-I (REV. LAC)

DC

D1#

1

RI1

#2

CT

S1

3

DT

R1#

4

RT

S1#

5

DS

R1#

6

SO

UT

17

SIN

18

DE

NS

EL#

/GP

IO50

9

MO

A#/

GP

IO51

10

DR

VA

#/G

PIO

5211

WD

AT

A#/

GP

IO53

/DC

D5#

12

DIR

#/G

PIO

54/R

I5#

13

ST

EP

#/G

PIO

55/C

TS

5#14

HD

SE

L#/G

PIO

56/D

TR

5#15

WG

AT

E#/

GP

IO57

/DS

R5#

16

RD

AT

A#/

GP

IO60

/DC

D4#

17

TR

K0#

/GP

IO61

/RI4

#18

IND

EX

#/G

PIO

62/C

TS

4#19

WP

T#/

GP

IO63

/DT

R4#

20

DS

KC

HG

#/G

PIO

64/D

SR

4#21

GN

D22

LRE

SE

T#

23

LDR

Q#

24

SE

RIR

Q25

LFR

AM

#26

LAD

027

LAD

128

LAD

229

LAD

330

VC

C31

PC

ICLK

32

CLK

IN33

KB

RS

T#

34

GA

2035

DC

D2#

/GP

IO30

36

RI2

#/G

PIO

3137

CT

S2#

/GP

IO32

38

KCLK 64

KDATA 63

MCLK 62

MDATA 61

VSB 60

GPIO07/RTS5# 59

GPIO06/SIN4/IRRX 58

GPIO05/SOUT4/IRTX 57

GPIO04/FWH_DIS/SPI_CSI# 56

GPIO03/SPI_MOSI 55

GPIO02/SPI_MISO 54

GPIO01/SPI_CS0# 53

GPIO00/SPI_CLK 52

SIN3/GPIO47 51

SOUT3/GPIO46 50

DSR3#/GPIO45 49

RTS3#/GPIO44 48

DTR3#/GPIO43 47

CTS3#/GPIO42 46

RI3#/GPIO41 45

DCD3#/GPIO40 44

SIN2#/GPIO37 43

SOUT2/GPIO36 42

DSR2#/GPIO35 41

RTS2#/GPIO34 40

DTR2#/GPIO33 39

SLC

T10

2

FA

NC

TL2

101

FA

NIN

210

0

FA

NC

TL1

99

FA

NIN

198

VC

C97

VIN

0(V

core

)96

VIN

195

VIN

294

VIN

393

VR

EF

92

D1+

(CP

U)

91

D2+

90

AG

ND

(D-)

89

RT

C_V

BA

T88

RT

X_X

287

RT

C_X

186

CO

PE

N#

85

VB

AT

84

RS

MR

ST

#/G

PIO

2783

PW

OK

/GP

IO26

82

PS

_ON

#/G

PIO

2581

S3#

/GP

IO24

80

PW

SO

UT

#/G

PIO

2379

PW

SIN

#/G

PIO

2278

AT

X P

G_I

N/G

PIO

2177

ALE

RT

#/G

PIO

2076

OV

T#

75

PM

E#

74

GN

D73

PE

CI/

GP

IO17

72

BE

EP

/GP

IO16

71

WD

TR

ST

#/G

PIO

1570

GP

IO14

/RT

S4#

69

GP

IO13

/SD

A/S

IN5

68

GP

IO12

/SC

L/S

OU

T5

67

GP

IO11

/LE

D_V

CC

66

GP

IO10

/LE

D_V

SB

65

PE103

BUSY104

ACK#105

SLIN#106

INIT#107

ERR#108

AFD#109

STB#110

PD0111

PD1112

PD2113

PD3114

PD4115

PD5116

PD6117

PD7118

VCC119

DCD0#120

RI0#121

CTS0#122

DTR0#123

RTS0#124

DSR0#125

SOUT0126

SIN0127

GND128

C343300pF /XC343300pF /X

R55 1M /XR55 1M /X

R63 22R63 22

R130 0/XR130 0/X

C4010pFC4010pF

R46 100K_1%R46 100K_1%

R37 560 /XR37 560 /X

C90.1uFC90.1uF

R34 200K_1%R34 200K_1%

R57 0/XR57 0/X

RN134.7K RN134.7K

12

34

56

78

R45 10K_1%R45 10K_1%

R40 200K_1%R40 200K_1%

RN104.7K RN104.7K

12

34

56

78

R42 20K_1%R42 20K_1%

R31 1K /XR31 1K /X

RN74.7K RN74.7K

12

34

56

78

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+3.3VCLK_BF PECLK0+PECLK0-

PECLK1+PECLK1-

PECLK2+PECLK2-

PECLK3+PECLK3-

PECLK4+PECLK4-

PCICLK1PCICLK2PCICLK3PCICLK4

PCICLK5

-CLK_PD

SRC_IN-SRC_IN

SDATASCLK

IREF


-HIGH_BW

OE_INV

-BYPASS

-SRC_DIV-SRC_STOP

PECLK6+PECLK6-

PCIE_CLK0+

PCIE_CLK0-

PCIE_CLK1+

PCIE_CLK1-

PCIE_CLK2+

PCIE_CLK2-

PCIE_CLK3+

PCIE_CLK3-

PCIE_CLK4+

PCIE_CLK4-

PCIE_CLK6+

PCIE_CLK6-

-BYPASS

-HIGH_BW

-SRC_DIV

OE_INV

-SRC_STOP

-CLK_PD

LPCCLK2LPCCLK1

LPCCLK4LPCCLK3

LPCCLK5

PCI_33_CLK1

PCI_33_CLK2

PCI_33_CLK3

LCLK_ROM2

LCLK_AK2001

LPC_HEADER

SIO_33_CLK







PCI_33_CLK[4]

PCI_33_CLK1 [25]PCI_33_CLK2 [25]

SMB_CLK[3,16,21,22,23]SMB_DAT[3,16,21,22,23]


LCLK_AK2001 [20]

LCLK_ROM2 [14]

LPC_33_CLK[3]

PCI_33_CLK3 [26]

SIO_33_CLK [7]

LPC_HEADER [14]

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

Title


Date: Sheet of


COMBED1



A1C

Title


Date: Sheet of


COMBED1



A1C

Title


Date: Sheet of


COMBED1



A1C

meet Zdif=49.9 ohm

PCI CLOCK

BUFFER

PCIE CLOCK

BUFFER

LPC CLOCK

BUFFER

VIA Confidential

R180 10K/XR180 10K/X

R213 51_1%R213 51_1%

R113 22R113 22

R229 10K/XR229 10K/X

R199 51_1%R199 51_1%

R175 475_1%R175 475_1%

R228 10K/XR228 10K/X

C1110.1uFC1110.1uF

R235 22R235 22

R201 22R201 22

R200 51_1%R200 51_1%

R112 22R112 22

C202 10pF/XC202 10pF/X

CKG_LOCKCKG_LOCK1

U19

ICS9DB801BGLF

U19

ICS9DB801BGLF

SCLK23

SDATA24

VDD12

VDD211

VDD319

GNDA 47

VDD539

SRC_IN4

DIF_0 8

DIF_0# 9

DIF_1 12

DIF_1# 13

DIF_2 16

DIF_2# 17

DIF_3 20

DIF_3# 21

DIF_4 30

DIF_4# 29

DIF_5 34

DIF_5# 33

SRC_IN#5

GND2 10

GND3 18

GND4 25

GND5 32

VDDA48

GND1 3

VDD431

DIF_6 38

DIF_6# 37

DIF_7 42

DIF_7# 41

OE_06

OE_114

OE_215

OE_37

OE_443

OE_535

OE_636

OE_744

OE_INV40

SRC_DIV#1

BYPASS#/PLL22

SRC_STOP#27

PD#26

HIGH_BW#28

IREF46

LOCK 45

R221 51_1%R221 51_1%

R217 51_1%R217 51_1%

C197 10pF/XC197 10pF/X

R222 22R222 22

R233 22R233 22

R179 10KR179 10K

R191 51_1%R191 51_1%

R205 10KR205 10K

R195 22R195 22

C20322pF/XC20322pF/X

C1900.1uFC1900.1uF

C19310uFC19310uF

R226 10K/XR226 10K/X

R204 10KR204 10K

R192 22R192 22

+

CE441000uF/10V

+

CE441000uF/10V

12

C106 10pF/XC106 10pF/X

R215 22R215 22

C1980.1uFC1980.1uF

R227 10KR227 10K

R208 22R208 22

R207 51_1%R207 51_1%

R187 10KR187 10K

R223 0R223 0

FB35 AA-600Y03102FB35 AA-600Y03102

C1740.1uFC1740.1uF

R194 10KR194 10KR209 10KR209 10K

R211 22R211 22

PCICLK3PCICLK31

R231 10K/XR231 10K/X

U21

CY23S05SXC-1

U21

CY23S05SXC-1

REF1

CLK2 2CLK1 3

GND4

CLKOUT 8

CLK4 7

VDD6

CLK3 5

U14

CY23S05SXC-1

U14

CY23S05SXC-1

REF1

CLK2 2CLK1 3

GND4

CLKOUT 8

CLK4 7

VDD6

CLK3 5

R225 10KR225 10K

R196 51_1%R196 51_1%

R198 22R198 22

R186 0R186 0

R206 10KR206 10K

C1820.1uFC1820.1uF

R219 22R219 22

R178 0R178 0

C199 10pF/XC199 10pF/X

R224 0R224 0

R232 10KR232 10K

PCICLK4PCICLK41

R210 51_1%R210 51_1%

R124 22R124 22

R220 51_1%R220 51_1%

R193 51_1%R193 51_1%

R216 51_1%R216 51_1%

C1830.1uFC1830.1uF

R214 22R214 22

C105 10pF/XC105 10pF/X

R188 10KR188 10K

C1730.1uFC1730.1uF

C107 10pF/XC107 10pF/X

LPCCLK2LPCCLK21

R176 10KR176 10KR197 22R197 22

R218 22R218 22R189 10KR189 10K

C12222pF/XC12222pF/X

R230 10KR230 10K

R173 10K/XR173 10K/X

C120 10pF/XC120 10pF/X

R234 22R234 22

R114 22R114 22

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

VCC_KB

KB_CK

CON_R

CON_G

VG

A_P

CON_VS

CON_B

CON_HS

MS_CK

KB_DT

KB_CK

MS_DT

MS_CK

KB_DT

MS_DT

V_SYNC

H_SYNC

CRTSPCLK

CRTSPD

VGA_PS

CRT_SPCLK [3]

CRT_SPD [3]VGA_G[3]

VGA_R[3]

VGA_B[3]

KB_DATA[7]

MS_DATA[7]

KB_CLK[7]

MS_CLK[7]

VGA_VSYNC[3]

VGA_HSYNC[3]

+5VDUAL

VCCE

+5VCRT

+3.3V

VCCE

+5VCRT

+3.3V

+3.3V

+5VCRT

+5VCRT

+5VCRT

+5V

Title


Date: Sheet of


COMBED1

KB/MS & VGA


A1C

Title


Date: Sheet of


COMBED1

KB/MS & VGA


A1C

Title


Date: Sheet of


COMBED1

KB/MS & VGA


A1C

KB / MS

2A


VGA

VIA Confidential

FB9QT2012RL600HC2ALFFB9QT2012RL600HC2ALF

R47 22R47 22

CB10.1uFCB10.1uF

R411.5KR411.5K

PS2-KBMSA

MH11061-P34-4F

PS2-KBMSA

MH11061-P34-4F

42

13

G1

G2

G35

6

D12

BAT54S

D12

BAT54S

2

3

1

D15BAT54SD15BAT54S

2

3

1

C6110pFC6110pF

Q82N7002Q82N7002

G

D SC5510pFC5510pF

D8BAT54SD8BAT54S

2

3

1

D11

BAT54S

D11

BAT54S

2

3

1

U6

NC7ST08M5X_NL

U6

NC7ST08M5X_NL

12

43

5

R731.5KR731.5KQ11

2N7002Q112N7002 G

D S


RN4D 4.7KRN4D 4.7K7 8

R67150_1%R67150_1%

D5

MSCD104

D5

MSCD104

A K

C6010pFC6010pF

PS11.1APS11.1A

1 2


R381.5KR381.5K

FB2 QT1608RL300LFFB2 QT1608RL300LFRN4B 4.7KRN4B 4.7K3 4

L8 CB-47CJ02101L8 CB-47CJ02101

C5410pFC5410pF

VGA_COM1B

C020388-2

VGA_COM1B

C020388-2

V6

G3

V1V7V2V8V3V9V4

V10

G4

V5

V11

V12

V13

V14

V15R62150_1%R62150_1%

RN4C 4.7KRN4C 4.7K5 6

U7

NC7ST08M5X_NL

U7

NC7ST08M5X_NL

12

43

5

C4710pFC4710pF

D4BAT54SD4BAT54S

2

3

1

C3312pFC3312pF

L1 CB-47CJ02101L1 CB-47CJ02101

C4610pFC4610pF

D10

BAT54S

D10

BAT54S

2

3

1

R28 22R28 22

D7BAT54SD7BAT54S

2

3

1

RN4A 4.7KRN4A 4.7K1 2

PS6

1.1A

PS6

1.1A

12

C4312pFC4312pF

FB1 QT2012RL600HC2ALFFB1 QT2012RL600HC2ALF


L7 CB-47CJ02101L7 CB-47CJ02101

PS2-KBMSB

MH11061-P34-4F

PS2-KBMSB

MH11061-P34-4F

108

79 11

12G4

G5

R841.5KR841.5K

C320.1uFC320.1uF

R56150_1%R56150_1%

CN1220pFCN1220pF

12

34

56

78

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

IDE_IRQ14

IDE_IORDY

-HD_LED

PRIMARY_28

IDE_REQ

IDE_D7

-IDE_CBLID

-HD_LED

IDE_D14

IDE_D12IDE_D11

IDE_D15

IDE_D8IDE_D9

IDE_D2

IDE_D0

IDE_D5 IDE_D10

IDE_D7IDE_D6

IDE_D1IDE_D13

IDE_D3IDE_D4

-IDE_ACK

IDE_D8IDE_D0

IDE_IORDY

IDE_D10

-IDE_CS1

IDE_IRQ14

-IDE_IOW

IDE_A0

IDE_D2IDE_D1

-IDE_CBLID

IDE_D3

IDE_D13

-IDE_IOR

IDE_REQIDE_A1

-HD_LED

-CD1_CF

IDE_D7

-CF_SEL

IDE_D9

IDE_A2

-IDE_RST

-IDE_CS3

IDE_D4

IDE_D15

IDE_D12

-CD2_CF

IDE_D14IDE_D6

IDE_D11

IDE_D5

-CF_DET

-CD2_CF

-CD1_CF

-CF_SEL

IDE_D[0:15][4]

-IDE_RST[4]

IDE_A2 [4]-IDE_CS3 [4]

IDE_REQ[4]-IDE_IOW[4]-IDE_IOR[4]IDE_IORDY[4]-IDE_ACK[4]IDE_IRQ14[4]IDE_A1[4]IDE_A0[4]

-IDE_CBLID [4]

-SATA_LED[3]

HD_LED [16]

-IDE_CS1[4]

-CF_DET [7]

+3.3V

+5V+5V

VCC_CF

VCC_CF

+3.3VVCC_CF

+5V

VCC_CF

VCC_CF

+5V +3.3V

VCC_CF

Title


Date: Sheet of


COMBED1

IDE & CF Card


A1C

Title


Date: Sheet of


COMBED1

IDE & CF Card


A1C

Title


Date: Sheet of


COMBED1

IDE & CF Card


A1C

IDE

CF Card

Active LowDetect CF Card

CF Card Detect

PIN 2-3:V_CF : Power Voltage SelectionDefault: Pin (1,2) Close

MS_CF_SEL1:PIN 1-2:

Lo -> MasterHi -> Slave : Default*

V_CF_SEL

+3.3V

+5V

1 - 2

2 - 3

CF VOLTAGESLAVE

MS_CF_SEL

MASTER

CF MASTER/SLAVE

2 - 3

1 - 2

VIA Confidential

R4410KR4410K


R103 0R103 0C66 0.1uFC66 0.1uF

R544.7KR544.7K

CF

0600000S35F

CF

0600000S35F

123

54

6789

10111213141516171819202122232425

26272829303132333435363738394041424344454647484950

G1

G2

G3

G4

G5

G6

M1

M2

C91 0.1uFC91 0.1uF

R74 10KR74 10KD3BAT54CD3BAT54C

1

23

R95 10K/XR95 10K/X

V_CF_SEL

HEADER_1X3

V_CF_SEL

HEADER_1X3

21

3

R94 10KR94 10K

R484.7KR484.7K


R1610KR1610K

Q72N7002PT

Q72N7002PTG

DS

R64 5.6K/XR64 5.6K/X R61 10K/XR61 10K/X

R65 470R65 470

IDE

IDE_CNTR_2X20

IDE

IDE_CNTR_2X20

13 4

2

5 67 89

111012

13 141615

17 1819

22242628303234

21232527293133

36384039

3735

MS_CF_SEL(1-2)

MINI-JUMPER

MS_CF_SEL(1-2)

MINI-JUMPERC63 0.1uFC63 0.1uF

R70 33R70 33

Q92N7002PTQ92N7002PTG

DSR32

100KR32100K

MS_CF_SEL

HEADER_1X3

MS_CF_SEL

HEADER_1X3

21

3

R3010KR3010K

R2410KR2410K

R72 4.7K/XR72 4.7K/X

C45 0.01uFC45 0.01uF

V_CF_SEL(1-2)

MINI-JUMPER

V_CF_SEL(1-2)

MINI-JUMPER

C67 0.1uFC67 0.1uF

R81 0/XR81 0/X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SATA_GNDSATA_GND

SATA_GND

OP+_IN

OP_OUT

FAN_PWRFAN_IO2

FAN_PWM2TR_BASE

SATA3_TX-[3]

SATA1_TX+[3]

SATA2_TX-[3]

SATA1_TX-[3]SATA0_TX-[3]

SATA2_TX+[3]

SATA0_TX+[3]

SATA3_TX+[3]


SATA3_RX+[3]SATA3_RX-[3]SATA2_RX-[3]

SATA2_RX+[3]


SATA_GND[3]

FANPWM2[7]

FANIO2 [7]

+3.3V

+3.3V

+12V_VCC+12V_VCC

Title


Date: Sheet of


COMBED1

SATA, FAN


A1C

Title


Date: Sheet of


COMBED1

SATA, FAN


A1C

Title


Date: Sheet of


COMBED1

SATA, FAN


A1C

SATA

FAN

CONNECTOR

6.3VSMD

16V SMD

VIA Confidential

R12 15KR12 15K

C5722pFC5722pF

R144.7KR144.7K

R81KR81K

SATA3

WATF-07DBN6SB1UW

SATA3

WATF-07DBN6SB1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

C74

22pF

C74

22pF

SATA1

WATF-07DBN6SB1UW

SATA1

WATF-07DBN6SB1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

R801KR801K

R7 470R7 470


B

CE

CT122uFCT122uF

C6210uFC6210uF

R21 47KR21 47K

SATA4

WATF-07DBN6SB1UW

SATA4

WATF-07DBN6SB1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

SATA2

WATF-07DBN6SB1UW

SATA2

WATF-07DBN6SB1UW

TX+2

TX-3

RX-5

RX+6

GND1

GND4

GND7

M1M1

M2M2

C59

10uF

C59

10uF

SYSFAN

FAN_CONN

SYSFAN

FAN_CONN

12

3

+

-

U3A

LM358DR

+

-

U3A

LM358DR

3

21

84

R680/XR680/X

R1815KR1815K

D14 RLS4148D14 RLS4148

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

COM_RI1COM_DTR1

COM_DSR1COM_DCD1

COM_RXD1

COM_CTS1COM_TXD1COM_RTS1

COM_RI1

COM_RTS1

COM_DTR1

COM_DSR1COM_DCD1

COM_CTS1COM_TXD1

COM_RXD1

COM_DCD2

COM_RI2

COM_CTS2

COM_DSR2

COM_RTS2COM_RXD2

COM_DTR2

COM_TXD2

COM_TXD2

COM_CTS2COM_DSR2


COM_RI2COM_RTS2

SIO_-DSR1[7]SIO_RXD1[7]SIO_-RTS1[7]SIO_TXD1[7]

SIO_-DCD1[7]

SIO_-CTS1[7]SIO_-DTR1[7]SIO_-RI1[7]

SIO_TXD2[7]

SIO_-DCD2[7]

SIO_-RI2[7]

SIO_RXD2[7]

SIO_-CTS2[7]

SIO_-RTS2[7]

SIO_-DTR2[7]

SIO_-DSR2[7]

-12V

+5V +12V_VCC

+12V_VCC+5V

-12V

Title


Date: Sheet of


COMEBD1

COM1,COM2


A1C

Title


Date: Sheet of


COMEBD1

COM1,COM2


A1C

Title


Date: Sheet of


COMEBD1

COM1,COM2


A1C

COM 1

COM 2

VIA Confidential

CN

4D22

0pF

CN

4D22

0pF

87

CN

3A22

0pF

CN

3A22

0pF

21

U11

GD75232PWR

U11

GD75232PWR

V+ 1

DIN116

DIN215

DIN313

ROUT119

ROUT218

ROUT317

ROUT414

ROUT512

V- 10GND11RIN5 9

RIN4 7

RIN3 4RIN2 3RIN1 2

DOUT3 8

DOUT2 6DOUT1 5

VCC20

CN

4B22

0pF

CN

4B22

0pF

43

VGA_COM1A

C020388-2

VGA_COM1A

C020388-2

C1C6C2C7C3C8C4C9C5

G1

G2

CN

5B22

0pF

CN

5B22

0pF

43

CN

2D22

0pF

CN

2D22

0pF

87

C1010.1uFC1010.1uF

CN

4C22

0pF

CN

4C22

0pF

65

CN

5A22

0pF

CN

5A22

0pF

21

CN

2C22

0pF

CN

2C22

0pF

65

CN

2A22

0pF

CN

2A22

0pF

21

U10

GD75232PWR

U10

GD75232PWR

V+ 1

DIN116

DIN215

DIN313

ROUT119

ROUT218

ROUT317

ROUT414

ROUT512

V- 10GND11RIN5 9

RIN4 7

RIN3 4RIN2 3RIN1 2

DOUT3 8

DOUT2 6DOUT1 5

VCC20

CN

5D22

0pF

CN

5D22

0pF

87

CN

3D22

0pF

CN

3D22

0pF

87

CN

2B22

0pF

CN

2B22

0pF

43

C970.1uFC970.1uF

C760.1uFC760.1uF

CN

3B22

0pF

CN

3B22

0pF

43

CN

5C22

0pF

CN

5C22

0pF

65

COM2

2213S-10G-E10-F2

COM2

2213S-10G-E10-F2

13 4

2

5 67 89

C650.1uFC650.1uF

CN

3C22

0pF

CN

3C22

0pF

65

C960.1uFC960.1uF

CN

4A22

0pF

CN

4A22

0pF

21

C640.1uFC640.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

COM_RXD3COM_DSR3

COM_DTR3COM_CTS3

COM_RI3

COM_RTS3

COM_DCD3

COM_TXD3

COM_RI3

COM_RXD3

COM_DCD3

COM_RTS3

COM_DTR3COM_CTS3

COM_DSR3

COM_TXD3

COM_RXD4

COM_TXD4

COM_RI4

COM_DSR4

COM_CTS4COM_DTR4COM_RI4

COM_DCD4

COM_RTS4 COM_RTS4COM_RXD4

COM_TXD4

COM_DTR4

COM_DSR4COM_DCD4

COM_CTS4

SIO_-DSR3[7]SIO_-DCD3[7]

SIO_RXD3[7]

SIO_TXD3[7]SIO_-CTS3[7]SIO_-DTR3[7]

SIO_-RTS3[7]

SIO_-RI3[7]

SIO_TXD4[7]

SIO_-RI4[7]

SIO_-CTS4[7]

SIO_-RTS4[7]

SIO_-DCD4[7]

SIO_-DTR4[7]

SIO_RXD4[7]SIO_-DSR4[7]

+12V_VCC

-12V

+5V

+5V

-12V

+12V_VCC

Title


Date: Sheet of


COMBED1

COM3, COM4


A1C

Title


Date: Sheet of


COMBED1

COM3, COM4


A1C

Title


Date: Sheet of


COMBED1

COM3, COM4


A1C

COM 3

COM 4

VIA Confidential

CN

9B22

0pF

CN

9B22

0pF

43

C1020.1uFC1020.1uF

CN

6C22

0pF

CN

6C22

0pF

65

C1150.1uFC1150.1uF

CN

7D22

0pF

CN

7D22

0pF

87

CN

9A22

0pF

CN

9A22

0pF

21

C1160.1uFC1160.1uF

CN

6A22

0pF

CN

6A22

0pF

21

C1030.1uFC1030.1uF

CN

8A22

0pF

CN

8A22

0pF

21

U12

GD75232PWR

U12

GD75232PWR

V+ 1

DIN116

DIN215

DIN313

ROUT119

ROUT218

ROUT317

ROUT414

ROUT512

V- 10GND11RIN5 9

RIN4 7

RIN3 4RIN2 3RIN1 2

DOUT3 8

DOUT2 6DOUT1 5

VCC20

CN

9D22

0pF

CN

9D22

0pF

87

CN

6B22

0pF

CN

6B22

0pF

43

COMB

1009-9M9M1N1P10-L

COMB

1009-9M9M1N1P10-L

G3

D1

G4

D2

D3

D4

D5

D6

D7

D8

D9

CN

9C22

0pF

CN

9C22

0pF

65

CN

8D22

0pF

CN

8D22

0pF

87

C1230.1uFC1230.1uF

CN

8C22

0pF

CN

8C22

0pF

65

U15

GD75232PWR

U15

GD75232PWR

V+ 1

DIN116

DIN215

DIN313

ROUT119

ROUT218

ROUT317

ROUT414

ROUT512

V- 10GND11RIN5 9

RIN4 7

RIN3 4RIN2 3RIN1 2

DOUT3 8

DOUT2 6DOUT1 5

VCC20

C1140.1uFC1140.1uF

COMA

1009-9M9M1N1P10-L

COMA

1009-9M9M1N1P10-L

G1

U1

G2

U2

U3

U4

U5

U6

U7

U8

U9

CN

8B22

0pF

CN

8B22

0pF

43

CN

7A22

0pF

CN

7A22

0pF

21

CN

6D22

0pF

CN

6D22

0pF

87

CN

7B22

0pF

CN

7B22

0pF

43

CN

7C22

0pF

CN

7C22

0pF

65

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

-LP_AFD

-LP_STB

-LP_STB

-LP_ACK

LP_PE

LP_D2

LP_BUSY

LP_BUSY

LP_SLCTLP_PE

LP_D4

-LP_ERR

-LP_ACK

LP_D5

LP_D1

-LP_INIT

LPT

_VC

C

LP_SLCT

-LP_SLIN

-LP_AFD

LP_D7

-LP_SLIN

LP_D6

LP_D3

LP_D0

LP_D6

-LP_ACK

LP_D4

LP_D2LP_D1 -LP_INIT

-LP_ERR-LP_STB

LP_D5

LP_BUSY

-LP_AFD

LP_SLCT

-LP_SLIN

LP_D7

LP_PE

LP_D0

LP_D3

ROM_A5

LCLK_ROM2

ID1

LPC_AD2

CE

-BIOS_DIS0

-LPC_FRAME

ROM_A6

ID3

ID0

ROM_OE

ID2

ROM_NC

ROM_CLK

LPC_AD1LPC_AD0

ROM_A7ROM_A8

ROM_A4

ROM_A9

LPC_AD3

ROM_A10

-LP_ERR

-LP_INIT

LP_D4LP_D5

LP_D7LP_D6

LP_D0LP_D1

LP_D3LP_D2

-SPI_SS0SPI_DI

SPI_VCC

-SPI_HOLD-SPI_WP

SPI_DOSPI_CLK

-SPI_HOLD

ROM_OE

-LP_AFD[7]

-LP_STB[7]


LP_SLCT[7]

-LP_SLIN[7]

LP_PE[7]

LCLK_ROM2[8]-PCI_RST1[7,24,26]

LPC_SERIRQ[3,7]-LPC_FRAME [3,7,20]LPC_AD3 [3,7,20]

LPC_48_CLK [7]LPC_AD0[3,7,20]

LPC_HEADER [8]LPC_AD1[3,7,20]-PCI_RST1[7,24,26]

-LPC_DRQ1[3]

LPC_AD2[3,7,20]

-BIOS_DIS0 [3]

-LP_ERR[7]

-LP_INIT[7]

LP_D4[7]LP_D5[7]

LP_D7[7]LP_D6[7]

LP_D0[7]LP_D1[7]

LP_D3[7]LP_D2[7]

RST_SW [16]


SPI_VCC[3]


-BIOS_DIS1 [3]

AZ_BITCLK [3,5]

AZ_SYNC [3,5]

+5V

+3.3V

+3.3V

+5V

+3.3V+3.3V

+3.3V

+3.3V+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

Title


Date: Sheet of


COMBED1



A1C

Title


Date: Sheet of


COMBED1



A1C

Title


Date: Sheet of


COMBED1



A1C

Printer Port

LPC FLASH ROM


KEY

LPC HEADER


2 - 3 (0)

CARRIER LPC BIOS

MODULE SPI BIOS

BIOS_DIS0

1 - 2 (1)

BIOS Selection Table

Pitch 2.54mm

SPI ROM

VIA ConfidentialCARRIER SPI BIOS 2 - 3 (0) 1 - 2 (1)

2 - 3 (0)1 - 2 (1)

BIOS DISABLE

MODULE LPC BIOS 1 - 2 (1) * 1 - 2 (1) *

BIOS Type Selection Table

LPC BIOS

1 - 2 (0)

1 - 2 (0) *

BIOS_TypeBIOS_SEL1

2 - 3 (1)SPI BIOS

BIOS_SEL0

2 - 3 (1) *

AZ_SYNCAZ_BITCLK

Q242N7002Q242N7002G

DS

Q252N7002Q252N7002G

DS

C11 180pFC11 180pF

R2944.7KR2944.7K

C26 180pFC26 180pF

C15 180pFC15 180pF

R52 10KR52 10K

C20 180pFC20 180pF

RN9C 10KRN9C 10K5 6

BIOS_DIS1(1-2)

MINI-JUMPER

BIOS_DIS1(1-2)

MINI-JUMPER

C420.1uFC420.1uF

BIOS_DIS1

HEADER_1X3

BIOS_DIS1

HEADER_1X3

21

3

R51 10KR51 10K

C14 180pFC14 180pF

SPI

2213S-08G-E7-F2

SPI

2213S-08G-E7-F2

13 4

2

5 68

LPT

2213S-26G-E26-F2

LPT

2213S-26G-E26-F2

13 4

2

5 67 89 10

11 1213 1415 1617 1819 2021 2223 2425

C240.1uFC240.1uF

C73 22pF /XC73 22pF /X

R914.7KR914.7K

R79 10 /XR79 10 /X

BIOS_DIS0(1-2)

MINI-JUMPER

BIOS_DIS0(1-2)

MINI-JUMPER

C72 0.1uFC72 0.1uF

C19 180pFC19 180pF

Q232N7002Q232N7002G

DS

R754.7KR754.7K

RN32.7KRN32.7K

1 23 45 67 8

RN9B 10KRN9B 10K3 4

RN9A 10KRN9A 10K1 2

RN8D 10KRN8D 10K7 8

C10 180pFC10 180pF

D2RLS4148D2RLS4148

BIOS_SEL0

HEADER_1X3

BIOS_SEL0

HEADER_1X3

21

3

RN8C 10KRN8C 10K5 6

RN9D 10KRN9D 10K7 8

BIOS_SEL0(2-3)

MINI-JUMPER

BIOS_SEL0(2-3)

MINI-JUMPER

R23 4.7KR23 4.7K

C22 180pFC22 180pFC21 180pFC21 180pF

R50 10KR50 10K

RN8B 10KRN8B 10K3 4

BIOS_SEL1

HEADER_1X3

BIOS_SEL1

HEADER_1X3

21

3

RN8A 10KRN8A 10K1 2

RN52.7KRN52.7K

1 23 45 67 8

R764.7KR764.7K

BIOS_SEL1(1-2)

MINI-JUMPER

BIOS_SEL1(1-2)

MINI-JUMPER

R2964.7KR2964.7K

R824.7KR824.7K

C480.1uFC480.1uF

U9

6601-32-01-F6

U9

6601-32-01-F6

A012

A111

A210

A39

A48

A57

A66

A75

A827

A926

A1023

A1125

A124

A1328

A1429

A153

A162

A1730CE 22

OE 24

WE 31

D0 13

D1 14

D2 15

D3 17

D4 18

D5 19

D6 20

D7 21

A181

+5V 32

GND 16

U9A

SST49LF080A-33-4C-NH

U9A

SST49LF080A-33-4C-NH

VDD32

WE/LFRAME23

DQ721

DQ620

DQ519

DQ418

LCLK31

RST2

OE/INIT24

MODE29

GND16

NC127

NC/GND26

NC2 22

A1/ID1 11

A0/ID0 12

LAD1 14

LAD2 15

LAD3 17

A10/GPI4 30

A9/GPI3 3

A8/GPI2 4

A7/GPI1 5

A6/GPI0 6

NC3 1

LAD0 13

VDD25

A5/WP 7

A4/TBL 8

A3/ID3 9

A2/ID2 10

NC/CE28

RN22.7KRN22.7K

1 23 45 67 8

C17 180pFC17 180pF

LPC

2208S-20G-BK-E01-F2

LPC

2208S-20G-BK-E01-F2

13 4

2

5 67 89 10

11 1213 1415 1617 1819

R2974.7KR2974.7K

C36 180pFC36 180pF

C37 180pFC37 180pF

C13 180pFC13 180pFC12 180pFC12 180pF

U2

25VF080B-50-4C-S2AF

U2

25VF080B-50-4C-S2AF

CE#1

SO2

WP#3

VSS4 SI 5SCK 6

HOLD# 7VDD 8

R9 2.7KR9 2.7K

Q122N7002Q122N7002G

DS

C18 180pFC18 180pF

C35 180pFC35 180pF

R2954.7KR2954.7K

BIOS_DIS0

HEADER_1X3

BIOS_DIS0

HEADER_1X3

21

3

R77 0 /XR77 0 /X

R174.7KR174.7K

RN12.7KRN12.7K

1 23 45 67 8

R78 0 /XR78 0 /X

C16 180pFC16 180pF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

-A7_L

A0_L

A7_L

A3_L

CLK1_L

-A6_L

-A5_L

-CLK1_L

SPCLK_R

-CLK1_L

-A2_L

-A4_L

-A1_LA5_L

SPD_R

A6_L

-CLK2_L

-A7_L

-A4_L

PVDD

A6_L

CLK2_L

A2_L

CLK1_L

A7_L

A4_L

A2_L

-A5_L

-A3_L

-A6_L

-A0_L

CLK2_L-CLK2_L

-A1_L

A4_L

-A3_L

-A0_L

A3_L

A1_L

-A2_L

A0_L

A5_LA1_L

BAKLITE

IVDD_GND

SPD1

-BKLT_EN

IVDD_IN

SPCLK1

BLT_CTRL

PVDD_SEL

VDD_EN

PVDD_ON

-VDD_EN

PVDD

IVDD_SEL

BKLT_EN

PVDD_TR

LVDS_A0+[3]

LVDS_A0-[3]

LVDS_A1+[3]

LVDS_A1-[3]

LVDS_A2+[3]

LVDS_A2-[3]

LVDS_A3+[3]

LVDS_A3-[3]

LVDS_A_CK+[3]

LVDS_A_CK-[3]

LVDS_B0+[3]

LVDS_B2+[3]

LVDS_B1-[3]

LVDS_B_CK+[3]

LVDS_B_CK-[3]

LVDS_B1+[3]

LVDS_B3+[3]

LVDS_B3-[3]

LVDS_B2-[3]

LVDS_B0-[3]

SPCLK1[3]SPD1[3]

LVDS_BKLT_EN[3]

LVDS_VDD_EN[3]

BLT_CK[3,4,24]

+5V

+5V

+12V_VCC

+5V +3.3V

+5V

+5V

+5V

Title


Date: Sheet of


COMBED1

LVDS


A1C

Title


Date: Sheet of


COMBED1

LVDS


A1C

Title


Date: Sheet of


COMBED1

LVDS


A1C

+12V *

IVDD_SEL

+5V Pin 1,2 : Close

Pin 2,3 : Close



+5V

Pin 2,3 : Close

PVDD

Pin 1,2 : Close

+3.3V *

LVDS CONNECTOR


VIA Confidential

R2033R2033

C7 0.1uFC7 0.1uF

IVDD(2-3)

MINI-JUMPER

IVDD(2-3)

MINI-JUMPER

L13

NCMS20C900-TR

L13

NCMS20C900-TR

1

4 3

2

C2 0.1uFC2 0.1uF

INVERTER

CON-53398-0890

INVERTER

CON-53398-0890

11

22

33

44

55

66

8877

R10 0R10 0C270.1uFC270.1uF


B

EC

C250.1uFC250.1uF

R6 0/XR6 0/X

L5 NCMS20C900-TRL5 NCMS20C900-TR

1

4 3

2

C230.1uFC230.1uF


1

4 3

2

R59 0R59 0

U1

AD5301BRTZ /X

U1

AD5301BRTZ /X

GND1

A0 5

VOUT 4SCL3SDA2

VDD 6

IVDDHEADER_1X3

IVDDHEADER_1X3

2 13

R44.7KR44.7K

+

CE147uF

+

CE147uF

12

Q1SI2301BDS-T1-E3Q1

SI2301BDS-T1-E3G

DS


L12

NCMS20C900-TR

L12

NCMS20C900-TR

1

4 3

2

LVDS1

20031-040U-01

LVDS1

20031-040U-01

2 14 36 58 7

10 912 1114 1316 1518 1720 1922 2124 2326 2528 2730 2932 3134 3336 3538 3740 39


1

4 3

2

C300.1uFC300.1uF

R274.7KR274.7K

Q52N7002Q52N7002G

DS

C8 0.1uFC8 0.1uFR15470R15470

L9

NCMS20C900-TR

L9

NCMS20C900-TR

1

4 3

2

R36 1KR36 1K

Q22N7002Q22N7002G

DS

PVDD(2-3)

MINI-JUMPER

PVDD(2-3)

MINI-JUMPER

L11

NCMS20C900-TR

L11

NCMS20C900-TR

1

4 3

2


B

EC

L10

NCMS20C900-TR

L10

NCMS20C900-TR

1

4 3

2

R26 1KR26 1K

FB7BLM21PG300SN1D

FB7BLM21PG300SN1D


1

4 3

2

FB4BLM21PG300SN1D

FB4BLM21PG300SN1D

PVDDHEADER_1X3

PVDDHEADER_1X32

1 3

R58 0R58 0


1

4 3

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

5V_DIO 12V_DIO

-PLED_2

GND

-SLEEP_LED

Q22_B

Q11_Q

12

-PLED_2

FP_1_3 FP_2

FP_7

Q21_G

GND

FP_14

-PW_BTN

SMB_DATSMB_CLK

RST_SW

-PLED_2FP_1_3 HD_LEDFP_2

RST_SW

5V_DIO1 12V_DIO1

-SYS_RESET

-PW_BTN

COM_GPO1[3]COM_GPI2 [3]

COM_GPO3[3] COM_GPI3 [3]COM_GPO2[3]

COM_GPO0[3]COM_GPI1 [3]COM_GPI0 [3]

HD_LED [10]

SPEAK[20]

-PW_BTN [3,7]

-SUSC[3]

-PLED[7]

DIO_GPIO24[7]

DIO_GPIO63 [7]

DIO_GPIO25[7]DIO_GPIO26[7]DIO_GPIO27[7]DIO_GPIO50[7]DIO_GPIO51[7]DIO_GPIO52[7]DIO_GPIO53[7]

DIO_GPIO54 [7]DIO_GPIO55 [7]DIO_GPIO56 [7]DIO_GPIO57 [7]DIO_GPIO60 [7]DIO_GPIO61 [7]DIO_GPIO62 [7]

RST_SW [14]

-WDT_OUT[3,7]

-SYS_RESET [3]

SMB_CLK [3,8,21,22,23]SMB_DAT [3,8,21,22,23]

I2C_CLK [3]I2C_DAT [3]

+12V_VCC+5V

+5V

+5VDUAL +5V

+5V

+3.3VSUS

+3.3V

+3.3V

+5V +12V_VCC

+3.3V

+5VSUS+5V

Title


Date: Sheet of


COMEBD1



A1C

Title


Date: Sheet of


COMEBD1



A1C

Title


Date: Sheet of


COMEBD1



A1C

SPEAK

FRONT PANEL

RESET

PW-BN

HD-LED

PW-LED

PWRBTN

SMBUS

RESET_BTN

Digital I/O

VIA Confidential

MFX

I2C_BUS

F_PANEL

F_PANEL

F_PANEL

F_PANEL

13 4

2

5 67 8

111012

13 14

9

16R267 330R267 330

C14433pF /XC14433pF /X

HDD_LED1

17-21VRC/TR8

HDD_LED1

17-21VRC/TR8

1 2

R272 68R272 68

C15110uFC15110uF

R131 0/XR131 0/X

R271 2.2KR271 2.2K

DIO1

2208S-20G

DIO1

2208S-20G

13 4

2

5 67 89 10

11 1213 1415 1617 1819 20

R270 2.2KR270 2.2K

I2C_BUS

HEADER_1X3

I2C_BUS

HEADER_1X3

21

3

R1534.7K /XR1534.7K /X

MFX

2213DI10GBK1178E01F2

MFX

2213DI10GBK1178E01F2

13 4

2

5 67 89

RST_BTN

PT-002-E1

RST_BTN

PT-002-E1

1

2

3

4

C1530.1uFC1530.1uF

C15210uFC15210uF

TP15TP151

PS4SMD1206P050TF/15

PS4SMD1206P050TF/15

1 2

PS2SMD1206P050TF/15

PS2SMD1206P050TF/15

1 2

PWR_BTN

PT-002-E1

PWR_BTN

PT-002-E1

1

2

3

4

PWR_LED1

LED LAMP GREEN

PWR_LED1

LED LAMP GREEN

1 2

R268330R268330

R269330R269330

PS3SMD1206P050TF/15

PS3SMD1206P050TF/15

1 2

Q172N7002Q172N7002

G

DS


B

EC

C14633pF /XC14633pF /X

R1174.7KR1174.7K

U16

NC7SZ08M5X_NL/X

U16

NC7SZ08M5X_NL/X

12

43

5

SMBUS

HEADER_1X3

SMBUS

HEADER_1X3

21

3

PS5SMD1206P050TF/15

PS5SMD1206P050TF/15

1 2

R1844.7K /XR1844.7K /X

R116 0R116 0

DIO2

2213S-12G-F2

DIO2

2213S-12G-F2

13 45 67 89 10

11 12

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VUSB2

USBD_T2+USBD_T2- USBD_T3-

USBD_T3+USBD_T1+USBD_T1-USBD_T0-

USBD_T0+

-ROC0 -ROC2


USB_DT1- USBD_T1-

USB_DT0+ USBD_T0+USBD_T0-

USBD_T2+USBD_T2-

USBD_T3-

USB_DT2+

USB_DT3+ USBD_T3+USB_DT3-

USB_DT2-

VUSB0

USBD_T0+

USBD_T0-

USBD_T1-

USBD_T1+

USBD_T2-

USBD_T2+

USBD_T3-

USBD_T3+

VUSB4

USBD_T4+USBD_T4-

USBD_T5+USBD_T5-

-ROC4

USBD_T5-

USBD_T4-



USBD_T4-

USBD_T4+

USBD_T5-

USBD_T5+

-USB_OC2[3]-USB_OC0[3]

USB_DT0-[3]

USB_DT0+[3]

USB_DT1-[3]

USB_DT1+[3]

USB_DT2-[3]

USB_DT2+[3]

USB_DT3-[3]

USB_DT3+[3]

-USB_OC4[3]

-RF_ON [7]W_LESS_LED [19]

USB_DT4-[3]

USB_DT5-[3]

USB_DT4+[3]

USB_DT5+[3]

+5VDUAL +5VDUAL

+5VDUAL

Title


Date: Sheet of


COMBED1

USB CONNECTOR


A1C

Title


Date: Sheet of


COMBED1

USB CONNECTOR


A1C

Title


Date: Sheet of


COMBED1

USB CONNECTOR


A1C

USB 1/2 USB 3/4

1. VUSB4(+5VDUAL)

5. W_LESS_LED

6. -RF_ON

Active High

VNT

4. GND

3. USBD_T5+

USBD_T5- , USBD_T5+for VNT 6656

2. USBD_T5-

Active Low

VNT Connector: 1x6 2.54mm

USB 5/6

USB 5/6

VIA Confidential

R12982KR12982K

C810.1uFC810.1uF

C780.1uFC780.1uF

L17NCMS20C900-TRL17NCMS20C900-TR

1

4 3

2


1

4 3

2

C940.1uFC940.1uF

C1260.1uFC1260.1uF


USB_3/4

UB1112C-8D1-4F

USB_3/4

UB1112C-8D1-4F

U1U2U3U4

U5U6U7U8

G1 G3

G2 G4

RN15 0/XRN15 0/X1 23 45 67 8

+

CE7220uF

+

CE7220uF

12

R104 68KR104 68K

R89 68KR89 68K

+

CE9220uF

+

CE9220uF

12


R128 68KR128 68K

USB_5/6

2213S-12G-BK-E9-F2

USB_5/6

2213S-12G-BK-E9-F2

13 45 67 8

1011 12

2

PS82APS82A

12


1

4 3

2

+

CE2220uF

+

CE2220uF

12

RN16 0/XRN16 0/X1 23 45 67 8

R8882KR8882K

C791uFC791uF

C801000pFC801000pF

R115 0R115 0

RN18 0/XRN18 0/X1 23 45 67 8

PS72APS72A

12

C1270.1uFC1270.1uF

R10282KR10282K


1

4 3

2

USB_LAN1A

9711-8814-S0L30-E-A

USB_LAN1A

9711-8814-S0L30-E-A

U1U2U3U4

U5U6U7U8

G1 G3

G2 G4

C951uFC951uF

PS92APS92A

12

C930.1uFC930.1uF

C1301uFC1301uF


1

4 3

2

C921000pFC921000pF

C1311000pFC1311000pF


1

4 3

2


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VUSB6

USBD_T6+

-ROC6

USBD_T7-

USBD_T7+

USBD_T6-


USBD_T7-

USBD_T7-USBD_T7+

USBD_T6+USB_DT6+USB_DT6- USBD_T6-

USBD_T6-

USBD_T6+

-USB_OC6[3]

USB_DT7-[3]

USB_DT7+[3]

USB_DT6+[3]

USB_DT6-[3]

+5VDUAL

Title


Date: Sheet of


COMBED1

USB Port 7 & 8


A1C

Title


Date: Sheet of


COMBED1

USB Port 7 & 8


A1C

Title


Date: Sheet of


COMBED1

USB Port 7 & 8


A1C

USB 7/8

VIA Confidential


1

4 3

2

PS102APS102A

12

R12782KR12782K

R126 68KR126 68K


1

4 3

2

C1240.1uFC1240.1uF

C1250.1uFC1250.1uF

C1291000pFC1291000pF

RN17 0/XRN17 0/X1 23 45 67 8

C1281uFC1281uF


+

CE8220uF

+

CE8220uF

12

USB_7/8

USB_CONN

USB_7/8

USB_CONN

13 4

2

5 67 8

10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LAN_-ACT

T_CT1

T_CT4

T_CT3

T_CT2

MCT2

MCT1

MCT0

-SP1000

-SP100

-ACT

-MDI0+MDI0

+MDI2-MDI2

-MDI3+MDI3

+MDI1

-MDI1

MCT3

MDI2-

MDI3+

MDI3-

MDI0+

MDI0-

MDI1+

MDI1-

MDI2+

-MDI3+MDI3

+MDI2-MDI2

-MDI1+MDI1

+MDI0-MDI0

W_LESS_LED[17]

LAN_-SP100 [3]

LAN_-SP1000 [3]

LAN_-ACT [3]

MDI0- [3]MDI0+ [3]

MDI1- [3]MDI1+ [3]

MDI3- [3]MDI3+ [3]

MDI2- [3]MDI2+ [3]

VDDTXRX_LAN [3]

+3.3VSUS

+3.3VSUS

RJ45_CGND

RJ45_CGND

RJ45_CGND

RJ45_CGND

Title


Date: Sheet of


COMBED1

RJ45/ LAN LED


A1C

Title


Date: Sheet of


COMBED1

RJ45/ LAN LED


A1C

Title


Date: Sheet of


COMBED1

RJ45/ LAN LED


A1C

VIA Confidential

RJ45

1st : LAN LED


FRONT LAN LED

GST5009 LF / LG-2413S-1 / P1012


99G26-07053299G26-070542

99G26-07056F

99G26-07053J

VT6122

BothhandGST5009 LF

LG-2413S-1

P1012(001-00)

TST1284A LF

LF-H6442S-1

VT6107

P1212(007-00)

T1

LANKOM

UDE

RTL8111E T1 install GST5009 LFVT6107 T1 install TST1284A LF

RTL8111E /

VT6122 /

O:mount X:unmount

VT6107

RTL8111E

VT6122

GST5009 LF99G26-070532

TST1284A LF99G26-070542

T1 C229,C230

99G26-070532GST5009 LF

FB69 C720,C722,C724,C727(6.8pFx4)

O

X

X

O

O

X

X

Bi-Tripple-color mode

L9_LED1

LEDS1,LEDS0

Note:

01=100M Link(Green)

LED Selection

LED2,LED1=

Link/Act (Yellow)

RJ45 Link status GMTI_9711-8814-S0L30-E-A for VT6107

0,1

L10_LED2

00=Link off(Darkless)

11=10M Link(Darkless)

Link: LED on

L12_LED0

CASE_1

R291

O O

R292, R293

O X

X X

C233C231

0.01uF

0.1uF

X X

O X X

O

99G26-07055F

99G26-07058J

R106 330R106 330

R2930R2930

C234 1000pF/2KVC234 1000pF/2KV

R28475R28475

R107 330R107 330

FB69CBG201209-260/XFB69CBG201209-260/X

C7246.8pF/XC7246.8pF/X


T1

GST5009 LF

T1

GST5009 LF

TCT1 1

TD1+ 2

TD1- 3

TCT2 4

TD2+ 5

TD2- 6

TCT3 7

TD3+ 8

TD3- 9

TCT4 10

TD4+ 11

TD4- 12

MCT124

MX1+23

MX1-22

MCT221

MX2+20

MX2-19

MCT318

MX3+17

MX3-16

MCT415

MX4+14

MX4-13

C231

0.1uF/X

C231

0.1uF/X

R2920R2920

R28575R28575

R28775R28775

R108 330R108 330

FLAN_LED

2208S-10G-E09-F2

FLAN_LED

2208S-10G-E09-F2

134

2

567

108

R2910R2910

C7226.8pF/XC7226.8pF/X

C7206.8pF/XC7206.8pF/X

C230

0.1uF/X

C230

0.1uF/X

R282 330R282 330

C233

0.1uF

C233

0.1uF

C7276.8pF/XC7276.8pF/X

R105 330R105 330


R28675R28675

R290 330R290 330

R283 330R283 330

C229

0.1uF/X

C229

0.1uF/X

C232 0.1uFC232 0.1uF

Yellow/R

Green/L

Yellow/L

TX_D1+TX_D1-

BI_D3+

BI_D4-

BI_D3-RX_D2-BI_D4+

RX_D2+

USB_LAN1B9711-8814-S0L30-E-A

Yellow/R

Green/L

Yellow/L

TX_D1+TX_D1-

BI_D3+

BI_D4-

BI_D3-RX_D2-BI_D4+

RX_D2+

USB_LAN1B9711-8814-S0L30-E-A

L1L2L3L4L5L6

L8L7

G5G6

G7

G8L9L10

L11

L12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-DGHLED_B

LED_ELED_C

LED_G

LED_DLED_FLED_A

-DGL

LED_E

LED_A

LED_G

LED_C

LED_B

LED_F

LED_D

-DGH

-DGL

LCLK_AK2001 [8]

-LPC_FRAME [3,7,14]

LPC_AD0 [3,7,14]

LPC_AD1 [3,7,14]

LPC_AD2 [3,7,14]

LPC_AD3 [3,7,14]

-PCI_RST3 [26]

SPKR [3,5]

SPEAK [16]

+3.3V

+3.3V

+3.3V

+3.3V

+3.3VSUS

+5VDUAL

+5V

-12V

+12V_VCC

+5V

+5V

Title


Date: Sheet of


COMBED1



A1C

Title


Date: Sheet of


COMBED1



A1C

Title


Date: Sheet of


COMBED1



A1C

LPC DEBUG PORT

LED

=R 30mA

V- Vf------------


BUZZER

VIA Confidential

R262 110R262 110

+5V_DUAL

LED LAMP GREEN

+5V_DUAL

LED LAMP GREEN

1 2

R35 33R35 33

C31 10uFC31 10uF

BUZZ1

KC-1206

BUZZ1

KC-1206

12

R27568R27568

R277 1KR277 1K


B

EC

C29 0.1uFC29 0.1uF

R259 360R259 360

R5 33R5 33

U4

AK2001-G

U4

AK2001-G

DGH#1

GND2

LEDA3

LEDB4

LEDC5

LEDD6

LEDE7

LEDF8

LEDG9

VCC110 DGL# 11

GND 12

PCICLK 13

LFRAME# 14

LAD0 15

LAD1 16

LAD2 17

LAD3 18

PCIRST# 19

VCC2 20

-12V_

LED LAMP GREEN

-12V_

LED LAMP GREEN

12

+3_3VSUS

LED LAMP GREEN

+3_3VSUS

LED LAMP GREEN

1 2

R261 51R261 51

+5V_

LED LAMP GREEN

+5V_

LED LAMP GREEN

1 2

+12V_VCC_

LED LAMP GREEN

+12V_VCC_

LED LAMP GREEN

1 2

+3_3V_

LED LAMP GREEN

+3_3V_

LED LAMP GREEN

1 2R276 22R276 22

C2271uFC2271uF

PORT_80


PORT_80


DG1

DA3

DF4


SEL1# 10

R263 360R263 360

C1 0.1uFC1 0.1uF

R258 110R258 110

R274 4.7KR274 4.7K

R260 51R260 51

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

-PE_RST0

SMB_DAT

-PE_WAKE

SMB_CLK

-PE1PRT2_1 -PE1PRT2_1

-PE1PRT2_1



-PE_RST0 [3,23]


-PE_WAKE[3,22,23]




SMB_CLK[3,8,16,22,23]SMB_DAT[3,8,16,22,23]

+12V_VCC +12V_VCC

+3.3V+3.3V

+3.3VSUS+3.3V

+12V_VCC

+3.3V

+3.3VSUS

+12V_VCC

+12V_VCC +12V_VCC+3.3V +3.3VSUS +3.3V +3.3VSUS

+3.3V

Title


Date: Sheet of


COMBED1

PCI Express x1


A1C

Title


Date: Sheet of


COMBED1

PCI Express x1


A1C

Title


Date: Sheet of


COMBED1

PCI Express x1


A1C

#1 PCIE X 1 #2 PCIE X 1

VIA Confidential

R212 2.2KR212 2.2K

+CE43 100uF+CE43 100uF1 2+CE65 470uF/16V+CE65 470uF/16V1 2

C207 0.1uFC207 0.1uF C206 0.1uFC206 0.1uF

Mechanical Key

PCI_Express_x1


PE2

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE2

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

Mechanical Key

PCI_Express_x1


PE1

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE1

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

C187 0.1uFC187 0.1uF C188 0.1uFC188 0.1uF

+CE63 100uF+CE63 100uF1 2

C213 0.1uFC213 0.1uF

+CE41 470uF/16V+CE41 470uF/16V1 2 +CE42 100uF+CE42 100uF1 2

C215 0.1uFC215 0.1uF

+CE64 100uF+CE64 100uF1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

-PE1PRT2_2

-PE_WAKE -PE_RST1

SMB_DATSMB_CLK

-PE1PRT2_2-PE1PRT2_2

-PE_RST1-PE_WAKE

SMB_DATSMB_CLK

-PE1PRT2_2

PCIE_CLK4- [8]PCIE_TX4-[3]


PCIE_CLK4+ [8]PCIE_TX4+[3]

SMB_CLK[3,8,16,21,23]SMB_DAT[3,8,16,21,23]

PCIE_RX3+ [3]

PCIE_TX3+[3]PCIE_CLK3+ [8]

PCIE_TX3-[3]

PCIE_RX3- [3]

PCIE_CLK3- [8]

-PE_RST1 [3]-PE_WAKE[3,21,23]

PCIE_TX2+[3]

PCIE_RX2+ [3]

PCIE_CLK2- [8]

PCIE_RX2- [3]

PCIE_TX2-[3]

PCIE_CLK2+ [8]

+3.3VSUS

+3.3V +12V_VCC

+3.3VSUS+3.3V

+12V_VCC+12V_VCC

+3.3V

+3.3VSUS

+3.3V +12V_VCC

+12V_VCC

+3.3V+3.3V

+12V_VCC

+3.3VSUS

+12V_VCC

+3.3V+3.3V

+3.3VSUS

+12V_VCC+12V_VCC

+3.3V

+3.3V

+3.3VSUS

Title


Date: Sheet of


COMBED1

PCI Express x1 -2


A1C

Title


Date: Sheet of


COMBED1

PCI Express x1 -2


A1C

Title


Date: Sheet of


COMBED1

PCI Express x1 -2


A1C

#5 PCIE X 1

#4 PCIE X 1#3 PCIE X 1

VIA Confidential

C189 0.1uFC189 0.1uF

C204 0.1uFC204 0.1uF

+CE46 100uF+CE46 100uF1 2

+CE50 470uF/16V+CE50 470uF/16V1 2

+CE56 100uF+CE56 100uF1 2

+CE51 470uF/16V+CE51 470uF/16V1 2

C201 0.1uFC201 0.1uF

+CE47 100uF+CE47 100uF1 2

+CE48 100uF+CE48 100uF1 2

+CE55 100uF+CE55 100uF1 2

Mechanical Key

PCI_Express_x1


PE5

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE5

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

C200 0.1uFC200 0.1uF

C208 0.1uFC208 0.1uF

+CE57 470uF/16V+CE57 470uF/16V1 2

C220 0.1uFC220 0.1uF

Mechanical Key

PCI_Express_x1


PE3

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE3

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

Mechanical Key

PCI_Express_x1


PE4

EE01800S-H3Z

Mechanical Key

PCI_Express_x1


PE4

EE01800S-H3Z

+12V1B1

+12V2B2

+12V5B3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#B17

GNDB18

PRSNT1# A1

+12V3 A2

+12V4 A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V2 A9

+3.3V3 A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

C214 0.1uFC214 0.1uF

C221 0.1uFC221 0.1uF

C219 0.1uFC219 0.1uF

+CE49 100uF+CE49 100uF1 2

R246 2.2KR246 2.2K

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

PSN2_1

PSN2_2

PSN2_3






PEG_TX5-[4]PEG_TX5+[4]











SMB_CLK[3,8,16,21,22]SMB_DAT[3,8,16,21,22]

-PE_WAKE[3,21,22]


-PE_RST0 [3,21]

+12V_VCC+12V_VCC

+3.3V +3.3V

+3.3VSUS

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+12V_VCC

+3.3VSUS

Title


Date: Sheet of


COMBED1

PCI Express x16


A1C

Title


Date: Sheet of


COMBED1

PCI Express x16


A1C

Title


Date: Sheet of


COMBED1

PCI Express x16


A1C

PCIE X 16

PCI Express x16, +12V 300mil width.


VIA Confidential

R162 2.2KR162 2.2K

R1574.7KR1574.7K

R161 2.2KR161 2.2K

C154 0.1uFC154 0.1uF

+CE19 470uF/16V+CE19 470uF/16V1 2

R156 4.7KR156 4.7K

C148 0.1uFC148 0.1uF

C147 0.1uFC147 0.1uF

R163 2.2KR163 2.2K

R1584.7KR1584.7K

+CE18 100uF+CE18 100uF1 2

+CE14 100uF+CE14 100uF1 2

+CE17 100uF+CE17 100uF1 2

Mechanical Key

PCI_Express_x16





PE16

PCI_EXPRESS_X16

Mechanical Key

PCI_Express_x16





PE16

PCI_EXPRESS_X16

+12VB1

+12VB2

+12VB3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3.3B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GNDB13

PETP0B14

PETN0B15

GNDB16

PRSNT2#1B17

GNDB18

PRSNT1# A1

+12V A2

+12V A3

GND A4

JTAG2 A5

JTAG3 A6

JTAG4 A7

JTAG5 A8

+3.3V A9

+3.3V A10

PERST# A11

GND A12

REFCLK+ A13

REFCLK- A14

GND A15

PERP0 A16

PERN0 A17

GND A18

PETP1B19

PETN1B20

GNDB21

GNDB22

PETP2B23

PETN2B24

GNDB25

GNDB26

PETP3B27

PETN3B28

GNDB29

RSVD3B30

PRSNT2#2B31

GNDB32

RSVD5 A19

GND A20

PERP1 A21

PERN1 A22

GND A23

GND A24

PERP2 A25

PERN2 A26

GND A27

GND A28

PERP3 A29

PERN3 A30

GND A31

RSVD6 A32

PETP4B33

PETN4B34

GNDB35

GNDB36

PETP5B37

PETN5B38

GNDB39

GNDB40

PETP6B41

PETN6B42

GNDB43

GNDB44

PETP7B45

PETN7B46

GNDB47

PRSNT2#3B48

GNDB49

RSVD7 A33

GND A34

PERP4 A35

PERN4 A36

GND A37

GND A38

PERP5 A39

PERN5 A40

GND A41

GND A42

PERP6 A43

PERN6 A44

GND A45

GND A46

PERP7 A47

PERN7 A48

GND A49

PETP8B50

PETN8B51

GNDB52

GNDB53

PETP9B54

PETN9B55

GNDB56

GNDB57

PETP10B58

PETN10B59

GNDB60

GNDB61

PETP11B62

PETN11B63

GNDB64

GNDB65

PETP12B66

PETN12B67

GNDB68

GNDB69

PETP13B70

PETN13B71

GNDB72

GNDB73

PETP14B74

PETN14B75

GNDB76

GNDB77

PETP15B78

PETN15B79

GNDB80

PRSNT2#4B81

RSVD4B82

RSVD8 A50

GND A51

PERP8 A52

PERN8 A53

GND A54

GND A55

PERP9 A56

PERN9 A57

GND A58

GND A59

PERP10 A60

PERN10 A61

GND A62

GND A63

PERP11 A64

PERN11 A65

GND A66

GND A67

PERP12 A68

PERN12 A69

GND A70

GND A71

PERP13 A72

PERN13 A73

GND A74

GND A75

PERP14 A76

PERN14 A77

GND A78

GND A79

PERP15 A80

PERN15 A81

GND A82

R160 4.7KR160 4.7K

+CE16 470uF/16V+CE16 470uF/16V1 2

R155 0R155 0

R159 0R159 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DVP1_VDD_EN[4]

DVP1_TVFLD [4]

DISP_CLKO0 [4]DISP_CLKI0 [4]

SPDIF-HDMI [5]

-PCI_RST1[7,14,26]

-PCI_INT_A[4,25,26]

DVP1_HS [4]DVP1_VS [4]

DVP1_TVCLKR [4]

DVP1_D2 [4]DVP1_D3 [4]

DVP1_D6 [4]DVP1_D7 [4]

DVP1_D9 [4]

DVP1_D12 [4]DVP1_D13 [4]

DVP1_CLK [4]

DVP1_DE [4]

DVP1_BKLT_EN[4]



DVP1_D8[4]

DVP1_D10[4]DVP1_D11[4]

DVP1_D14[4]DVP1_D15[4]

BLT_CK[3,4,15]

DVP1_DET [4]

+5V+3.3V

+5V

+3.3V

+5V +3.3V

Title


Date: Sheet of


COMBED1

DVP SLOT


A1C

Title


Date: Sheet of


COMBED1

DVP SLOT


A1C

Title


Date: Sheet of


COMBED1

DVP SLOT


A1C

DVP SLOT

10V 080510V 0805

VIA Confidential

+CE32 470uF/16V+CE32 470uF/16V1 2

C162 10uFC162 10uF

+CE33 470uF/16V+CE33 470uF/16V1 2

C163 10uFC163 10uF

Mechanical Key

PCI_Express_x4



DVP_SLOT

EE03200S-CP3

Mechanical Key

PCI_Express_x4



DVP_SLOT

EE03200S-CP3

+5V B1+5V B2NC B3

GND B4SPCLK1 B5

SPD1 B6GND B7

+3.3V B8TVFLD B9+3.3V B10

DE B11

CLOCK B12GND B13D13 B14D12 B15

GND B16D9 B17

GND B18

RST#A1+5VA2+5VA3GNDA4NCA5TS1ERRA6VCP1VSYNCA7VCP1HSYNCA8+3.3VA9+3.3VA10INTA11

GNDA12D15A13D14A14GNDA15D11A16D10A17GNDA18

D7 B19D6 B20

GND B21GND B22

D3 B23D2 B24

GND B25GND B26

VSYNC B27HSYNC B28

GND B29DET/TVCLKR B30

TVCLKR B31GND B32

D8A19GNDA20D5A21D4A22GNDA23GNDA24D1A25D0A26GNDA27GNDA28ENBLTA29ENVDDA30GNDA31NCA32

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

-P1REQ64

-P1LOCK

-P1ACK64

-P1ACK64-P1REQ64

-PCI_INT_B-PCI_IRDY

-PCI_PERR-PCI_SERR

-PCI_STOP

-PCI_FRAME

-PCI_TRDY-PCI_DEVSEL

-P1LOCK

-PCI_INT_A

-PCI_INT_C-PCI_INT_D

-PCI_GNT0-PCI_REQ0

-PCI_REQ2

-PCI_GNT1-PCI_GNT2

-PCI_REQ1

-PCI_GNT3

-PCI_REQ3

-PCI_INT_A

PCI_AD28

PCI_AD8

PCI_AD22

PCI_AD25

-PCI_INT_D

PCI_AD9

-PCI_STOP

PCI_AD16

PCI_AD19

-PCI_FRAME

PCI_AD10

PCI_AD26

-PCI_INT_C

-PCI_GNT1

PCI_AD27

PCI_AD20

-PCI_PERR

PCI_PAR

PCI_AD24

-PCI_INT_B

PCI_AD31

PCI_AD15

PCI_AD1

PCI_AD12

-P2ACK64

PCI_-CBE3

PCI_AD4

PCI_AD7PCI_AD6

PCI_AD2

PCI_AD5

-PCI_DEVSEL

PCI_AD21

-PCI_PME

-PCI_SERR

-PCI_REQ1

PCI_AD29PCI_AD30

PCI_AD20

PCI_AD18

-P2REQ64

PCI_-CBE0

PCI_AD3

-PCI_TRDY

PCI_-CBE1

PCI_AD23

PCI_-CBE2

PCI_AD13

-PCI_IRDY

PCI_AD0

-PCI_RST4

PCI_AD11

-P2LOCK

PCI_AD17

PCI_AD14

-P2REQ64-P2ACK64

PCI_CLK1PCI_33_CLK1

PCI_33_CLK2 PCI_CLK2

-P2LOCK

PCI_AD19

PCI_AD1[4,26]

PCI_AD3[4,26]PCI_AD5[4,26]

PCI_AD7[4,26]PCI_AD8[4,26]

PCI_AD10[4,26]PCI_AD12[4,26]

PCI_AD14[4,26]

PCI_AD17[4,26]

PCI_AD19[4,26]PCI_AD21[4,26]

PCI_AD23[4,26]

PCI_AD25[4,26]PCI_AD27[4,26]

PCI_AD29[4,26]PCI_AD31[4,26]

-PCI_IRDY[4,26]

-PCI_DEVSEL[4,26]

-PCI_PERR[4,26]

PCI_-CBE1[4,26]

PCI_-CBE2[4,26]

PCI_-CBE3[4,26]

-PCI_SERR[4,26]

-PCI_INT_B[4,26]-PCI_INT_D[4,26]

-PCI_INT_A [4,24,26]-PCI_INT_C [4,26]

-PCI_RST2 [26]

-PCI_GNT0 [4]

PCI_AD30 [4,26]

PCI_AD28 [4,26]PCI_AD26 [4,26]

PCI_AD24 [4,26]

PCI_AD22 [4,26]PCI_AD20 [4,26]

PCI_AD18 [4,26]PCI_AD16 [4,26]

-PCI_FRAME [4,26]

-PCI_TRDY [4,26]

-PCI_STOP [4,26]

PCI_PAR [4,26]PCI_AD15 [4,26]

PCI_AD13 [4,26]PCI_AD11 [4,26]

PCI_AD9 [4,26]

PCI_AD6 [4,26]PCI_AD4 [4,26]

PCI_AD2 [4,26]PCI_AD0 [4,26]

PCI_-CBE0 [4,26]

PCI_33_CLK1[8]

-PCI_PME [4,7,26]-PCI_REQ0[4]

-PCI_REQ2[4,26]

-PCI_REQ3[4]

-PCI_GNT2[4,26]

-PCI_GNT3[4]

-PCI_REQ1[4]

-PCI_GNT1[4]

PCI_33_CLK2[8]

-PCI_RST4[26]

+3.3V

+5V

+12V_VCC

+5V

+3.3VSUS

+3.3V -12V

+12V_VCC

+5V

+5V

+3.3V +5V

+5V +5V

+3.3V+3.3V -12V +12V_VCC

+3.3VSUS

+3.3V+5V-12V

Title


Date: Sheet of


COMBED1

PCI Slot 1,2


A1C

Title


Date: Sheet of


COMBED1

PCI Slot 1,2


A1C

Title


Date: Sheet of


COMBED1

PCI Slot 1,2


A1C

16V 0805

16V 0805

PCI 1

10V 0805

10V 0805 10V 0805

10V 0805

PCI 2

-PCI_REQ0, -PCI_GNT0, -INTAPCI SLOT1: AD19

-PCI_REQ1, -PCI_GNT1, -INTBPCI SLOT2: AD20

VIA ConfidentialR240 4.7KR240 4.7K

C205 10uFC205 10uF

R253 2.2KR253 2.2K

C212 10uFC212 10uF+CE53 470uF/16V+CE53 470uF/16V12

+CE54 470uF/16V+CE54 470uF/16V1 2

C216 10uFC216 10uF

R245 2.2KR245 2.2K

R243 4.7KR243 4.7K

R238 4.7KR238 4.7K

C211 5pF /XC211 5pF /X

C218 10uFC218 10uF

R244 2.2KR244 2.2K

PCI1

EH0600F-DAW

PCI1

EH0600F-DAW

TRST A1

+12V A2

TMS A3

TDI A4

+5V A5

INTA A6

INTC A7

+5V A8

RESERVED3 A9

+5V A10

RESERVED4 A11

GND A12

GND A13

3.3V_AUX A14

RST A15

+5V A16

GNT A17

GND A18

PME A19

AD30 A20

+3.3V A21

AD28 A22

AD26 A23

GND A24

AD24 A25

IDSEL A26

+3.3V A27

AD22 A28

AD20 A29

GND A30

AD18 A31

AD16 A32

+3.3V A33

FRAME A34

GND A35

TRDY A36

GND A37

STOP A38

+3.3V A39

SDONE A40

SBO A41

GND A42

PAR A43

AD15 A44

+3.3V A45

AD13 A46

AD11 A47

GND A48

AD9 A49

C/BE0 A52

+3.3V A53

AD6 A54

AD4 A55

GND A56

AD2 A57

AD0 A58

+5V A59

REQ64 A60

+5V A61

+5V A62

-12VB1

TCKB2

GNDB3

TDOB4

+5VB5

+5VB6

INTBB7

INTDB8

PRSNT1B9

RESERVED1B10

PRSNT2B11

GNDB12

GNDB13

RESERVED2B14

GNDB15

CLKB16

GNDB17

REQB18

+5VB19

AD31B20

AD29B21

GNDB22

AD27B23

AD25B24

+3.3VB25

C/BE3B26

AD23B27

GNDB28

AD21B29

AD19B30

+3.3VB31

AD17B32

C/BE2B33

GNDB34

IRDYB35

+3.3VB36

DEVSELB37

GNDB38

LOCKB39

PERRB40

+3.3VB41

SERRB42

+3.3VB43

C/BE1B44

AD14B45

GNDB46

AD12B47

AD10B48

GNDB49

AD8B52

AD7B53

+3.3VB54

AD5B55

AD3B56

GNDB57

AD1B58

+5VB59

ACK64B60

+5VB61

+5VB62

R97 4.7KR97 4.7K

R252 2.2KR252 2.2K

+CE67 470uF/16V+CE67 470uF/16V1 2

RN19 4.7KRN19 4.7K1 23 45 67 8

R248 4.7KR248 4.7K

+CE59 470uF/16V+CE59 470uF/16V1 2

R237 4.7KR237 4.7K

RN20 4.7KRN20 4.7K1 23 45 67 8

PCI2

EH0600F-DAW

PCI2

EH0600F-DAW

TRST A1

+12V A2

TMS A3

TDI A4

+5V A5

INTA A6

INTC A7

+5V A8

RESERVED3 A9

+5V A10

RESERVED4 A11

GND A12

GND A13

3.3V_AUX A14

RST A15

+5V A16

GNT A17

GND A18

PME A19

AD30 A20

+3.3V A21

AD28 A22

AD26 A23

GND A24

AD24 A25

IDSEL A26

+3.3V A27

AD22 A28

AD20 A29

GND A30

AD18 A31

AD16 A32

+3.3V A33

FRAME A34

GND A35

TRDY A36

GND A37

STOP A38

+3.3V A39

SDONE A40

SBO A41

GND A42

PAR A43

AD15 A44

+3.3V A45

AD13 A46

AD11 A47

GND A48

AD9 A49

C/BE0 A52

+3.3V A53

AD6 A54

AD4 A55

GND A56

AD2 A57

AD0 A58

+5V A59

REQ64 A60

+5V A61

+5V A62

-12VB1

TCKB2

GNDB3

TDOB4

+5VB5

+5VB6

INTBB7

INTDB8

PRSNT1B9

RESERVED1B10

PRSNT2B11

GNDB12

GNDB13

RESERVED2B14

GNDB15

CLKB16

GNDB17

REQB18

+5VB19

AD31B20

AD29B21

GNDB22

AD27B23

AD25B24

+3.3VB25

C/BE3B26

AD23B27

GNDB28

AD21B29

AD19B30

+3.3VB31

AD17B32

C/BE2B33

GNDB34

IRDYB35

+3.3VB36

DEVSELB37

GNDB38

LOCKB39

PERRB40

+3.3VB41

SERRB42

+3.3VB43

C/BE1B44

AD14B45

GNDB46

AD12B47

AD10B48

GNDB49

AD8B52

AD7B53

+3.3VB54

AD5B55

AD3B56

GNDB57

AD1B58

+5VB59

ACK64B60

+5VB61

+5VB62

R251 4.7KR251 4.7K

+CE68 470uF/16V+CE68 470uF/16V12R250 22 /XR250 22 /X

R255 4.7KR255 4.7K

+CE66 470uF/16V+CE66 470uF/16V1 2

R239 4.7KR239 4.7K

+CE60 470uF/16V+CE60 470uF/16V1 2

R247 100R247 100

R249 4.7KR249 4.7K

+CE62 470uF/16V+CE62 470uF/16V1 2

C217 5pF /XC217 5pF /X

R98 4.7KR98 4.7K

R242 22 /XR242 22 /X

R241 100R241 100

R256 4.7KR256 4.7K

C209 10uFC209 10uF

C210 10uFC210 10uF

R236 4.7KR236 4.7K

E

E

D

D

C

C

B

B

A

A

D D

C C

B B

A A

PCI_AD22

-P3REQ64

-P3LOCK

-P3ACK64

-P3ACK64

-P3REQ64

-P3LOCK

PCI_CLK3PCI_33_CLK3

-RST_2

-RST1 -RST_1

-PCI_RESET -RST2-RST2

-RST1

PCI_AD1[4,25]

PCI_AD3[4,25]PCI_AD5[4,25]

PCI_AD7[4,25]PCI_AD8[4,25]

PCI_AD10[4,25]PCI_AD12[4,25]

PCI_AD14[4,25]

PCI_AD17[4,25]

PCI_AD19[4,25]PCI_AD21[4,25]

PCI_AD23[4,25]

PCI_AD25[4,25]PCI_AD27[4,25]

PCI_AD29[4,25]PCI_AD31[4,25]

-PCI_IRDY[4,25]

-PCI_DEVSEL[4,25]

-PCI_PERR[4,25]

PCI_-CBE1[4,25]

PCI_-CBE2[4,25]

PCI_-CBE3[4,25]

-PCI_SERR[4,25]

-PCI_INT_D[4,25]-PCI_INT_B[4,25]

-PCI_INT_C [4,25]-PCI_INT_A [4,24,25]

-PCI_RST3 [20]

-PCI_GNT2 [4,25]

PCI_AD30 [4,25]

PCI_AD28 [4,25]PCI_AD26 [4,25]

PCI_AD24 [4,25]

PCI_AD22 [4,25]PCI_AD20 [4,25]

PCI_AD18 [4,25]PCI_AD16 [4,25]

-PCI_FRAME [4,25]

-PCI_TRDY [4,25]

-PCI_STOP [4,25]

PCI_PAR [4,25]PCI_AD15 [4,25]

PCI_AD13 [4,25]PCI_AD11 [4,25]

PCI_AD9 [4,25]

PCI_AD6 [4,25]PCI_AD4 [4,25]

PCI_AD2 [4,25]PCI_AD0 [4,25]

PCI_-CBE0 [4,25]

PCI_33_CLK3[8]

-PCI_PME [4,7,25]-PCI_REQ2[4,25]

-PCI_RESET[4]

-PCI_RST3 [20]

-PCI_RST2 [25]

-PCI_RST1 [7,14,24]

-PCI_RST4 [25]

+3.3V

+5V

+12V_VCC

+5V

+3.3VSUS

+3.3V -12V

+5V

+12V_VCC

-12V +5V

+3.3V

+3.3VSUS

+3.3VSUS

+3.3VSUS+3.3VSUS

+3.3VSUS

+3.3VSUS

+3.3VSUS

Title


Date: Sheet of


COMBED1

PCI Slot 3


A1C

Title


Date: Sheet of


COMBED1

PCI Slot 3


A1C

Title


Date: Sheet of


COMBED1

PCI Slot 3


A1C

PCI 3

16V 0805

16V 0805

10V 0805

10V 0805

-PCI_REQ2, -PCI_GNT2, -INTCPCI SLOT3: AD22

PCIRST

VIA Confidential+CE69 470uF/16V+CE69 470uF/16V1 2

PCI3

EH0600F-DAW

PCI3

EH0600F-DAW

TRST A1

+12V A2

TMS A3

TDI A4

+5V A5

INTA A6

INTC A7

+5V A8

RESERVED3 A9

+5V A10

RESERVED4 A11

GND A12

GND A13

3.3V_AUX A14

RST A15

+5V A16

GNT A17

GND A18

PME A19

AD30 A20

+3.3V A21

AD28 A22

AD26 A23

GND A24

AD24 A25

IDSEL A26

+3.3V A27

AD22 A28

AD20 A29

GND A30

AD18 A31

AD16 A32

+3.3V A33

FRAME A34

GND A35

TRDY A36

GND A37

STOP A38

+3.3V A39

SDONE A40

SBO A41

GND A42

PAR A43

AD15 A44

+3.3V A45

AD13 A46

AD11 A47

GND A48

AD9 A49

C/BE0 A52

+3.3V A53

AD6 A54

AD4 A55

GND A56

AD2 A57

AD0 A58

+5V A59

REQ64 A60

+5V A61

+5V A62

-12VB1

TCKB2

GNDB3

TDOB4

+5VB5

+5VB6

INTBB7

INTDB8

PRSNT1B9

RESERVED1B10

PRSNT2B11

GNDB12

GNDB13

RESERVED2B14

GNDB15

CLKB16

GNDB17

REQB18

+5VB19

AD31B20

AD29B21

GNDB22

AD27B23

AD25B24

+3.3VB25

C/BE3B26

AD23B27

GNDB28

AD21B29

AD19B30

+3.3VB31

AD17B32

C/BE2B33

GNDB34

IRDYB35

+3.3VB36

DEVSELB37

GNDB38

LOCKB39

PERRB40

+3.3VB41

SERRB42

+3.3VB43

C/BE1B44

AD14B45

GNDB46

AD12B47

AD10B48

GNDB49

AD8B52

AD7B53

+3.3VB54

AD5B55

AD3B56

GNDB57

AD1B58

+5VB59

ACK64B60

+5VB61

+5VB62

R265 4.7KR265 4.7K

+CE52 470uF/16V+CE52 470uF/16V1 2

C60.1uF /XC60.1uF /X

R322R322


R264 22 /XR264 22 /X


R254 2.2KR254 2.2K

R266 2.2KR266 2.2K

C222 5pF /XC222 5pF /X

C30.1uFC30.1uF

C750.1uF /XC750.1uF /X

C223 10uFC223 10uF

C226 10uFC226 10uF

U5A

SN74LV04ADR

U5A

SN74LV04ADR

1 2

147

R1322R1322

+CE61 470uF/16V+CE61 470uF/16V12

U5D

SN74LV04ADR

U5D

SN74LV04ADR

9 8

147

U5E

SN74LV04ADR

U5E

SN74LV04ADR

11 10

147

+CE58 470uF/16V+CE58 470uF/16V1 2

U5C

SN74LV04ADR

U5C

SN74LV04ADR

5 6

147

U5B

SN74LV04ADR

U5B

SN74LV04ADR

3 4

147

R8322R8322

R257 100R257 100

R222R222

C224 10uFC224 10uF

C225 10uFC225 10uF

U5F

SN74LV04ADR

U5F

SN74LV04ADR

13 12

147

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PSON

PW_OK

PWR_OK

TYPE1_2

TYPE0_

Q5_B

SUSB_PASS

SUSBSUSB

SUSB

PWR_OK [3]

-TYPE2[4]

-TYPE1[4]

-TYPE0[4]

-SUSB[3]

-SUSB [3]

+5V

+5VSUS

+3.3V

+12V_VCC

-12V +5V

+5V

+3.3VBAT

+3.3VSUS+5VSUS

+5VSUS

+12V_VCC

+5VDUAL+5VSUS

+5V

+5VSUS

+5VSUS+3.3VSUS

+12V +12V_VCC +12V_VCC+12V

+12V

+5VSUS+5VSUS

+5VSUS

+12V_VCC+12V+5VSUS

Title


Date: Sheet of


COMBED1


A1C

ATX POWERTitle


Date: Sheet of


COMBED1


A1C

ATX POWERTitle


Date: Sheet of


COMBED1


A1C

ATX POWER

ATX POWER

VCC_RTC

ENABLE

NORMAL

FUNCTION

2 - 3

1 - 2

CLEAR_CMOS+3.3VSUS

+5VDUAL

*

VIA Confidential

Discharge Circuit

0

10

S4/S5

S111 S3

Pstate-SUSC0

-SUSB

R1251KR1251K

ATXPWR

ATP12120-F0D8H

ATXPWR

ATP12120-F0D8H

3V3-113

-12V14

GND15

PS-ON16

GND17

GND18

GND19

-5V20

5V121

5V222

3V3-2 1

3V3-3 2

GND 3

5V4 4

GND 5

5V5 6

GND 7

PW-OK 8

5VSB 9

12V1 10

5V323

GND2412V2 11

3V3-4 12

C11010uFC11010uF

+

CE5470uF/16V

+

CE5470uF/16V

12

R1093.48K_1%R1093.48K_1%

C10010uFC10010uF

R86 10KR86 10K


1


1

+

CE11470uF/16V+

CE11470uF/16V1

2

Q212N7002Q212N7002G

DS

TP_3V3SUSTP_3V3SUS

1

+

CE61000uF/16V

+

CE61000uF/16V

12

C1180.1uFC1180.1uF


B

EC

C1330.1uFC1330.1uF

R1434.7K/XR1434.7K/X

R146100K/XR146100K/X

C1170.1uFC1170.1uF


21

3

TP_+5VSUSTP_+5VSUS

1

R27822R27822

R90 1KR90 1K

C850.1uFC850.1uF

JP2

OpenPad-1x2.5

JP2

OpenPad-1x2.5

1 2

Q14

AP4800AGM

Q14

AP4800AGM

S11

S22

S33

G4 D4 5D3 6D2 7D1 8

R147 0R147 0

C990.1uFC990.1uF

VCC

GND

U17B

74HCT08D/X

VCC

GND

U17B

74HCT08D/X

4

56

147

CLEAR_CMOS(1-2)

MINI-JUMPER

CLEAR_CMOS(1-2)

MINI-JUMPER

R123200_1%R123200_1%

TP_+3_3VTP_+3_3V

1

U13AMS1117-3.3U13AMS1117-3.3

V_INI

GN

DG

V_OUT O

C1120.1uFC1120.1uF

JP4

OpenPad-1x2.5

JP4

OpenPad-1x2.5

1 2

TP_+5VTP_+5V

1R2894.7K/XR2894.7K/X

C900.1uFC900.1uF

BAT1A

BAT_3V

BAT1A

BAT_3V

1 2

R1454.7K/XR1454.7K/X

BAT1AAA-BAT-014-K01BAT1AAA-BAT-014-K01

12

AUX12VAUX12V4

32

1

R1201KR1201K

R85 1KR85 1K

+

CE101000uF/10V

+

CE101000uF/10V

12

D16

SSM5817PT

D16

SSM5817PT

A K

R27922R27922

Q132N7002Q132N7002

G

DS

VCC

GND

U17A

74HCT08D/X

VCC

GND

U17A

74HCT08D/X

1

23

147

R1224.7KR1224.7K

R1116.65K_1%R1116.65K_1%

+

CE41000uF/16V

+

CE41000uF/16V

12

VCC

GND

U17C

74HCT08D/X

VCC

GND

U17C

74HCT08D/X

9

108

147

C1090.1uFC1090.1uF

D17

BAT54C

D17

BAT54C

1

23

JP1

OpenPad-1x2.5

JP1

OpenPad-1x2.5

1 2

C11910uFC11910uF

R280100KR280100K

+5VDUAL+5VDUAL

1

R8710KR8710K

Q202N7002Q202N7002G

DS

R118 0 /XR118 0 /X

TP_-12VTP_-12V

1

JP3

OpenPad-1x2.5

JP3

OpenPad-1x2.5

1 2

Q162N7002Q162N7002G

DS

R121470_1%R121470_1%

R119 1KR119 1K

+

CE31000uF/10V

+

CE31000uF/10V

12

C1320.1uFC1320.1uF

+12V+12V

1

R1101KR1101K

C9810uFC9810uF

C1044.7uFC1044.7uF

R1424.7K/XR1424.7K/X

C1134.7uFC1134.7uF

Q222N7002Q222N7002

G

DS

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCOUPON3_L1

PCOUPON2_L1

NCOUPON2_L1

PCOUPON1_L6

NCOUPON3_L1

PCOUPON4_L1

NCOUPON4_L1

+3.3V

+3.3V

AGND

+3.3V

+12V

AGND

Title


Date: Sheet of


COMBD1

Impedance Trace


A1C

Title


Date: Sheet of


COMBD1

Impedance Trace


A1C

Title


Date: Sheet of


COMBD1

Impedance Trace


A1C

TEST COUPON

For USB signals 90 Ohmimpedance( 6:7:6 )

DIFFERENTIAL TRACE SIGNALS

For LAN signals 100 Ohmimpedance( 5:8:5 )

VIA Confidential

For single end signals 55Ohm +- 15 Ohmimpedance 5 mils

For EMI

For SATA signals 93 Ohmimpedance( 6:8:6 )


FIDUCIAL MARK

C71 0.1uFC71 0.1uF

C108 0.1uFC108 0.1uF

C38 0.1uFC38 0.1uF

MH15MTH4mm

MH15MTH4mm

1234 5

678

9

C70 0.1uFC70 0.1uF

6mm

2.7mm

MH9

MH6_2.7

6mm

2.7mm

MH9

MH6_2.71

6mm

2.7mm

MH10

MH6_2.7

6mm

2.7mm

MH10

MH6_2.71

MH1MTH4mm

MH1MTH4mm

1234 5

678

9

C140 0.1uFC140 0.1uF

C196 0.1uFC196 0.1uF

6mm

2.7mm

MH6

MH6_2.7

6mm

2.7mm

MH6

MH6_2.71

6mm

2.7mm

MH11

MH6_2.7

6mm

2.7mm

MH11

MH6_2.71

C52 0.1uFC52 0.1uF

Z3 COUPONZ3 COUPON

MH2MTH4mm

MH2MTH4mm

1234 5

678

9

C178 0.1uFC178 0.1uF

MH19MTH4mm

MH19MTH4mm

1234 5

678

9

C185 0.1uFC185 0.1uF

C170 0.1uFC170 0.1uF

MH14MTH4mm

MH14MTH4mm

1234 5

678

9

C49 0.1uFC49 0.1uF

C50 0.1uFC50 0.1uF

C68 0.1uFC68 0.1uF

C121 0.1uFC121 0.1uF

C171 0.1uFC171 0.1uF

C194 0.1uFC194 0.1uF

6mm

2.7mm

MH12

MH6_2.7

6mm

2.7mm

MH12

MH6_2.71

MH16MTH4mm

MH16MTH4mm

1234 5

678

9

FID1

FIDUCIAL

FID1

FIDUCIAL

1

C89 0.1uFC89 0.1uF

Z4 COUPONZ4 COUPON

MH18MTH4mm

MH18MTH4mm

1234 5

678

9

6mm

2.7mm

MH5

MH6_2.7

6mm

2.7mm

MH5

MH6_2.71

MH3MTH4mm

MH3MTH4mm

1234 5

678

9

C192 0.1uFC192 0.1uF

C51 0.1uFC51 0.1uF

6mm

2.7mm

MH7

MH6_2.7

6mm

2.7mm

MH7

MH6_2.71

6mm

2.7mm

MH13

MH6_2.7

6mm

2.7mm

MH13

MH6_2.71

C53 0.1uFC53 0.1uF

Z1 COUPONZ1 COUPON

MH17MTH4mm

MH17MTH4mm

1234 5

678

9

FID3

FIDUCIAL

FID3

FIDUCIAL

1

FID2

FIDUCIAL

FID2

FIDUCIAL

1

C77 0.1uFC77 0.1uF

MH20MTH4mm

MH20MTH4mm

1234 5

678

9

C69 0.1uFC69 0.1uF

6mm

2.7mm

MH8

MH6_2.7

6mm

2.7mm

MH8

MH6_2.71

C172 0.1uFC172 0.1uF

Z2 COUPONZ2 COUPON

6mm

2.7mm

MH4

MH6_2.7

6mm

2.7mm

MH4

MH6_2.71

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