capacitance of forward biased diode - gonzaga...

Capacitance of Forward Biased Diode

• When a diode changes from reverse biased (with little current through it) to forward biased (with significant current across it) the charge being stored near and across the junction changes

• Part of the change in charges is due to the change in the width of the depletion region and therefore the amount of immobile charge stored in it( Cj)

• An additional change in the charge storage is necessary to account for the excess of minority carriers close to the depletion region edges required for the diffusion current to exists. This component is modeled by another capacitance, called the diffusion capacitance ( Cd)

• As a diode is turned off (changes from forward biased to reverse biased) for a short period of time a current will flow in the negative direction until

the minority charge is removed

Charge of Forward Biased Diode

P NIn the N region we have a lot of electronsthat will diffuse toward the P region

In the P region we have a lot of holesthat will diffuse toward the N region

Direction of positive current

Depletion Region

- - - -

- - - - - -

+ + + + + + + + + + + +

immobile chargeelectron diffusion

hole diffusion

Total Capacitance of Forward Biased Diode

• It is the sum of the diffusion capacitance Cd and the depletion capacitance Cj

• For a forward biased diode the junction capacitance is roughly approximated by:

• The approximation is not critical since the diffusion capacitance is typically much larger than than the depletion capacitance

Ctotal

Cd

Cj

Cd

Cj

Cj

2 Cj0

C j 2 C j0 for VD

0.750

Diffusion Capacitance

• To find the diffusion capacitance we first find the minority charge “close” the depletion edges Qd and then differentiate it with respect to the voltage applied Vd.

Cd

d Qd

d Vd V

D

T

Id

@VD

VT

Small signal diffusion capacitance

The diffusion capacitance of a forward biased diodeis proportional to the diode current

Diffusion ChargeQ

dQ

pQ

n

excess of minority

charge (holes)

stored in the N region

excess of minority

charge (electrons)

stored in the P region

n p x ' n p x ' 0 e

x '

Lp

0x'

np(x'=0)

n p0 e

Vd

VT

x-x

p0

np0

xn

0p

n0e

Vd

VT

pn( =0)

pn0

pn

pn

0 eL

n

Q p q A0

n p x ' dx ' q A0

n p 0 e

x '

L pdx '

q A0

n p0 e

V d

V T1 e

x '

L pdx '

q A n p0 e

Vd

VT

1

0

e

x '

Lp

dx '

q An

i

2

ND

e

V d

V T1 L p e

x '

Lp

0

q Ani

2L p

ND

e

V d

V T1

Qn

q A ni

2L

n

NA

e

Vd

VT

1

Diffusion Charge

• The excess hole charge stored in the N region is given by:

• Similarly, the excess electron charge stored in the P region is:

Jp

q Dp

L p

pn0

eV

dV

T

1

Qp

A q pn

xn

pn0

Lp

Aq L p pn0

eV

dV

T

1

A J p

L p

2

D p

I p

L p

2

D p

I p p

pn

xn

pn0

eV

dV

T

1

pn0

eV

dV

T

1 Jp

Lp

q D p

L p D p p

Qn I n n

Total Diffusion Charge

• Thus, the total excess minority carrier charge is:

• Since the diode current is it is more convenient to express the excess charge as:

Qd Q p Qn I p p I n n

Qd T

Id

(where T

is called mean transit time )

Id

Ip

In

Diffusion Capacitance

Cd

dQd

dVd V

D

dT

Id

dVd V

D

T

dId

dVd V

D

T

rd

1

rd

dId

dVd V D

d Is

e

V d

V T1

dVd V D

Ise

V d

V T

VT V D

Id

Is

VT V D

Id

VT V D

Cd T

Id

VT V D

Transition Time

• The general expression for T is quite cumbersome:

T

Cd

rd

where1

r d

dI d

dV d V D

Cd

d Qd

d Vd V D

with Qd

q Ani

2

L p

ND

q Ani

2

Ln

NA

e

Vd

VT

1

with Id

q A Dn

Ln

ni

2

NA

q A D p

L p

ni

2

ND

e

Vd

VT

1

Transition Time

• In practice, since usually diodes are single sided (i.e. one side will be much more heavily doped than the other side) the minority charge storage in the heavily doped side can be ignored

• Assuming the P side is more heavily doped than the N side:

Qn

q A ni

2L

n

NA

e

Vd

VT

1

NA

ND

Q p Qn

Qd

Q p Id

I p

T p

L p

2

D p

Q p

q A ni

2L p

ND

e

Vd

VT

1

NOTE: •Holes (Qp) are minority carriers on the N side• Electrons (Qn) are minority carriers on the P side

Single Sided Diodes

• One side of the diode is more heavily doped than the other

• Many of the junctions encountered in integrated circuits are one-sided junctions with the lightly doped side being the substrate or the well.

• Foe single sided diodes the depletion region will extend mostly on the lightly doped side.

• The depletion capacitance is almost independent of the doping concentration on the heavily doped side

Single Sided Diodes

• The PN junctions inside CMOS ICs are single-sided

• NMOS transistors have parasitic diodes with the N side more heavily doped than the P side:

• PMOS transistors have parasitic diodes with the P side more heavily doped than the N side:

• NOTE: in general within an MOS transistor, it is undesirable to have a forward biased junction, it usually means there is a problem.

ND

NA

NA

ND

Schottky Diodes

• A different type of diode, can be realized by contacting a metal to a lightly doped semiconductor region.

• The use of a lightly doped semiconductor, causes a depletion region to form at the interface between the aluminum anode and the n+ silicon region

Schottky Diodes

• The voltage drop of a forward biased Schottky diode is smaller. The value depends on the metal used. For aluminum is approx 0.5 V

• When the diode is forward biased there is no minority charge storage in the lightly doped n+ region. Thus Cd = 0

• The absence of diffusion capacitance makes the diode much faster.

Diodes realized in CMOS technology

NOTE: For the case of Fig 14.54(a) the anode is inevitably grounded

Diode SPICE model

Diode SPICE Modeling

Id

Is

expV

d

nVT

1 GMIN Vd

Convergence Aid

Id

Is

expBV V

d

VT

1BV

VT

Id

Is

GMIN Vd

IS (BV/VT)

MOS physical structure

Thermal Equilibrium

• Absence of any stimulus to the device

• The populations of electrons and holes are each in equilibrium and, therefore must have zero current densities

0 q n0 n

E0

q Dn

Dn0

dx

0 q n0 p

E0

q Dp

dp0

dx

0 n0 n

d0

dxD

n

dn0

dx

d0

Dn

n

dn0

n0

d0

VT

dn0

n0 xR

x

d0

VT

xR

x

dn0

n0

0x

0x

RV

Tln

n0

x

n0

xR

Thermal Equilibrium

0x

0x

RV

Tln

n0

x

n0

xR

By convention the reference for the potential is chosen to be the point where the carrier concentration is the intrinsic concentration

0 x V T lnn0 x

ni

0x

R0 when n

0x

Rn

i

NOTE: for N type silicon since n0 > n

i the electrostatic potential at equilibrium is positive

n0

x nie

0x

V T

Thermal Equilibrium

A similar derivation for the hole concentration leads to the following result:

0 x V T lnp0 x

ni

NOTE: for P type silicon since p0 > ni the electrostatic potential at equilibrium is negative

p0

x nie

0x

V T

source/drain/bulkgate

Figure. Using the MOSFET as a capacitor

At equilibrium the p- substrate and the n+ source and drain form a pn junction. Therefore a depletion region exists between the n+ source and drain and the p- substrate

The gate and the substrate of the MOStransistor form a parallel plate capacitorwith the SiO2 as dielectric

Since source and drain are separated by back-to-back junctions, the resistance between the source and the drain is very high (> 1012 ohm)

MOS Capacitor in Thermal Equilibrium

MOS structure in Thermal Equilibrium

VGB

= 0

n+ pE

0

p V T lnN A

n i

n + V T lnN D

n i

equilibrium potential in the silicon (bulk=substrate)

equilibrium potential inthe polysilicon (gate)

NA

1017

cm-3

ND

3 1019

cm-3

ni

1010

cm-3

n+ p 550mV 420mV 970mV

MOS in Thermal Equilibrium

VGB

= 0

• From the sign of the potential drop across the MOS structure it follows that the electric field points from gate to bulk.

• Therefore, a positive charge must be present on the polysilicon gate and there must be a balancing negative charge in the p-type silicon substrate (the oxide will be considered a charge-free perfect insulator)

n+ p 970mV E0

Charge on the MOS in TE

VGB

= 0

• Since the gate is highly conductive n+ polysilicon the gate charge QG0 can be

thought as a sheet charge located at the bottom surface of the polysilicon gate

• The charge on the p-type silicon substrate QB0 is formed by the immobile

negatively charged acceptor ions (to a depletion depth of Xd0 ) left behind by

the mobile holes repelled by the positive charge on the gate.

0

0

M O S

Charge on the MOS in TE

G0 B0q N

AX

d0units :C cm

2

VGB

= 0

Potential across the MOS in TE

Surface Potential Potential at the SiO2-silicon

interface (x=0)Voltage drop across the oxide

Voltage drop across the depletion regionIn the silicon

Built in Voltage across the MOS structure BUILT-IN n+ p V

ox ,0V B ,0

M O S

Potential across the MOS in TE• The equilibrium potential of a given material is commonly

referred as its Fermi potential

• The Built in voltage across the MOS structure is often expressed in term of the work function between the gate material and the bulk silicon

p F-bulk V T lnN A

nin+ F-gate V

Tln

ND

ni

MS F-gate F-bulk n+ p BUILT-INV

Tln

ND

NA

ni

2

NOTE: This term is referred as the metal-to-silicon work function even though the gate terminal is something other than metal (i.e. polysilicon)

MOS in TE: “fixing” KVL

mn+V

ox ,0V

B0 pm 0

VGB

= 0

Vox ,0

VB0 mn+ pm

n+ p BUILT-IN

MOS in TE

NOTE: for the case of TE thegate and the bulk metal contacts are at the samepotential

n+ p mn+ pm

MOS in TE: Quantitative Analysis

The electric field is confined in the region tox < x < Xd0

The total excess charge in the region tox x Xd0 is zero (neutrality of charge)

oxE

ox sE 0

+

E 0+ ox

s

Eox

Eox

E 0+ s

ox

Boundary condition at the oxide/silicon interface (0 x 0+):

In the oxide ( tox < x < 0) the charge density is zero thus the

field is constant (Eox):

Eox

E 0+

Gauss ' s Law :dE

dx

0

3


dE xq N

A

s

dx

E 0+

E Xdo

dE xq N

A

s 0+

Xdo

dx

In the charged region of the silicon oxide/silicon interface (0+ x < Xd0) the charge density is

constant:

sE X

d0 sE 0

+

q NA

Xd0

E 0+

q NA

s

Xd0

0

Within the same material the electric field will not jump !

Eox

E 0-

E 0+ s

ox

q NA

ox

Xd0

Eox


Within the same material the electric field will not jump !

Eox

GE t

ox

-

G oxE t

ox

+

E tox

+ G

ox

B

ox

q NA

Xd0

ox

Eox

• Just for the sake of double-checking the correctness of the previous result let's also apply the boundary condition at the interface between gate and oxide and see if we get the same result

MOS Potential in TE

Eox

E 0 xd 0 x

dx

s0 00

MOS in TE: Potential in the oxide

d0

x E0

x dx

tox

x 0 :

s0 00

OM S

0x

n+

tox

x

Eox

dxq N

AX

d0

ox tox

x

dxq N

AX

d0

ox

x tox

for tox x 0: 0 x n+

q N A X d0

ox

x t ox

Potential in the oxide

MOS in TE: Potential in the oxide

s0 00

OM S

for tox

x 0:

0x

n+

q NA

Xd0

ox

x tox

Potential in the oxide

s0 0 0 n+

q N A X d0

ox

tox n+

q N A X d0

ox

Surface Potential (Potential at the oxide/silicon interface)

withox

ox

tox

Vox ,0 0

tox 0

0n+ s0

q NA

Xd0

ox

G0

ox

Voltage drop across the oxide

with :

G0 B0q N

AX

do

NOTE: VOX,0 is proportional to the charge stored on each side of the oxide

MOS in TE: potential in the depletion region in the silicon substrate

OM S

dE0

xx

s

dx

depletion region

0 x Xd0

:

E0 0+

E0 x

dE0

x

0+

x

x

s

E0

x E0

0+

0+

x

qNA

s

dxq N

Ax

s

E 0 x E0 0+ qN A x

s

q N A X d0

s

qN A x

s

qN A

s

X do x

E0

0+

q NA

Xd0

s


OM S

charged region

0 x Xd0

:

0 0

0x

d0

x

0

x

E0

x dx 0x

00

0

x

qNA

s

Xdo

x dx

d0

x E0

x dx

Electric Field in the Depletion region

for 0 x Xd0

:

E0

xq N

A

s

Xd0

x

0 x 0 0qN A

s

X do

0

x

dxqN A

s 0

x

x dxqN A

s

X do xx

2

2

0x

00

qNA

s

Xdo

xx

2

2


OM S

charged region

0 x Xd0

:0

x0

0qN

A

s

Xdo

xx

2

2

s0 0 0 n+

q N A X d0

ox

Surface Potential

for 0 x Xd0

:0

xn+

q NA

Xd0

ox

qNA

s

Xdo

xx

2

2

Potential in the depletion region in the substrate


OM S

charged region

for 0 x Xd0

:

0x

n+

q NA

Xd0

ox

qNA

s

Xdo

xx

2

2

Potential in the depletion region in the substrate

0 X d0 p n+

q N A X d0

ox

qN A

2 s

X do

2

n+ p

q N A X d0

ox

qN A

2 s

X do

2Voltage drop across the MOS structure

This must be the voltage drop acrossthe charged region ofthe silicon substrate

Since this is the voltage drop across the oxide

Vox ,0

VB 0

MOS in TE: Width of the Depletion region

OM S

depletion region

Voltage drop across the MOS structure

Voltage drop across the charged region of the silicon substrate

Voltage drop across the oxide

n+ p V ox ,0 V B0

q N A X d0

ox

qN A

2 s

X do

2

Vox ,0

q NA

Xd0

ox

G

ox

B

ox

V B0

q N A

2 s

X do

2q N A

2 s

X do

2 q N A X d0

ox

n+ p 0

Xdo

2q N

A

ox

2s

q NA

Xd0

2s

q NA

n+ p 0 Xdo

22

s

ox

Xd0

2s

q NA

n+ p 0

MOS in TE: Width of the Depletion region

Xdo

22

s

ox

Xd0

2s

q NA

n+ p 0 ax2

bx c 0 xb b

24ac

2a

X do

2 s ox 4 s

2

ox

28 s q N A n+ p

2

s ox s

2

ox

22 s q N A n+ p

s

ox

1 12 s

q N A

ox

2

s

2 n+ p

Xdo

s

ox

12

ox

2

q NA s

n+ p 1

NOTE: Xd0 can be only positive

2

Depletion Width:

MOS under Bias

VGB

0

(FLATBAND) – ACCUMULATION – DEPLETION – (THRESHOLD) INVERSION

Flatband

• We apply a gate to bulk voltage that is opposite to the built-in potential. This special voltage bias is called flat-band voltage

VFB BUILT_IN n+.0 p.0

The bulk metal contact is considered fixed

VGB mn+ pm V

MOS

VGB BUILT-IN

VMOS

VGB

VFB

VMOS

mn+

pm

VMOS

if VGB

VFB

VMOS

0

NOTICE:For an MOS structure with n+ poly-silicon gate and p-type substrate this voltage is negative

Flat-band Voltage

p p,0

n+ n+,0 V GB

n+ p n+,0 V GB p

n+,0 p,0 V GB V FB V GB

Flatband• In flat-band condition (VGB=VFB) there is no internal voltage drop

across the MOS capacitor.

The bulk metal contact is considered fixed

Thermal Equilibrium

Applying VGB = VFB

shifts the gate metal contact

lower by – 970 mV (=VFB)

p = 420 mV ( n+,o = 550 mV)

n+,0 V GB

Flatband

• Since in flat-band condition (VGB=VFB) there is no internal voltage

drop across the MOS capacitor, as a result the electric field is zero and the gate charge density is zero

QG

VGB

VFB

0

capacitance of forward biased diode - gonzaga...

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