buck sr design 1

7/29/2019 Buck SR Design 1

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N.Femia: buck SR design – power components

the step-down (buck)converter

Buck DR Converter

Buck SR Converter

The buck converter is used in two different versions:-the Diode Rectification (DR) buck converter

-the Synchronous Rectification (SR) buck converterThe former requires a simpler control circuitry, as only the control MOSFET must be driven. Due to the forward voltage drop of diodes, the buck-DR can bepreferable in low-current and high duty-cycle applications. A furtherdisadvantage is the possible operation in discontinuous conduction mode, whichcan be prevented at the price of a higher output filter inductance.The buck-SR, instead, is preferred in low-voltage/high-current applications, asthe use of a low-side MOSFET allows a reduction of conduction losses. Moreover,the buck-SR never enters discontinuous conduction mode. It requires a morecomplex control and drive circuitry to manage efficiently and safely theoperation of the two MOSFETs.



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real buck real buck real buck real buck- -- -SR SR SR SR

AD

C

B

5

4

33

2

15

6

The real schematic of a real buck SR is shown in the figure. It includes:-a power components section (A)-a feedback control section (B)

-a drive&control IC (C)-auxiliary components for:-setting switching frequency (D.1)-setting soft-start time (D.2)-FET gate driving (D.3)-current sensing (D.4)-IC supply voltage filtering (D.5)-power enabling (D.6)



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drive&control drive&control drive&control drive&control IC IC IC IC

A

D

C

B

5

4

3

2

1

6

D

A drive&control IC buck SR is shown in the figure. It includes:-FET drive section (A)-PWM section (B)

-feedback error amplifier OP-AMP (C)-auxiliary components for:-current limiting (D.1)-over-voltage and under-voltage protection (D.2)-soft-start (D.3)-power enabling (D.4)-shut-down (D.5)-clock generation (D.6)



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gate drivesgate drivesgate drivesgate drives

A gate drive is shown in the figure. Parasitic inductances have a great impact onFET gate driving.



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LossLess buck DR Q1

D1

VgVo

Vp

Vc

ton

Ts=1/fs

D=ton/Ts

The main waveforms of ideal LossLess buck DR are analyzed for the example inthe figure. The circuit can operate both in Continuous Conduction Mode (CCM)

and Discontinuous Conduction Mode (DCM), due to the diode current blockcapability.



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LL-buck DR waveforms (CCM)(D=0.545,L=4.7µH,Io=2A,fs=300kHz)

Vg

D1

Q1Vo

ton

Ts=1/fs

D=ton/Ts

the figure shows the waveforms of:-inductor current

-switch current-diode current-output voltagefor buck DR



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LL-buck DR waveforms (CCM)output current balance

the figure shows the waveforms of:-inductor current-output capacitor current

-load currentIdeally, the output capacitor should be able to by-pass the entire ripplecomponent of inductor current, so that the load sinks only the dc component ofinductor current. This condition is never met exactly in practice, as it wouldrequire an output capacitor with zero series resistance ESR and infinitecapacitance C. However, residual ripple current flowing through the load can bereduced to very low levels by means of proper selection of inductor and outputcapacitor.



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LL-buck DR waveforms (CCM)input current balance

the figure shows the waveforms of:-switch current-diode current

-line currentIdeally, the input capacitor should be able to by-pass the entire ripple componentof switch current, so that the source feeds only the dc component of switchcurrent. This condition is never met exactly in practice, as it would require aninput capacitor with zero series resistance ESR and infinite capacitance C.However, residual ripple current flowing through the load can be reduced to verylow levels by means of proper selection of input capacitor.



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real components: capacitors

All real components are affected by power losses. The main parameter related tolosses, which is common to all components, is the series resistance.



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Lossy buck DR

A more realistic schematic of buck DR converter including losses is shown in thefigure.



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steady-state Lossy buck DR

(Dlossy=Dlossless=0.545)

(Vo_lossy=1.4V<Vo_lossless=1.8V)

green = lossless, blue = lossy@rg=1mΩΩΩΩ, red = lossy@rg=100mΩΩΩΩ

The main effect of losses, besides power dissipation in itself, is a decrease ofoutput voltage.



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(Dlossless=0.545<Dlossy=0.665)

(Vo_lossy=Vo_lossless=1.8V)

Achieving a determined output voltage for a given input voltage and load currentrequires a value of duty-cycle which increases with losses.



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Ig_lossy = 1.33A > Ig_lossless = 1.09A

Losses cause an increase of source current, and then of source power, requiredto supply the power required by the load.



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perturbed Lossy buck DR

The figure shows an open-loop buck-DR with perturbations on input voltage Vg,output current Io and control voltage Vc.



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Open-loop operation involves:-a dependence of the output voltage on input voltage Vg, output current Io and

control voltage Vc-surges and oscillations during the transients



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DC, ac and ripple components

All waveforms of voltage and currents in switching regulators include threecomponents:-a steady-state average component (DC), X

-a transient average component (ac), x’(t)-a ripple component, x’’(t)the total waveform is x(t)=X+x’(t)+x’’(t).



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DC, ac and ripple components

All waveforms of voltage and currents in switching regulators include threecomponents:-a steady-state average component (DC), X

-a transient average component (ac), x’(t)-a ripple component, x’’(t)the total waveform is x(t)=X+x’(t)+x’’(t).



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Vref

Vout

voltage-controlled voltage-source

ioutv in+

-

The goal of voltage regulator design is to allow the converter to operate as closeas possible like a lossless voltage controlled voltage source, so that output

voltage is adequately immunized against source and load perturbations.



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Design specifications

DC SPECIFICATIONS

• Vi ∈∈∈∈ [Vi_min,Vi_max]

• Vo ∈∈∈∈ [Vo_min,Vo_max]

• Io ∈∈∈∈ [Io_min,Io_max]

• ηηηηmin@Io_max

AC SPECIFICATIONS

• ∆∆∆∆Vo Vi_minVi_max

• ∆∆∆∆Vo Vi_maxVi_min

• ∆∆∆∆Vo Io_minIo_max

• ∆∆∆∆Vo Io_maxIo_min

• fs ∈∈∈∈ [fs_min,fs_max]

• ∆∆∆∆Vo_pp_max

, ∆∆∆∆Vi_pp_max• ∆∆∆∆Io_pp_max, ∆∆∆∆Ii_pp_max

• fc ∈∈∈∈ [fc_min,fc_max]

• ϕϕϕϕm

∈∈∈∈ [ϕϕϕϕm_min

, ϕϕϕϕm_max

]

• T i|fs, T v |fs

POWER DEVICES CONTROL DEVICES

The buck converter must fulfill two types of design constraints:Customer’s application specifications:-[Vi_min,Vi_max]=input voltage range-

[Vo_min,Vo_max]=output voltage range-[Io_min,Io_max]=output current range-∆Vo_reg= output voltage regulation window-∆tos/us_max= maximum overshoot/undershoot time above VoDesigner’s choices:-switching frequency fs-∆Vo_pp_max= maximum output capacitor voltage ripple-∆Vi_pp:_max= maximum input capacitor voltage ripple-∆iL_pp_max= maximum output inductor current ripple-∆ii_pp_max= maximum input inductor/line current ripple-control type (voltage/current mode, etc.) and dynamic constraintsMost of designer’s choices are usually made either on the basis of personalexpertise or on the basis of design hints proposed in manufacturers applicationnotes



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traditional power traditional power traditional power traditional power stage design stepsstage design stepsstage design stepsstage design steps

Customer/application specifications analysis

Loss analysis ⇒ MOSFET/diode

Numerical simulations and preliminary test

Ripple/transient analysis ⇒ passive components

Prototyping and final experimental test

Market

The traditional design of the buck converter usually starts with the powerdevices design. This is pretty right, provided that the reciprocal influencebetween power devices design choices and control design choices and their joined

impact on the overall static and dynamic converter’s performances areconsidered, especially in applications where output voltage immunity to loadtransients is an issue.Wrong choices concerning device models and design equations, switchingfrequency, loss distribution among devices, ripples and load transient constraintsand other issues related to operating parameters, device parameters andparasitic parameters, may bring the designer to loop into the design processbecause of either technical or market inadequacy of the design solution



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Example: Example: Example: Example: singlesinglesinglesingle- -- -load buck load buck load buck load buck- -- -SR SR SR SR

Power Management IC’s manufacturers often provide solutions for POLconverters related to most diffused standard applications.



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POWER COMPONENTS

Selections of commercial devices for power stage components are suggested.The IC application notes also provide information about the assumptions andequations adopted to figure out the main parameters of the power stage devices.



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CONTROL COMPONENTS

Selections of commercial devices for control circuitry components are alsosuggested. The IC application notes also provide the basic assumptions andequations adopted to figure out the parameters of the control stage devices.



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Example: buck-SR farmfor IBDA architecture

12,512,510,410,49,89,88,88,8Po5,05,05,85,88,28,28,08,0Io

2,52,51,81,81,21,21,11,1Vo

isolatedconverter

POL1 POL2 POL3 POL4

3.3V bus

IC manufacturers design examples often offer acceptable solutions for standardapplications.In many applications, such as Point Of Load (POL) converters for Intermediate

Distributed Bus Architecture supply systems, there is the need of figuring outdesign solutions ensuring high static and dynamic performances, low cost, andhigh power density.



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Power Management: FPGA

Powerdevices

Controldevices

FPGA systems are typical applications where a number of different converters mustbe designed for supplying the system with different voltages and currents. Whilethe low-current inputs can be fed by linear regulators, the high-current inputs

require high efficiency switching regulators. These latter are made by differenttypes and number of power devices to comply with the power specifications, andcontrol components are also strongly conditioned by the dynamic constraints of thespecific application. Each buck switching regulator looks very simple by a circuitpoint of view: nevertheless, its design is becoming a challenging task under theheavy pressure of low-cost/small-size market targets.



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power devices power devices power devices power devicescharacteristics

dielectric losses,..Vmax, Irms, C, ESRcapacitor

core losses,..Vmax, Irms, Isat, L, ESRinductor

reverse recovery,..VBD, IF, VFdiode

switching losses,..VDS, ID, VGS, RDS(on)MOSFET

other characteristics main parameters device

The selection of components is firstly conditioned by the fulfillment ofcurrent/voltage ratings imposed by the application. Besides the principalparameters identifying the device (capacitance, inductance), parasitic

parameters responsible of losses also characterize the device (MOSFET channelresistance, capacitor’s and inductor’s ESR). Parasitic parameters to beconsidered in high-current/high-frequency applications include MOSFET gatecharge and inductors core losses. The overall static performances of buck-SRare heavily conditioned by the combination of all parasitic parameters ofcommercial components. Designer’s capability must be improved in figuring outnot just a single optimum design solution for the given application, but rather avariety of nice design solutions, based on different sets of commercialcomponents, among which the most suitable for the overall final productexpectations can be selected.



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power MOSFETs

double diffused asymmetrical

trenchFET

Power MOSFETs are responsible for most of power losses in high-current/high-frequency buck converter applications. Several types of MOSFETs are availabletoday, which offer different trade-off solutions between conduction and

switching losses. This allows to figure out adequate solutions in very-low outputvoltage POL applications (e.g. 12V to 1.2V) where duty-cycle is very low, as well asin medium-high duty-cycle applications where output and input voltages are notmuch different.DirectFET, HEXFET, CoolMOS and other proprietary technologies have beenintroduced by manufacturers on the market during last years, which offer verylow on-resistance, down to 1mΩ, and low gate charge, down to 1nC, withcorresponding drop of switching times down to few ns.



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MOSFET channel resistance

The main parameters conditioning MOSFET switching losses are:-channel resistance-parasitic capacitances-

gate-source threshold voltage-gate resistance-forward voltage drop of body diode-parasitic inductancesThe MOSFET’s on drain-to-source resistance is one of the most importantparameters in the determination of losses. It depends on the gate-to-sourcevoltage, the junction temperature and the drain current. The value of drain-to-source resistance affects the conduction losses, as well as the switchinglosses. In fact, its value contributes to determine the junction temperatureand this influences the parameters involved in the determination ofswitching losses. In general, the loss model of the MOSFET to be adopted inorder to get realistic values of losses must necessarily account for joinedeffects of conduction and switching losses.The parasitic internal inductances of MOSFETs, deriving from internal

wiring to package pins, are also important parameters conditioning switchinglosses. In some cases manufacturers provide values of such parasiticinductances. The true switching waveforms of MOSFET’s voltage andcurrent may exhibit not negligible oscillations because of parasiticinductances, whose values may range in the order of hundreds of pH. Theseinductances must be summed to external trace stray inductances andresistances for the analysis of switching waveforms.



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MOSFET: capacitances

CGD= CGD0/(1+αααα√√√√VDS)= CRSS

CDS= CDS0/(1+ββββ√√√√VDS)= COSS-CRSS

CGS

= CISS

-CRSS

The MOSFET’s parasitic capacitances are the most important parametersconditioning MOSFET switching times. The capacitances CGS and CGD are conditioned

by the geometry of the device: they depend inversely on drain-to-source voltage.The capacitance CDS characterizes the MOSFET’s parasitic bipolar transistor. Noneof the MOSFET’s physical capacitances are directly provided in devices datasheets.They can be obtained from the values of measurable capacitances CISS, COSS andCRSS, whose plots vs drain-to-source voltage are provided by manufacturersdatasheets.



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MOSFET: switching times

Although MOSFETs datasheets include values of switching times measured atspecific test conditions, such values are purely indicative, as the switching timesmay change considerably with MOSFET operating conditions.



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MOSFET: total gate charge

2

2 in s oss

Coss V f C

P = dr s g gate V f Q P = in s rr rr V f Q P =

Components’ datasheets include total gate charge values and related plots vs the

gate-to-source voltage, which can be used to determine values of switching times

for each application. Additional possible MOSFET commutation losses derivefrom output MOSFET capacitance Coss charging/discharging, from gate

charge/discharge and from body-diode reverse recovery. Such losses are much

smaller, in most cases, with regard to the switching losses depending on the total

gate charge Qg.



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MOSFET: gate-sourcevoltage

The threshold gate-to-source voltage depends on the operating temperature.The temperature coefficient of threshold voltage is negative and typicallyranges from –3mV/°C to -7mV/°C. Power MOSFETs are usually used at as high

current as possible in their current rating range, so that their junctiontemperature rises often beyond 100 degrees centigrade. Thus, the thresholdvoltage value must be calculated at the expected MOSFET operating junctiontemperature in order to estimate switching times in worst case conditions. Somemanufacturers provide only the temperature coefficient of threshold voltage,whereas other ones provide a temperature plot.



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MOSFET: transconductance

gFS=dID/dVGSID=(VGS-Vth)gFS

VGS,Miller=Vth+ID/gFS

The MOSFET’s trans-conductance is an important parameter in thedetermination of switching times, as it determines the value of the Miller plateaugate-to-source voltage during the commutation. Manufacturers provide its value

in datasheets, and in some cases also its dependence upon temperature.



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High-Side (HS) MOSFET: ohmic losses

∆+=

22

_ 121

1o

Lpp o ds HS c I

i DI R P

iLo

Iom

IoM

2 _ rms ds HS c I R P =

The losses of high-side and low-side MOSFETs in buck-SR can be much differentdepending on the application. They must be analyzed separately.High-side MOSFET conduction losses depend on channel resistance and duty-

cycle. The impact of peak-to-peak inductor current ripple is not much importantuntil it reaches the value of average inductor current (100% ripple). Channelresistance RDS is the most important MOSFET’s parameter for high-side ohmiclosses.



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HS MOSFET: turn on switching losses

VGS

VDS

IDS

Vdr

t1 t2 t3 t4

Vsp

Vth

Qg,sw

Turn-on high-side MOSFET switching losses depend on input voltage, switchingfrequency, load current, peak-to-peak inductor current ripple and switchingtimes. The impact of peak-to-peak inductor current ripple can be important when

it approaches the value of average inductor current (100% ripple). Switchingtimes depend on gate current, which in turn is dependent on the total gateresistance.



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HS MOSFET: turn on switching losses

gLH

spLH dr gLH R

V V

I

−

=

FS

om th spLH g

I V V +=

VGS

VDS

IDS

Vdr

t1 t2 t3 t4

Vsp

Vth

LH om s LS f in swLH t I f V V P )( ,21 +=

RgHL=Rgdrv +Rgext+Rgint

Lpp o om i I I ∆−= 21

gLH

sw g LH I

Q t ,=

Qg,sw

Turn-on high-side MOSFET switching losses depend on input voltage, switchingfrequency, load current, peak-to-peak inductor current ripple and switchingtimes. The impact of peak-to-peak inductor current ripple can be important when

it approaches the value of average inductor current (100% ripple). Switchingtimes depend on gate current, which in turn is dependent on the total gateresistance.



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HS MOSFET: turn off switching losses

VGS

VDS

IDS

Vdr

t1 t2 t3 t4

Vsp

Vth

Qg,sw

Turn-off high-side MOSFET switching losses also depend on input voltage,

switching frequency, load current, peak-to-peak inductor current ripple and

switching times. The gate charge Qg is the most important parameter forMOSFETs switching losses. Switching times depend on gate current, which in

turn is dependent on the total gate resistance.



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HS MOSFET: turn off switching losses

VGS

VDS

IDS

Vdr

t1 t2 t3 t4

Vsp gHL

spHL

gHL R

V

I =

FS

oM th spHL g

I V +=

Vth

HL oM s LS f in swHL t I f V V P )( ,21 +=

RgHL=Rgdrv +Rgext+Rgint

Qg,sw

Lpp o oM i I I ∆+= 21

gHL

sw g HL I

Q t ,=

Turn-off high-side MOSFET switching losses also depend on input voltage,

switching frequency, load current, peak-to-peak inductor current ripple and

switching times. The gate charge Qg is the most important parameter forMOSFETs switching losses. Switching times depend on gate current, which in

turn is dependent on the total gate resistance.



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Low-Side (LS) MOSFET: ohmic losses

∆+−=

22

_ 121

1)1(o

Lpp o ds LS c I

i I D R P

iLo

Iom

IoM

2 _ rms ds LS c I R P =

Low-side MOSFET conduction losses depend on channel resistance and duty-

cycle. The impact of peak-to-peak inductor current ripple is not much important

until it reaches the value of average inductor current (100% ripple). The channelresistance RDS is the main MOSFET’s parameter determining low-side ohmic

losses.



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LS MOSFET: turn on switching losses

VGS

VDS

IDS

Vdr

t1 t2 t3 t4

Vsp

Vspec

Vth

tdtLH

-VF

-R DS IoM

-2R DS IoM

-IM

Turn-on low-side MOSFET switching losses depend on body-diode forward

voltage, switching frequency, load current, peak-to-peak inductor current

ripple, input MOSFET capacitance Ciss and switching times. The impact ofpeak-to-peak inductor current ripple can be important when it approaches the

value of average inductor current (100% ripple). Switching times depend on

total gate resistance and on the minimum specified gate-to-source voltage

Vspec, which may range from 1.8V to 4.5V depending on the type of MOSFET,

and on the corresponding drain-to-source on resistance of the MOSFET at

that voltage Rspec, which usually equals two times the nominal on drain-to-

source resistance RDS. In the following, it will be assumed that Vspec=2.5V and

Rspec=2Rds.



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[ ] s oM oM ds LH f swLH f I t I R t V P 3221 +=

−

−=

spec dr

th dr iss gLH LH V V

V V C R t ln

−

−=

spec dr

sp dr iss gLH V V

V V C R t ln3

2/Lpp o oM i I I ∆+=

LS MOSFET: turn on switching losses

VGS

VDS

IDS

Vdr

t1 t2 t3 t4

Vsp

Vspec

Vth

tdtLH

-VF

-R DS IoM

-2R DS IoM

-IM

Turn-on low-side MOSFET switching losses depend on body-diode forward

voltage, switching frequency, load current, peak-to-peak inductor current

ripple, input MOSFET capacitance Ciss and switching times. The impact ofpeak-to-peak inductor current ripple can be important when it approaches the

value of average inductor current (100% ripple). Switching times depend on

total gate resistance and on the minimum specified gate-to-source voltage

Vspec, which may range from 1.8V to 4.5V depending on the type of MOSFET,

and on the corresponding drain-to-source on resistance of the MOSFET at

that voltage Rspec, which usually equals two times the nominal on drain-to-

source resistance RDS. In the following, it will be assumed that Vspec=2.5V and

Rspec=2Rds.



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LS MOSFET: turn off switching losses

VGS

VDS

IDS

Vdr

t1t2t3t4

Vsp

VthtdtHL

-VF

-Im

-R DS Iom

-2R DS Iom

Vspec

Turn-off low-side MOSFET switching losses depend on body-diode forward

voltage, switching frequency, load current, peak-to-peak inductor current ripple,

input MOSFET capacitance Ciss and switching times. The impact of peak-to-peakinductor current ripple can be important when it approaches the value of average

inductor current (100% ripple). Switching times depend on total gate resistance

and on the minimum specified gate-to-source voltage Vspec.



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LS MOSFET: turn off switching losses

[ ] s om HL om ds HL f swHL f I t I R t V P 3221 +=

=

th

spec iss gHL HL V

V C R t ln

=

sp

spec iss gHL HL V

V C R t ln3

2/Lpp o om i I I ∆−=

VGS

VDS

IDS

Vdr

t1t2t3t4

VspVspec

VthtdtHL

-VF

-Im

-R DS Iom

-2R DS Iom

Turn-off low-side MOSFET switching losses depend on body-diode forward

voltage, switching frequency, load current, peak-to-peak inductor current ripple,

input MOSFET capacitance Ciss and switching times. The impact of peak-to-peakinductor current ripple can be important when it approaches the value of average

inductor current (100% ripple). Switching times depend on total gate resistance

and on the minimum specified gate-to-source voltage Vspec.



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LS MOSFET: body diodedead-time losses

)( oM dtLH om dtHL s f dt I t I t f V P +=

Low-side MOSFET switching losses are also conditioned by the body-diode

conduction during the dead-time programmed to avoid cross conduction of high-

side and low-side MOSFETs. Such losses increase with dead-time duration, whichcan be either fixed (usually few tens of nanoseconds) or adaptive, depending on

the drive’s technology.

Dead-time losses may impose severe restrictions on other losses to contain total

MOSFET losses within a fixed limit.

.



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HS MOSFET: losses summary

[ ]HL oM LH om s in sw t I t I f V P +=21

∆+=

22

121

1o

Lpp o ds cond I

i DI R P

2

2 in s oss

Coss V f C

P =

dr s g gate V f Q P = in s rr rr V f Q P =

rr gate Coss sw cond dHS P P P P P P ++++=

[ ] gHL oM gLH om g s in sw I I I I Q f V P //21

+=

Total high-side MOSFET losses can be expressed as a function of application

specifications Vi, Vo, Io, design parameters ∆iLpp, fs, driver’s parameters RgHL,

RgLH, Vdr and MOSFET’s parameters RDS, Qg, Vth, gfs, Vspec. The main losses canbe identified in conduction losses (Pcond) and switching losses (Psw). The main

parameters conditioning these losses are the drain-to-source resistance RDS and

the gate charge Qg, which are also related to each other by the device

technology.

Thus, the choice of a specific device to be used as high-side MOSFET can be

done by matching two different curves relating RDS to Qg, the first one coming

from design specifications and constraints and the other one coming from

commercial components databases.



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LS MOSFET: losses summary

dt swLH swHL cond dLS P P P P P +++=

)( oM dtLH om dtHL s f dt I t I t f V P +=

∆+−=

22

121

1)1(o

Lpp o ds cond I

i I D R P

[ ] s oM LH oM ds LH f iss swLH f I I R V C P 3221

β α +=

[ ]s om HL om ds HL f iss swHL

f I I R V C P 3

22

1 β α +=

Total low-side MOSFET losses can be expressed as a function of application

parameters Vi, Vo, Io, ∆iLpp, fs, driver’s parameters RgHL, RgLH, Vdr and

MOSFET’s parameters RDS, Ciss, Vth, Vspec. The main losses can be identified inconduction losses (Pcond) and switching losses (Psw). The main parameters

conditioning these losses are the drain-to-source resistance Rds and the input

capacitance Ciss, which are also related to each other by the device technology.

Thus, the choice of a specific device to be used as low-side MOSFET can be done

by matching two different curves relating RDS to C iss, the first one coming from

design specifications and constraints and the other one coming from physical

devices databases.

The total low-side MOSFET losses can be written in explicit form as a function

of all the aforementioned parameters.

The expression of total losses is quite involved. If the peak-to-peak inductor

current ripple is neglected, an easier expression is obtained.



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parameters summary

application:

Vi, Vo, Io, η, D

gate driver/IC:gate driver/IC:

Vdr, Rgdr

MOSFET family:

gFS, Vth, Rgint

operating conditions:fs, Pdhs, Pdls

∆iLpp, ∆Vopp, ∆Vipp

MOSFETs’ figures of merit: Rds, Qg, Ciss

A summary of the parameters involved in the equations for the calculation of

MOSFET losses can be done by grouping them in five different categories.

The application parameters are fixed by the design specifications.The gate driver parameters are fixed by the driver or by the IC adopted to

control the converter.

The trans-conductance, the threshold gate-source voltage and the internal gate

resistance of the MOSFET depend on the family of devices selected. A unique

value to each of them cannot be given: nevertheless, the average value over the

selected group of devices can be calculated and later verification can be done

after specific devices have been chosen.

Operating conditions parameters are the goal of our design, together with the

power devices to be selected.

The last group of parameters can be considered as “figures of merit” of

MOSFETs as they are the ones which mostly determine the losses in these

components.

The design approach we are going to analyze uses these figures of merit to

search the best combination of real power MOSFET and operating conditions

parameters making the converter complying with the design specifications.



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WARNINGS

•Effects of inductances of traces:⇒⇒⇒⇒ do a good layout design!

Attention!

•Thermal verification of the selected MOSFETs:

T j=T a+Rθ jaPd(Rds(T j),Vth(T j),gFS(T j))

Pd≅Pcond(Rds(T j))+Psw(Vth(T j),gFS(T j))

•Losses verification of the selected MOSFETs:⇒⇒⇒⇒ replace average values of Vth, gFS and Rgint with thespecific ones

•Additional losses of high-side MOSFET:⇒⇒⇒⇒ consider all losses at high switching frequency (>MHz)

The MOSFET selection approach presented in the previous pages is completed aftersome verification is made:

•the minor losses related to output capacitance Coss (½CossVDS2

fs), to the gatecharge (QgVdrfs) and to possible diode reverse recovery (QrrVDSfs) must beevaluated;

•the values of Vth, gFS and Rgint for the specific MOSFETs selected must beconsidered in the calculation of the losses;

•the thermal verification is required to ensure that the operating junctiontemperature is lower than the maximum allowed one for the use of a heat sink is notnecessary: in this context some iterative calculation is required, as the junctiontemperature is a function of the total MOSFET’s losses and these, in turn, dependon the temperature. So that, starting from a given T j guess (the one adopted toextract the values of RDS used in the RDS vs Qg and RDS vs Ciss plots), the lossesare calculated and a new T j guess is obtained, and the process is repeated until

convergence (usually, no more than three/four iterations are required). The missingconvergence is indicative of wrong MOSFET selection (e.g. too high thermalresistance).

A final remark is necessary about the conditions to be ensured for all the previouscalculations provide results that can be considered realistic: a very good layout mustbe realized, with minimum length of all the traces involved in high-current and high-slew-rate current paths (e.g. gate currents). In fact, a bad layout may causeincrease of switching times and related losses, noise, parasitic couplings and otherdrawbacks discussed later in a specific seminar of this course.



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MOSFET Thermal Analysis

• MOSFETs’ junction temperature depend on ambienttemperature T a on losses and on thermal resistance Rθ ja:

(3) T j = T a + Rθθθθ ja Pd(T j,fs)

• MOSFETs’ losses depend on parameters and on switchingfrequency fs:

(2) Pd(T j,fs) = K0(T j) + fs K1(T j)

• MOSFET’s parameters depend on junction temperature T j:

(1.a) Rds(T j) = Rds@25° ( 1 + dRds/dT j (T j -25°) )

(1.b) Vth(T j) = Vth@25° ( 1 + dVth/dT j (T j -25°) )

(1.c) gFS(T j) = gFS@25° ( 1 + dgFS/dT j (T j -25°) )

The equations for thermal analysis are shown in the figure:•Equations (1) provide the values of physical parameters given the temperature;•Equation (2) provides the losses given the physical parameters and the switching

frequency;•Equation (3) provides the temperature given the losses and the thermal resistanceof the device.The set of equations can be used in several ways to analyze the thermal behavior ofthe device.



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MOSFET-TA: problem #1 given fs and Rθθθθ ja ---> calculates T j and Pd

(3) T j = T a + Rθθθθ ja Pd(T j,fs)

(2) Pd(T j,fs) = K0(T j) + fs K1(T j)

(1) Rds(T j),Vth(T j),gFS(T j)

T j = T a

∆∆∆∆T j < εεεεno yes

T j , Pd

An iterative solution is required if the calculation of operating temperature andlosses is required, given the switching frequency and the thermal resistance of thedevice.



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MOSFET-TA: problem #2 given fs and T j_max ---> calculates Rθθθθ ja_max and Pd

(3) Rθθθθ ja_max = (T j-T a)/Pd(T j,fs)

(2) Pd(T j,fs) = K0(T j) + fs K1(T j)


T j = T j_max

Rθθθθ ja_max ,Pd

Calculation of maximum allowed thermal resistance of the device and operatinglosses for given switching frequency and junction temperature is straightforward.



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MOSFET-TA: problem #3 given Rθθθθ ja and T j_max ---> calculates fs_max and Pd

(3) Pd(T j,fs)=(T j-T a)/Rθθθθ ja

(2) fs_max= (Pd(T j,fs)-K0(T j))/K1(T j)


T j = T j_max

fs_max ,Pd

Calculation of maximum allowed switching frequency and operating losses given thethermal resistance of the device and junction temperature is straightforward.



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MOSFET-TA: problem #4 given Rθθθθ ja and Pd_max ---> calculates fs_max and T j

(3) T j=T a+Rθθθθ jaPd(T j,fs)

(2) fs_max= (Pd(T j,fs)-K0(T j))/K1(T j)


Pd = Pd_max

fs_max ,T j

Calculation of maximum allowed switching frequency and operating junctiontemperature for given thermal resistance and operating losses of the device isstraightforward.

buck sr design 1

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