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“Broadway” microprocessor

The Open University of HKCOMPS260F Group Presentation

The small brain behind the Nintendo Wii

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Contents

• Introduction to Nintendo Wii• Wii hardware• “Broadway” microprocessor

Specifications Similarities with PowerPC 750CL CPU

– Why people keep saying it so? Hardware architecture of PowerPC 750CL CPU Interesting stuff regarding Wii

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Introducing Nintendo Wii

• Introduced in November 19, 2006 • What makes it successful?

Motion sensing games• Over 67 Million units sold

(as of end of 2009)• Backward compatible

with Nintendo GameCube (!!)

Source: Wikipedia, Licensed under CC-by-sa 3.0.

Original creator: Jecowa

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Wii titles

And many more…But hey!! This is not a Wii sales presentation!And so we move on…

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The hardware of Wii

“Hollywood”

GPU & I/O

Bluetoothmodule

SD Cardslot

GameCube controller ports

Wi-F

iM

odul

e

GameCube memory card slot

USB

“Broadway”

µP

RAM

RCA portSensor bar port

Image source: http://techon.nikkeibp.co.jp/article/NEWS/20061120/123997/

6Image source: http://techon.nikkeibp.co.jp/article/NEWS/20061120/123997/

“Broadway”microprocessor

A closer shot…

“Hollywood”GPU & I/O

64 MbytesGDDR3 RAM

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“Broadway” processor

• No extensive public specifications list – basically we know nothing about it!

• Nintendo only says: It operates at 729 MHz frequency It’s a PowerPC processor from IBM

• Previous generation Nintendo GameCube also use PowerPC processors: Custom version of IBM PowerPC 750CXe

• So people start speculating about the chip…• And they come up with…

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IBM PowerPC 750CL processor

• Why?• Direct die-shrink of PowerPC 750CXe/enhanced version

PowerPC 750CXe: Made on 180 nm process PowerPC 750CL: Made on 90 nm SOI process

• Remember backwards compatibility with Nintendo GameCube mentioned in slide #3? CPU used in GameCube is custom version of PowerPC

750CXe at frequency of 486 MHz, so this is the same casefor the CPU used in Wii

• Same processor family and the same Power Architecture based

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But…

• Something is not inline with their assumptions: Bus frequency (datasheet says 240 MHz for PPC 750CL) Multiplier (a.k.a. bus-to-core frequency ratio) CPU frequency (“Broadway” at 729 MHz)

• Some quick math: 729/240 = 3.0375, but processor only supports multipliers

such as 3.0x or 3.5x 729/3 = 243 MHz should be the bus frequency of “Broadway”

and 3 is the multiplier (more on this later…)• So we assume the same with “Broadway” – a custom

version of PowerPC 750CL processor…

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(Source: http://wiibrew.org/w/images/a/aa/Wii_hw_diagram.png)

Simplified Wii Hardware Diagram

88 MB Total System memory

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IBM PowerPC 750CLSpecifications

• Based on PowerPC architecture – an RISC design

• CPU frequency: 400 MHz to 1 GHz• Bus frequency: 50 MHz to 240 MHz• Voltage:

0.95V to 1.25V (CPU), 1.15V/1.8V (I/O)

• Power consumption: 1.7W @ 400 MHz5.6W @ 900 MHz

• Widely used in embedded computing systems

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IBM “Broadway” features

• CPU Frequency: 729 MHz • Bus to main memory: 243 MHz, 64 bits

Maximum bandwidth: 1.9 GB/s• Multiplier: 3.0 x• CPU design

Superscalar microprocessor with six execution units Two, 32-bit integer/fixed-point units (IU/FXU) One floating point unit (FPU)

supports single precision (32-bit) and double precision (64-bit)

Branching unit System register unit Load/store unit

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IBM “Broadway” features

• Caches 32 KB 8-way set-associative L1 instruction cache 32 KB 8-way set-associative L1 data cache (can set up

16-kilobyte data scratch pad) DMA unit (15-entry DMA request queue) used by 16-

kilobyte data scratch pad Write-gather buffer for writing graphics command

lists to the graphics chip Onboard 256-kilobyte 2-way set-associative L2

integrated cache Supports three L2 cache fetch modes: 32-Byte, 64-Byte,

and 128-Byte.

• Supports bus pipeline depth levels: level 2, level 3, and level 4.

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So, the features of IBM “Broadway”

• Instruction per cycle (IPC)– The FPU supports paired single floating point (FP/PS) – The FPU supports paired single multiply add (ps_madd). Most

FP/PS instructions can be issued in each cycle and completed in three cycles.

– Fixed-point to floating-point conversion can be performed at the same time as FPU register load and store, with no loss in performance.

• Branch prediction– static branch prediction and – dynamic branch prediction

• Program execution– When an instruction is stalled on data, the next instruction

can be issued and executed. All instructions maintain program logic and will complete in the correct program order.

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IBM Pow

erPC 750CL/”Broadway”

Block Diagram

(Source: IBM datasheet)

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IBM Pow

erPC 750CL/”Broadway”

Hardw

are Registers List (partial)

Name Number Description GQR0 912 (0x390) Graphics Quantization Register 0

GQR1 913 (0x391) Graphics Quantization Register 1

GQR2 914 (0x392) Graphics Quantization Register 2

GQR3 915 (0x393) Graphics Quantization Register 3

GQR4 916 (0x394) Graphics Quantization Register 4

GQR5 917 (0x395) Graphics Quantization Register 5

GQR6 918 (0x396) Graphics Quantization Register 6

GQR7 919 (0x397) Graphics Quantization Register 7

HID0 1008 (0x3F0) Hardware Implementation-Dependent register 0

HID1 1009 (0x3F1) Hardware Implementation-Dependent register 1

HID2 920 (0x398) Hardware Implementation-Dependent register 2

HID4 1011 (0x3F3) Hardware Implementation-Dependent register 4

L2CR 1017 (0x3F9) Layer 2 cache Control Register

MMCR0 952 (0x3B8) Monitor Mode Control Register 0

MMCR1 956 (0x3BC) Monitor Mode Control Register 1

PMC1 953 (0x3B9) Performance Monitor Counter register 1

PMC2 954 (0x3BA) Performance Monitor Counter register 2

PMC3 957 (0x3BD) Performance Monitor Counter register 3

PMC4 958 (0x3BE) Performance Monitor Counter register 4

WPAR 921 (0x399) Write-gather Pipe Address Register

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About the subtitle…

Remember the subtitle of thispresentation?

“The small brain behind the Nintendo Wii”

Why would that be?

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About the subtitle…

Code execution on Wii: “Starlet” chip running an IOS, the chip direct I/Os to the “Broadway” processor when executing the codes

“Starlet” is located in the “Hollywood” chip… And the “Broadway” processor will only do what “Starlet” tells it to do…

Which is a little bit different from our knowledge that an OS must run on the CPU, but interesting nonetheless.

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Thank you

Any questions?

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Backup slides

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Group 4Team 11 – Members

Lam Yuen Chi, HenryLiu Man Chun, TommyMak Chun Yu, PhilYim Chun Kit, Leo

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References• Wikipedia

– http://en.wikipedia.org/wiki/Wii_system_software – http://en.wikipedia.org/wiki/Broadway_(microprocessor)

• Datasheets– IBM PPC 750CL datasheet 1– IBM transition guide PPC 750CL

• Teardowns & Hacks– http://wiibrew.org/wiki/Broadway/Registers – http://techon.nikkeibp.co.jp/article/NEWS/20061120/1239

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