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  • 1. Broadway microprocessor
    The small brain behind the Nintendo Wii
    The Open University of HKCOMPS260FGroup Presentation
    1

2. Contents
Introduction to Nintendo Wii
Wii hardware
Broadway microprocessor

  • Specifications

3. Similarities with PowerPC 750CL CPU Why people keep saying it so? 4. Hardware architecture of PowerPC 750CL CPU 5. Interesting stuff regarding Wii2
6. Introducing Nintendo Wii
Introduced in November 19, 2006
What makes it successful? Motion sensing games
Over 67 Million units sold (as of end of 2009)
Backward compatible with Nintendo GameCube (!!)
Source: Wikipedia, Licensed under CC-by-sa 3.0. Original creator: Jecowa
3
7. Wii titles
And many more
But hey!! This is not a
Wii sales presentation!
And so we move on
4
8. GameCube controller ports
GameCube memory card slot
USB
Bluetoothmodule
HollywoodGPU & I/O
SD Cardslot
RAM
BroadwayP
RCA port
Sensor bar port
Wi-FiModule
The hardware of Wii
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Image source: http://techon.nikkeibp.co.jp/article/NEWS/20061120/123997/
9. HollywoodGPU & I/O
64 MbytesGDDR3 RAM
Broadwaymicroprocessor
A closer shot
Image source: http://techon.nikkeibp.co.jp/article/NEWS/20061120/123997/
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10. Broadway processor
No extensive public specifications list basically we know nothing about it!
Nintendo only says:

  • It operates at 729 MHz frequency

11. Its a PowerPC processor from IBMPrevious generation Nintendo GameCube also use PowerPC processors:

  • Custom version of IBM PowerPC 750CXe

So people start speculating about the chip
And they come up with
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12. IBM PowerPC 750CL processor
Why?
Direct die-shrink of PowerPC 750CXe/enhanced version

  • PowerPC 750CXe: Made on 180 nm process

13. PowerPC 750CL: Made on 90 nm SOI processRemember backwards compatibility with Nintendo GameCube mentioned in slide #3?

  • CPU used in GameCube is custom version of PowerPC 750CXe at frequency of 486 MHz, so this is the same caseforthe CPU used in Wii

Same processor family and the same Power Architecture based
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14. But
Something is not inline with their assumptions:

  • Bus frequency (datasheet says 240 MHz for PPC 750CL)

15. Multiplier (a.k.a. bus-to-core frequency ratio) 16. CPU frequency (Broadway at 729 MHz)Some quick math:

  • 729/240 = 3.0375, but processor only supports multipliers such as 3.0x or 3.5x

17. 729/3 = 243 MHzshould be the bus frequency of Broadway and 3 is the multiplier (more on this later)So we assume the same with Broadway a custom version of PowerPC 750CL processor
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18. 10
(Source: http://wiibrew.org/w/images/a/aa/Wii_hw_diagram.png)
Simplified Wii Hardware Diagram
88 MB Total System memory
19. IBM PowerPC 750CLSpecifications
Based on PowerPC architecture an RISC design
CPU frequency: 400 MHz to 1 GHz
Bus frequency: 50 MHz to 240 MHz
Voltage: 0.95V to 1.25V (CPU), 1.15V/1.8V (I/O)
Power consumption: 1.7W @ 400 MHz5.6W @ 900 MHz
Widely used in embedded computing systems
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20. IBM Broadway features
CPU Frequency: 729 MHz
Bus to main memory: 243 MHz, 64 bits

  • Maximum bandwidth: 1.9 GB/s

Multiplier: 3.0 x
CPU design

  • Superscalar microprocessor with six execution units

21. Two, 32-bit integer/fixed-point units (IU/FXU) 22. One floating point unit (FPU) 23. supports single precision (32-bit) and double precision (64-bit) 24. Branching unit 25. System register unit 26. Load/store unit12
27. IBM Broadway features
Caches

  • 32 KB 8-way set-associative L1 instruction cache

28. 32 KB 8-way set-associative L1 data cache (can set up 16-kilobyte data scratch pad) 29. DMA unit (15-entry DMA request queue) used by 16-kilobyte data scratch pad 30. Write-gather buffer for writing graphics command lists to the graphics chip 31. Onboard 256-kilobyte 2-way set-associative L2 integrated cache 32. Supports three L2 cache fetch modes: 32-Byte, 64-Byte, and 128-Byte. Supports bus pipeline depth levels: level 2, level 3, and level 4.
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33. So, the features of IBM Broadway
Instruction per cycle (IPC)
The FPU supports paired single floating point (FP/PS)
The FPU supports paired single multiply add (ps_madd). Most FP/PS instructions can be issued in each cycle and completed in three cycles.
Fixed-point to floating-point conversion can be performed at the same time as FPU register load and store, with no loss in performance.
Branch prediction
static branch prediction and
dynamic branch prediction
Program execution
When an instruction is stalled on data, the next instruction can be issued and executed. All instructions maintain program logic and will complete in the correct program order.
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34. 15
(Source: IBM datasheet)
IBM PowerPC 750CL/BroadwayBlock Diagram
35. 16
IBM PowerPC 750CL/BroadwayHardware Registers List (partial)
36. About the subtitle
Remember the subtitle of thispresentation?
The small brain behind the Nintendo Wii
Why would that be?
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37. About the subtitle
Code execution on Wii:Starlet chip running an IOS, the chip direct I/Os to the Broadway processor when executing the codes
Starlet is located in the Hollywood chipAnd the Broadway processor will only do what Starlet tells it to do
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Which is a little bit different from our knowledge that an OS must run on the CPU, but interesting nonetheless.
38. Thank you
Any questions?
19
39. Backup slides
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40. Group 4Team 11 Members
Lam Yuen Chi, Henry
Liu Man Chun, Tommy
Mak Chun Yu, Phil
YimChun Kit, Leo
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41. References
Wikipedia
http://en.wikipedia.org/wiki/Wii_system_software
http://en.wikipedia.org/wiki/Broadway_(microprocessor)
Datasheets
IBM PPC 750CL datasheet 1
IBM transition guide PPC 750CL
Teardowns & Hacks
http://wiibrew.org/wiki/Broadway/Registers
http://techon.nikkeibp.co.jp/article/NEWS/20061120/123997/
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