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Brief History. Early ‘80s, US Dept. of Defense project V HSIC H ardware D escription L anguage VHSIC = Very High Speed Integrated Circuit For documentation & specification of ASICs 1987, IEEE standard adopted 1992, standard updated ‘90s to date, highly popular in industry - PowerPoint PPT Presentation


  • Brief HistoryEarly 80s, US Dept. of Defense projectVHSIC Hardware Description LanguageVHSIC = Very High Speed Integrated CircuitFor documentation & specification of ASICs1987, IEEE standard adopted1992, standard updated90s to date, highly popular in industryMain HDL competitor: Verilog, simpler to learnCommonly taught in CEng programs

  • Uses EvolvedDocumentation & specification

    Circuit simulation

    Circuit synthesis

  • Why a language?VHDL largely overlooked while schematic capture reignedMoores Law put schematic capture out of businessText-based modeling attractive suitable input for CAD toolsModeling, simulation, synthesis

  • Is it like C?YesThere are statements, block structure, variables, constants, operators, even ;NoSW programmers follow sequential Von Neumann computation model; butHDL statements translate into logic gates, not instructionsHW is always there, always on, operating concurrently surprises SW people (example later)

  • Three ways to describe circuitStructuralInstantiate specific library components and wire them togetherDataflow (RTL)Instantiate register components from libraryCode combo logic with high-level operations; let VHDL compiler synthesize logic gatesBehaviouralCode algorithm steps; let VHDL compiler infer components, datapath, and controller

  • Basic IngredientsStructureEntity/architectureBehaviourProcessTimingDataSignalVariableLogic values

  • Basic Logic Gatelibrary ieee;use ieee.std_logic_1164.all;

    entity AND_ent isport( x: in std_logic;y: in std_logic;F: out std_logic);end AND_ent;

    architecture behav2 of AND_ent isbegin F

  • Library: Abstract Data TypesIEEE std_logic_1164 valuesUUninitializedXUnknown0Zero1OneZHigh Impedance (tristate not driving output)WWeak UnknownLWeak Zero (low)HWeak One (high)-Dont CareWhy all these??

  • Entity/Architecture PairEntity circuits external interfacePorts function parametersStrongly typed: std_logicMode: in, out, inout (tristate), buffer (out thats readable inside architecture)Architecture internal implementationMultiple implementations allowedCode block: thing beginend thing ;

  • ProcessWrapper for sequential statements( sensitivity list )Tells simulator to re-simulate the process when any member of list changes valueSequential-type statements can only appear inside a process:
  • Result of DescriptionLike OO class definition, entity has to be instantiated in another architectureOne behaviour chosen upon instantiationLibraries full of entity definitions

    If simulation is goal:Both behaviours are identical

    If synthesis is goal (actual AND gate):Should anticipate what circuit compiler will createDifferent from SW where normally trust compiler

  • Combinational Logic Design

    Component Library workentity OR_GATE isport( X:in std_logic;Y:in std_logic;F2:out std_logic);end OR_GATE;

    entity AND_GATE isport( A:in std_logic;B:in std_logic;F1:out std_logic);end AND_GATE;use work.all;

    entity comb_ckt isport( input1: in std_logic;input2: in std_logic;input3: in std_logic;output: out std_logic);end comb_ckt;

    architecture follows outputinput2input3input1

  • Combo Logicarchitecture struct of comb_ckt is

    component AND_GATE isport( A: in std_logic; B:in std_logic; F1: out std_logic ); end component;

    component OR_GATE isport( X: in std_logic; Y:in std_logic; F2: out std_logic ); end component;signal wire: std_logic; -- signal just like wirebegin -- use sign "=>" to clarify the pin mapping

    Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);

    Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);end struct;Label for statement

  • Example of Programmers Surpriseentity port( a, b, c: in bit; X, Y: out bit );signal s: bit:=0;Y
  • Sequential Designentity seq_design isport( a: in std_logic;clock: in std_logic;reset: in std_logic;x: out std_logic);end seq_design;

    architecture FSM of seq_design is -- define the states of FSM model

    type state_type is (S0, S1, S2, S3); signal next_state, current_state: state_type;begin -- concurrent process #1: -- advance state on clock going high state_reg: process(clock, reset) beginif (reset='1') then current_state

  • Sequential Design-- concurrent process #2: -- compute output and next statecomb_logic: process(current_state, a) begin-- use case statement to show the -- state transition

    case current_state is when S0 =>x

  • Many More FeaturesLogic vectors & arraystype mem is array(0 to 127) of std_logic_vector(15 downto 0);Define registers, buses, memoriesVariablesc := a xor b;Temporary value, not intended to generate hardwareTiming statementswait for 10 ns;Used for simulationTest bench code connected to system-under-test can check if timing constraints met/violated

  • Still More FeaturesLibrarieslibrary ieee;Default library = workBuilt-in packages in stdPackageuse ieee.std_logic_1164.all;Binds constants, types, operations into set of abstract data typesConfigurationfor Gate1: AND_ent use entity work.AND_Ent(behav2);Selects alternative architectures when instantiating entityGeneric like C++ template parameterization

  • VHDLAn acronym for Very high speed integrated circuit Hardware Description LanguageVHDL enables hardware modelling from the gate to system level Allows various design methodologiesProvides technology independenceVHDL has been standardised: VHDL 87VHDL 93

  • System Design; definition and use of its partsA system communicates via an interfaceInterface is entity in VHDLCannot have any VHDL system without an entityExample: entity my_entity is..end entity my_entity;

  • ArchitectureThe body of the system accomplishes some tasks on the dataeg data transformationIn VHDL the body is called architectureExample: architecture my_architecture of my_entity is . begin end architecture my_architecture ;

  • Types of ArchitectureBehavioural (Functional)The system in terms of its functionality It does not contain any information about the internal system structureIt describes the expected behaviour: What a system will doResponse of outputs to inputsNo clue as to HOW but describes WHAT a system has to do

  • Types of ArchitectureStructuralHOW a system is composedwhat components should be useddescribes internal structure of systemhow they should be connectedakin to a textual version of a schematic diagram

  • A behavioural architectureif CLK'event and CLK='1' then --CLK rising edgeDOUT
  • A structural architectureA Full Adder:


  • A Structural Architecture--generate constructgen: for i in 0 to n-1 generate--component instantiationins: full_adder port map (a(i), b(i), carry(i), sum(i), carry(i+1));end generate;

  • One Entity - Many ArchitecturesMore than one way to create a designSimilarly, more than one architecture for a single entity (cf. More than one schematic to fulfil same specification) Same interface

    BUT only one entity for any architecture

  • PackageExternal source of descriptionAllow you to define items outside of VHDL standardsMust be declared in advance using library and use keywords, usually before entity

  • Few PackagesStandard (defined by the std library)Std_logic_Textio (defined by the IEEE library)Std_logic_1164 (defined by the IEEE library)Plus vendor-specific

  • CommunicationsSignals: inside device or between devicesSingle or multiple wire - (bus) or (vector)Examplebit for single signalsbit_vector for multiple signalsin both cases, each signal line can be either 1 or 0For bit_vector the width of the vector must be specified using two key words: downto and toOrder important for vectorbit_vector(7 downto 0) ascending order of bitsbit_vector (0 to 7) descending order of bits

  • external signals External signals connect the system to the outside: they form the systems interfaceEach external signal is specified as port inside its entityEach external needs a unique name, a type and a direction:input - inoutput - outbi-directional - inout

  • Port Syntaxport_name: port_direction port_type ;example: port( result: inout bit_vector (0 to 7) );

    Multiple signals of different type separated by semicolonsSame type separated by commasoptional initial value, preceded by :=

  • Example: entity ROM_MEMORY is port ( A_ROM : in bit_vector (3 downto 0); CS_ROM : in bit; D_ROM : out bit_vector (7 downto 0) );end entity ROM_MEMORY;


  • Internal signals Internal signals declared inside an architectureThe keyword signal is required to declare an internal signalInternal signals do not require a directionIt is possible to specify an initial value for an internal signal

  • GenericsMethod of providing constant values for different parameters.Must be in entity, before portsNeed the keyword generic, name, type, value, optional commentexample generic (BusWidth : integer := 2; MaxDelay : time := 100 ns ) ;Can be used anywhere a constant is needed

  • GenericsCan be used anywhere a constant is neededParameters are typically specified by generics:The size of some objects such as arrays or busesTiming parameters Useful in structural and behavioral models

  • Standard Data TypesEnumeration types ( Boolean, bit, character)Integer typeReal typePhysical type (time)Standard array types ( string, bit_vector)

  • Enumeration typesBit 0,1not same as Boolean in VHDLBoolean true, falseCharacterall characters in ISO 8859-1 (West European)eg 0, 1, X

  • Intege