base computer based measuring techniques

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PrefaceThis is part 2 of a compendium in Measuring Techniques intended for a course in Computer basedmeasuring techniques on distance.Part 1 (in Swedish) is intended for a basic course coveringanalog and digital electronics with applications to sensors and actuators. This part, Computer BasedMeasuring Techniques, covers computer busses and interface techniques, as well as signal analysiswith FFT and data analyses with least square fits.
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1.Introduction : Computer Based Measuring Techniques

Welcome to the world of laboratory and industrial automation. This compendium is an attempt tosummarize important tools for how to:

* Attach a computer to an instrument or sensor.* Control the instrument.* Collect data from it.* Analyze the data.

However, a short compendium can never replace a text book with its deeper and more thoroughlytreatment of a subject. When possible, references are made to Horowitz and Hill: The Art ofElectronics, 2:nd ed. Cambridge University Press 1989, a solid "brick" with numerous of examples.Another textbook that also treats all circuits from sensor to computer is Wassos and Ewing: Analogand Computer Electronics for Scientists, Wiley & Sons 1993. Practical hints may also be found inGates and Becker: Laboratory Automation using the IBM PC, and T.Olsson: IBM PC i styr- ochmtsystem, Studentlitteratur 1986, not to forget instrument catalogs from companies such as

National Instruments, IOtech,Keithley, Burr-Brown and many many more.

Latest information is probably obtained using Internet. Try for instance the search enginehttp://www.pcwebopaedia.com/ .

In most modern applications, laboratory automation involves the use of computers or computer-based systems to control one or more instruments, collect data from those instruments, and processthe data to make it useful to the scientist or other user. Less formal, it involves hooking up acomputer to a sensor with some electronics and writing some software. Laboratory automation canalso include the area commonly referred to as laboratory robotics, in which a computer-controlleddevice is responsible for some or all of the sample handling during the experiment and many otherkind of large-scale applications such as process control and laboratory information management.However, this is not the subject of this compendium.

Figure.1: Computer based measuring system

Figure 1 shows a block diagram of a computer based measuring system. Attached to the object we

have the sensor, which is characterized by its linearity or nonlinear behaviour, the precision and itsaccuracy. See the sectiondata analysis on how to control and determine these factors in software.Calibration of the sensor with all electronics attached is also of central importance if a product
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should achieve the ISO-9000 quality system standard certification (ISO = International StandardOrganization, seehttp://www.iso.ch ). Stability of e.g. amplifier gain, is perhaps settled only after along time. Any adjustment in the electronics may require a new settling time. However, in acomputer based system adjustments may instead be introduced in the software.

Noise, shielding, grounding and analog to digital converters are described in section "adc". Filteringof the digital data may also be performed by the software, see section "signal", where also spectralanalyses and correlation analysis are treated. We should not forget that measured values often arerepresenting parameters of a physical model which should be fitted (section "LSQF").

Most parts of the computer based measuring system in Figure 1 are tied together by the bus anddifferent busses are also the main subject of this compendium. Figure 2 shows three differentapproaches, all of which are treated in more detail in section "bus" and "GPIB".

1.Whenmeasuredobject is closeto thecomputer, in alab or testenvironment.

2.When generalinstrumentsare used.
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3.When usingfew

instruments,located farfrom thecomputer.

Figure.2:Measuring systems with PC-computers


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2 PID control : Computer Based Measuring Techniques

"Measuring technique" do not only involve measurements of some kind of physical parameter butalso control of actuators and larger systems. Controllers are designed to eliminate the need forcontinuous operator attention. Cruise control in a car and a house thermostat are common examples

of how controllers are used to automatically adjust some variable to hold the measurement (orprocess variable) at the set-point. The set-point is where you would like the measurement to be. Atypical temperature controller system measures a temperature as give by a temperature sensor,compares this with a set-point - wanted temperature, and controls the heating or cooling aggregatein order to minimize the deviation or error. The Figure shows a block diagram of such a feedbacksystem.

Figure:Control feedback loop. The output u from the controller is a function of the difference("error" e) between the set point r and the measured value y: e=y-r.

The simplest feed back is the on-off regulation which can be improved by introducing somehysteresis. A more "smooth" feedback loop is the PID-regulator, where PID stands for Proportional,Integral, Derivative:

.

The mathematics behind the design of such feedback loops and how to determine the best choice ofparameters is not the subject of this compendium, but is covered by other courses and texbooks

such as T.Glad & L.Ljung: Reglerteknik - Grundlggande teori, (Studentlitteratur 1981), andL.Ljung: Reglerteori - Moderna analys- och syntesmetoder, (Studentlitteratur 1986). A tutorialoverview may also be found at http://www.expertune.com/tutor.html . An extensive ControlTutorials for Matlab is found at http://www.engin.umich.edu/group/ctm/.

Zeigler-Nichols method is described in some manuals to measure and control programs:First set KI and KD =0. Increase KP gradually until the system just starts to oscillate. This point of

instability is called the "ultimate gain" PU and "ultimate period" TU:

Action Performance Gain K P Integral 1/KI Derivative KD

P 1/4 decay 0.5 PU

PI 1/4 decay 0.45 PU 0.833 TU

PID 1/4 decay 0.6 PU 0.5 TU 0.125 TU

PID some overshoot 0.33 PU 0.5 TU 0.33 TU
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PID no overshoot 0.2 PU 0.33 TU 0.5 TU

However, this method assumes no positive or negative limitation of the controller output u.

Electrically, the PID-regulator is realized with op-amplifier circuits but it is also readilyimplemented in a software measure and control program. With a computer or microcontroller in thefeedback loop self adjusting PID-regulators are possible to implement as well as more fancyregulators based on neural network algorithms and Fuzzy Logic Control.


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12. Microcomputers and busses Computer Based MeasuringTechniques

Figure 12.1: Block diagram of a computer


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12. Microcomputers and busses : Computer Based MeasuringTechniques

The internal structure of computers involve several parallel communication paths, called busses(Figure 12.1), A typical bus system contains a large number of long parallel conductors in thefollowing substructure: (1) A data bus carries the 1's and 0's representing the data to be transmitted

between devices. (2) An address bus contains a number representing the destination. (3) A controlbus serves as an administrator the process and also transmits instructions from the controller. Beforelooking into a typical bus interface more in detail (Figure 12.5) we recall some digital electronics

basics.

Figure 12.2: Tri-state and Open Collector logic.

In general one may not connect the outputs from two devices to each other, unless the output circuitis of "Open Collector" or "Tri-state" type. In Tri-state logic, the output is activated or isolated (like aswitch) with a third signal. The output of the leftmost device is enabled when the gate is high. An"inverting ring" on the gate of the second circuit, indicates that the enabling of the output is activewhen the signal is low. Only one output may be active at the time and this is usually controlled bythe address and control busses.

Open collector circuits are not able to drive the high logic state by themselves, only to sink theoutput to low voltage. If any output is low the bus line will be in the low state independent of theother outputs. A high state is only possible when all outputs are "high" and the high voltage of the

bus line is driven by a "pull-up" resistor to e.g. +5V. The open collector logic is often called "wiredor" since the true state (active state or 1's) are represented by 0 V (inverted logic). It is particularuseful for handshaking: Each device acknowledge an instruction by releasing the bus line but thisgoes high first after all devices has given their acknowledge.


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Latchand registers

are used for receiving or transmitting data on thebus. Several D-flip-flops in parallel have a commonclock (or gate) input and tri-state enable input.

Figure 12.3 shows a '573 octal D-type latch with tri-state outputs. 8-bit of parallel data (byte) is clockedfrom the inputs when C is high (1) and is present on

the outputs when is low (0).

The term "latch" strictly refers to a transparent latch,whose output follow the respective inputs whileenabled. A so-called edge-triggered latch ('574), withedge-triggered clock, is properly called a D-typeregister. The difference may have importantconsequences when latching data from a bus,

because of the relative timing of data and thestrobing clock pulse.

Figure 12.3: '573-register

Address Decoder

Figure 12.4 shows one example of a decoder circuitoften used for address decoding. The output (Yn),corresponding to the address given by the numbern=CBA in binary form, is low (as indicated by therings) while all other outputs are high.

The '138 circuit has 3 extra gate-inputs which maybe used to extend the address range beyond the 3bits (C,B,A).

Figure 12.4: '138 address decoder


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Figure 12.5: An example of bus connections based on the ISA-bus structure.

Figure 12.5 shows an example of how an interface to a computer bus looks like. It is based on thesignals available on the ISA-bus, found in IBM PC/AT, 386, 486, 586 etc. (ISA = Industry StandardArchitecture, a de facto standard). It is probably the most common bus for plug cards inmeasurement systems and is described later in more detail. In Figure 12.5 only the three leastsignificant address bits are shown. The other address bits may control the gate inputs G1, G2 andGL on the '138-decoder, through additional logic.

When the computer writes data to a card or device on the bus, it puts the 8 bit (1 byte) parallel dataon the data bus while simultaneously putting the address on the address bus. When address and data

is available it sends a strobe signal which goes low for slightly longer than 0.5s. During thisstrobe pulse the card with the appropriate address must "latch" or catch the data in a register. When

the address is 5 in Figure 12.5, Y5 is 0 on the '138. Y5 and are NOR'ed to the clock of the left

'573-latch. Hence this clock input becomes 1 only when =0 andY5=0 (NOR works for activelow inputs like AND for active high inputs). The output of the latch is continuously showing the

values of the D-flip-flops in the '573, since is tied to ground.

When the computer reads data from the bus it sends an address and a strobe signal which goeslow for slightly longer than 0.5s. During this strobe pulse the addressed card is allowed to put itsdata on the data-bus, but not otherwise. As before Y5=0 for the address 5 and this is OR'ed with

=0 to give =0 on the right '573 latch which then enables its tri-state outputs. We assumethat the inputs to this latch is not changed during this time and that the clock (C) gate can be tied to+5V for simplicity.

When LS, HC or HCT gates (e.g. 75LS573) are used, there is no problems with the propagationtime in the gates relative to the length of the strobe pulses.

The popular ISA bus, or equivalent IBM-AT-bus, is an extension of the IBM-PC bus . The originalPC cards required a 60-connector socket. The ISA bus (Table 1) added a 36 connector extensionsocket with additional data (8), address (4), interrupt (5) and other lines. In this way the original PC-cards can also be used on the ISA bus and many I/O-cards today are only using the PC bus signals

and connector. In 1988 yet another connector was added and the Extended Industry StandardArchitecture (EISA) was introduced. It uses a two-level socket where the lower part follows the60+36 ISA setup, while the upper part connects with a third set of contacts. Thus standard ISA plug-


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in boards can be plugged into EISA getting normal ISA functionality while EISA designed systemssupport 32-bit data transfers at higher rates, 32-bit memory addressing, multiple bus masters,

programmable level or edge-triggered interrupts and automatic board configuration.

From the first IBM PC up through the first PS/2 computers (introduced in 1987) a computer hadone bus and all of its devices and chips ran at the same speed. On those systems, additionalcomputer memory was often added by plugging an adapter card into the same slots that held I/Oadapters. Starting with machines that used the 386 CPU, the memory and CPU of the system ranfaster than the I/O devices. The solution was to separate the CPU and memory from all the I/O.Today, memory is only added by plugging it into special sockets on the main computer board. In amodern PC, there may be a half dozen different Bus areas. There is certainly a "CPU area" that stillcontains the CPU, memory, and basic control logic. There is a "High Speed I/O Device" area thatmost often is a PCI Bus, connecting the high speed bus on the mainboard to the display adapter andIDE disk interface chip. Then one or two extra I/O slots may allow adapter cards to connect to thePCI bus. The remaining I/O device slots support standard "ISA" bus cards. Some computers willalso provide sockets for a number of PCMCIA "credit card" adapters commonly found in laptopcomputers. More about these buses in section 12.5.

There are three different methods to transmit data between a card on the bus and memory:a) Programmed I/O. Data goes via the CPU-registers. Uses the assembler instructions IN andOUT. In TurboPascal these are called by using the predefined array PORT[ ], in Borland C (orTurbo C) by the OUTPORTB and INPORTB- instructions and in Visual C++ by _outp and _inp.Addresses refer to the "port" address on the bus, see Table 2, which is distinguished from memoryaddresses on the ISA bus by AEN=0. This signal must be included in the address decoder on thecard. The Centronics printer port uses this type of I/O.

b) DMA- Direct Memory Access. A smarter device can transfer data directly to memory withoutthe use of the CPU. DMA is requested from the CPU on a special bus line DRQ. The CPU leavesthe control of memory addressing, handshaking, etc. to the memory card. In the PC/AT there is a

special DMA controller chip which simplifies the construction of the measuring card. A programstores into the DMA circuit a starting memory buffer address and length. When the device is readyfor more data, it uses one bus cycle to send a request to the DMA chip, the chip then substitutes forthe CPU in generating the next buffer address to the memory circuits to fetch the next chunk of datafor the device. However, that first signal from the device to the DMA chip takes one more bus cyclethan ordinary Programmed I/O. Thus DMA has not been attractive for disk, LAN, and other

performance critical I/O.

c) Memory mapped I/O. A measuring card may be placed as part of free RAM then using

and strobe pulses instead of and . This technique is used by certaincommercial measuring cards to PC:s. Monitor interfaces and frame-grabber cards, connected to

CCD-cameras (TV-cameras), often have their own memory which from the programmers point ofview just looks like the usual memory. Data is accessed by using pointers like any other variable inthe program. The graphics card of the IBM-PC is placed in memory location above 640 kbytewhich is the reason why standard DOS programs are limited to 640k memory usage. Older NU-bus

based Macintosh computers use this type of I/O with the upper 64 Mbytes of the 32 bits addressrange reserved for plug-in cards.


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Table 1: ISA bus signals and pin assignments

Signal name Pin # FunctionD0-D7 A9-A2 DataA0-A19 A31-A12 Address lines (A0-A9 for external I/O)AEN A11 Address Enable - high at DMA (Direct Memory Access), low at

"programmed" I/OB14 I/O read strobe - computer reads data

B13 I/O write strobe - computer writes data

B12 Memory read strobe

B11 Memory write strobe

IRQ3 B25 Interrupt request (Serial port 2)IRQ4 B24 Interrupt request (Serial port 1)IRQ5 B23 Interrupt request (Parallel printer port 2)IRQ6 B22 Interrupt request (Floppy disk adapter)IRQ7 B21 Interrupt request (Parallel printer port 1)IRQ9 B4 Interrupt request (PC bus IRQ2). Rerouting to INT 10RESET DRV B2 Power-on resetDRQ1-DRQ3 B18,B6,B16 DMA request

- B17,B26,B15 DMA acknowledgeB19

ALE B28 Address latch enableCLK B20 Bus clock (8.3 MHz)

A1 I/O parity error indicator

A10 Lengthens the read/write strobe time by up to 2.5 s

OSC B30 14.31818 MHz signal used for color graphic boardsT/C B27 DMA terminal count0WS B8 0-wait state indicator GND B1,B10,B31 signal and power ground+5V DC B3,B29 +12V DC B9 -5V DC B5 -12V DC B7 16 bit AT expansion slot

D8-D15 C11-C18 dataSBHE C1 System bus high enable, indicates high byte on the busLA17-LA23 C8-C2 Extra address bits 17 to 23

C9 Memory read strobe

C10 Memory write strobe

D1 Memory chip select 16 for 16 bit memory operation

D2 I/O chip select 16 for 16 bit data operation

IRQ10-IRQ12 D3-D5 Interrupt request, rerouted trough IRQ2, spare

IRQ14 D7 Interrupt request, rerouted trough IRQ2, hard disk IRQ15 D6 Interrupt request, rerouted trough IRQ2, spareDRQ0 D9 DMA request

D8 DMA acknowledge

DRQ5-DRQ7 D11,D13,D15 DMA request

- D10,D12,D14 DMA acknowledge

+5V DC D16 D17 Gain master control

GND D18 Ground


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Table 2: I/O port addresses (with AEN=0) for IBM PC/AT

Hex Range Device Usage000-01F DMA controller 1, 8237A-5 System020-03F Interrupt controller 1, 8259A System040-05F Timer, 8254-2 System060-06F Keyboard I/O System070-07F Real time clock, NMI mask System080-09F DMA page register System0A0-0BF Interrupt controller 2, 8259A System0C0-0DF DMA controller 2, 8237A-5 System0F0.0FF Math Coprocessor System1F0-1F8 Fixed Disk I/O200-207 Game I/O278-27F Parallel printer port 2 I/O2F8-2FF Serial port 2 I/O300-31F Prototype card I/O360-36F Reserved I/O378-37F Parallel printer port 1 I/O380-3AF SDLC, 1-2 I/O3B0-3BF Mono display printer adapter I/O3C0-3CF Reserved I/O3D0-3DF Color Graphic monitor adapter I/O3F0-3F7 Floppy diskette controller I/O3F8-3FF Serial port 1 I/O

Figure 12.6: ISA bus I/O write and read cycle. Note that valid data is available after has gonelow in the write cycle. The output of a transparent latch will have a glitch (wrong bits during a shorttime), while this is avoided by using a positive edge triggered register.

Figure 12.7:ISA card


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12.1 CPU Central Processing UnitAmong the devices that control the bus, the CPU or microprocessor is the master. The interface busitself continues inside the CPU chip but there are also internal busses that connect various

components (see Figure 12.1).- Register - very fast one-word memories. Defines the size of a "word". See.Table 3.- Flags - 1-bits flip-flops. Keeps track of operation conditions.- Counters - such as program counters indicating next memory location of instructions).- ALU Arithmetic Logic Unit (+ - AND OR, ...)- Cache memory- Control logic and instruction decoders.

An assembler instruction (machine language) is as a binary number which cause a certain actiondetermined by the instruction decoder in the CPU. The example below illustrates the same programline in different languages. Figure 12.8 illustrates how a binary number can be decoded to e.g.

move data from one register to another.Pascal if n=m then n := n+1;C if ( n == m ) ++n;Fortran if ( n .eq. m ) n=n+1Assembler #LINE#3:

CS:0317 8B46FE mov ax, [bp-02]CS:031A 3B46FC cmp ax, [bp-04]CS:031D 7503 jne #LINE#4CS:031F FF46FE inc word ptr [bp - ds 6E07]#LINE#4

Note that the CPU register names, size and organization must be known together with theinstruction set when programming in assembler language.

Table 3: Intel 8086 CPU-family (PC/AT) registers.Register name Uses in TurboPascal or C (DOS-applications)

AX AH AL Calculations, I/O, return values from functions, etc.

CX CH CL String counters, shift operations etc.

DX DH DL Calculations, I/O, and more

BX BH BL Addressing

SP Stack pointer

BP Base pointer

SI Source index - points to strings in the program code.DI Destination index - for strings

ES Extra segment

CS Code segment - for program code and constants

SS Stack segment - stack position (local variables)

DS Data segment - position of global variables

IP Instruction pointer

Flag Status word


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Intel 8086/8 (IBM-PC) has 16 bit registers,only allowing 216 = 64 Kbytes directaddressing. 1 Mbytes (20 bit) is addressedusing a segment and an offset address. DOS

program data arrays in Pascal and C arelimited to one 64k segment each. With the

80386 CPU and later, registers are 32 bitlong but can also be used as 16-bit units forcompatibility reasons.

Figure 12.8: Demonstration of how an instruction in form of a binary number moves data from oneregister to another. The two leftmost digits are decoded to enable the output of register D, while theright half of the instruction word enables the input gate of register B.


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Motorola's MC 68000 - family is together with theINTEL 8086-family the most popular microprocessorstoday. The old Macintosh (not PowerMac) is based onthe Motorola processor while the PC's (486,Pentium,..) uses INTEL-processors.

Some MC 68000 features:32 bit general purpose data and address registers(Figure 12.9).Address space 4 Gbytes with 32 bit address.Only memory mapped I/O - interface cards are placedas part of free RAM.

Bus-signals for MC 68008:A0 - A19 20 address lines (1 Mbytes)

despite 32 bit registers.D0 - D7 8 data linesAS', DS', R/W' strobe linesDTACK' acknowledge (handshaking)IPL0-IPLK2' 3 interrupt lines

NOTE! This is the microprocessor bus, not thebackplane bus in the Macintosh.

Figure 12.9: 68000/8 registers

Electronic constructors use today more likely microcontrollers than microprocessors, since thesealready contains I/O-ports and perhaps DAC, ADC, etc. on the same chip. Many of these are foundin household electronics such as washing machines, microwave oven, CD-players, TV, videos, .....


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12.2 Memory:The memory size of a chip is given in kbit or Mbit while memory addressing is referring to bytes.Each bit in a data word is stored in separate chips or memory banks activated by the same address.

Introduced in the early 1950s, core memory consisted of small magnetic rings, that could receivetwo state of magnetization. Now it has been abandoned in favor of semiconductor RAM. These are(unlike cores) volatile - they loose the information when power is turned off.

RAM Random Access Memory

SRAM Static RAM - "D-flip-flops"

DRAM Dynamic RAM - "capacitor charge", must be updated regularly. See Figure 12.10.

ROM Read Only Memory - programmed when manufactured.

PROM Programmable ROM - burns off "wires" in a matrix.

EPROM Erasable PROM - charges that may be erased with UV-light.

EEPROM Electrical EPROM - erased where it is connected but all bytes are erased at once.

CDROM 600 Mbyte / 5" (1993) - rather an external memory like a harddisk.

WORM Write Once Read Many times

Flash "EEPROM" - block wise erase.

To quote the size of DRAM chips is hazardous since it easily makes the text out of date. In 1995the chip size used for PC-computers were 4 Mbit. 64 Mb were soon in mass production, a numberwhich increases by a factor of 4 each second year. Research institutes produced already 1Gbmemories. The limitations are set by the line size (now 0.25 m) and electron tunneling.


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Figure 12.10: A simplified DRAM element Figure 12.11: Schematic connection of a memory tothe computer bus.


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12.3 InterruptAt an interrupt ("avbrott") the running program is interrupted and the execution of an "interruptservice routine" (ISR) is started. When this program is ready the execution of the original program

is continued. Example: When the mouse (or other pointing device) is moved an interrupt isgenerated by the mouse interface. The computer jumps to a memory resident mouse driver program,usually installed at start-up, and the cursor is redrawn on the screen. Then the execution of theoriginal program is continued.

In many measuring situations data are not coming regularly in time, e.g. for radioactive decays.Instead of having the computer locked up waiting for data, the data can generate an interrupt. Therunning activity (e.g. plotting) is interrupted and an ISR-program reads and stores the data.

PC/AT:

A special interrupt controller circuit 8259 PIC (programmed interrupt controller) simplifies the

interrupt handling versus the CPU.1. IRQn goes high.

2. If bit number n is =0 in a mask register in the 8259 PIC (port-address hex. 21) an interrupt isrequested at the CPU.

3. The program counter is saved by the CPU on the stack memory. The program counter is aregister in the CPU showing where the next instruction is in the memory.

4. The program counter is replaced by the interrupt vector n. This vector contains the start addressfor the ISR-program. The interrupt vectors are placed in the beginning of RAM with memoryaddresses hex. 20 + 4n (byte).

5. The ISR-procedure must first save on the stack all CPU-registers it may use itself, so no valuesare changed for the interrupted program. These instructions are automatically inserted by theTurboPascal or Borland C compiler when a procedure or function has the key-wordInterrupt

6. The ISR-procedure performs its task.

7. The ISR-procedure informs the 8259 PIC that it is ready by writing hex. 20 to a register with theport-address hex. 20: outportb(0x0020,0x20); in BorlandC.

8. Reset all CPU-registers. Automatically inserted instructions at the end; of anInterrupt-specified procedure.

9. The program pointer is restored by the CPU and the old program continues.

Installation of an ISR-procedure (see program example):

1. Write the address of the ISR-procedure to the interrupt vector n.setvect(n+8, isr); in BorlandC.

2. Reset bit n to 0 in the 8259 PIC:s mask register in order to activate the interrupt n.outportb(0x21, inportb(0x21) & (~(1


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#include

unsigned int k; /* global variables */

void interrupt isr(void) {k++;

outportb(0x0020,0x20); /* non specific EOI to 8259 PIC */}

voidmain(void) {/* Set interrupt vector entry to isr-procedure

IRQ7 interrupt line correspond to 7+8 dos interrupt number */ setvect(7+8, isr);

/* Enable interrupt:Get IMR (interrupt mask register) from 8259 and clear mask bit 7 */

outportb(0x21, inportb(0x21) & (~(1


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The ISA bus use edge sensitive triggering, which avoids the problem of retriggering for longinterrupt pulses. However, most other systems use level sensitive triggering, which allow severalunits to use the same IRQ-line with open collector logic. Different methods are used to determinewhich device that caused an interrupt:

1) Polling "Autovectored polling" (compare SPOLL in GPIB).- IRQ (interrupt request) to the CPU.- Read successively each status register on each connected unit. A flag indicates whether the unitrequested interrupt or not.- To each unit there is an interrupt vector, then continue as described for the PC-interrupt.- The IRQ-line is low until all units, requesting an interrupt, has been served and released the IRQ-line..

2) Vectored interrupt "full vectored interrupt acknowledgment protocol"- IRQ to the CPU- CPU gives an "interrupt acknowledge" (INTA)- The interrupting unit writes its interrupt vector on the data bus lines, then as for the PC.This is the method used by IBM PC/AT but simplified for the user, thanks to the 8259 PIC-circuit)

Several units may be connected in a so called "Daisy chain". Interrupt acknowledge is here not abus signal but goes into one unit which (by some logic) sends it to the next unit unless it requestedan interrupting by itself. The unit closest to the CPU gets the highest priority.

Figure 12.12: Daisy chained vectored interrupt system where the interrupting units are sending anidentification code. The device closest to the CPU has the highest priority but passes the interruptacknowledge (INTA) signal to the next device when it did not request interrupt itself. Uponreceiving INTA the second device puts its interrupt vector on the data bus.


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4 Digital signal transmission

Microprocessor-based systems are continuing to increase in frequency of operation at anaccelerating pace. As a result, local and external busses are also being pushed to higher and higherfrequencies. Time allowed for signal "settling" can no longer just be guessed and the bus design

must be optimized for minimal data transfer time. This in turn requires that phenomena such asreflections, crosstalk, ground shift, etc., be understood and minimized.

Reflection in transmission line networks are basically the result of impedance discontinuities. Thecommon coax-cable RG-58 has a "characteristic impedance" of 50 , meaning that a wave frontmoving along the line has a voltage / current ration of 50 . For a lossless line (negligible Cu-

resistance) the impedance, which is resistive (real), is , where L = inductance and C =capacitance per unit length. The transmission velocity is about 2/3 of the velocity of light or about 1meter in 5 ns. If the receiving end has a low impedance (RL=0 in fig.) the wave is reflected with

opposite phase so that the sum of incoming and reflected voltage is zero in the shorted point. If the

impedance is high (RL=) the summed currents must be zero and the wave is reflected with thesame voltage phase. 50-termination gives no refection.

Figure 12.13: Characteristic impedance of a cable and termination.

The characteristic impedance on printed boards and for twisted pair cables is about 100 . The typeof bus transmission line together with driver and receiving circuits (transceivers) determines the

maximum speed and length for the digital transmission on the bus. There are often special driverand receiver chips constructed for different bus-types.

12.5 Other parallel backplane bussesA "backplane" (or motherboard) is used to electrically interconnect a group of circuit boards while

providing mechanical support for those boards in a rack or computer box. The connectors (or slots)of a backplane bus are usually wired in parallel. Table 4 list some popular busses and theircharacteristics.


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Table 4: Backplane busses

Bus Band-widthMbyte/s

Data width Addresswidth

Sync orAsync

IRQlines

Drivers Comments

PC/XT 1.2 8 20 S 5E TTL IBM PC & compatible

PC/AT 5.3 8,16 20,24 S 10E TTL Industry Standard Architecture (ISA) but notaccording to any standardization commissioAccepts PC/XT

EISA 33 8,16,32 20,24,32 S 11P TTL "Extended ISA", accepts old AT-cards but wi

PCI 132 32(64)

S TTL New local bus in PC-compatibles, Power Mothers. For multimedia, graphics, disk drivesmore. Plug-and-play. More info:

http://www.pcwebopedia.com/PCI.ht

CAMAC 3 24 9 S L TTL/OC

Instrument bus often used in nuclear and par

NuBus 40 32 32 S M TTL (IEEE-1196, 1987) used inMacintosh-II. Common data and address bususing 16 Mbyte of the last 1/16 of the 4 Gby

VME 40 8,16,32

16,24,32

A 7 TTL VERSA Module Eurocards, developed fromVERSA-bus. Asynchronous microprocessorof accessories. SUN-3

VXI VME eXtension for Instrumentation. Fast-grfor instrumentation systems, in particular -systems.

Futurebus 120 A special 3,2 Gbyte/s?Not approved as a standard yet.

Fastbus 160 32 32 A M ECL Developed for data collection and control ofdetector systems in particle and high energy

E = Edge-sensitive; L = LAM ("look at me"); M = via bus mastership; P = programmable edge- or level-sensitive

Some busses use synchronous data transfer. A "strobe"-signal indicates when data is available but

no "acknowledge" of received data. For asynchronous transfer an acknowledge"-signal indicatesthat data has been received and until then data is available on the bus.

Sometimes a separate address bus is missing and a common data and address bus is used (e.g.NuBus in Macintosh II). In general this requires more logic on the I/O cards compared to theexample in Figure 12.5.

Devices and plug-in cards for the more advanced busses are often using special ASIC (ApplicationSpecific Integrated Circuits) for the interface with the bus.

Plug and Play: ISA boards usually have to be manually configured via DIP switches and/orjumpers, e.g. to set the base I/O address. Now, with special logics on the plug-in card, one can takeadvantage of Plug and Play operating systems, such as Windows 95, and use software.

PCI - bus ISA - bus
http://www.pcwebopedia.com/PCI.htmhttp://www.pcwebopedia.com/PCI.htm


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Peripheral Component Interconnect Industry Standard Architecture

33 MHz (66 MHz ext.)"half the memory bus speed"

8 MHz

32 bit (64 bit ext.) 16 bit

133 Mbytes/s, (800 Mb/s burst transfer) 8 Mbytes/s (64 Mbytes/s)

49 signalsmultiplexed address and dataaddress: memory, I/O, configuration4 IRQ (shareable)+5V, +3.3V, +12V, -12V, GND

88 signalsseparate address and data linesaddress: memory, I/O11 IRQ+5V, -5V, +12V, -12V, GND

5 V (3.3 V) signal level 5 V TTL-signal level

Plug-and-play defined in the standard often jumper configuration

No DMA but "Bus mastering" DMA

Bus connectors. Top: ISA-bus,. Bottom right: PCI (32-bit standard), left: 64 bit extension.

PC Card(PCMCIA)The Personal Computer Memory Card International Association (PCMCIA) established a standardfor credit-card sized PC plug-in interfaces. Originally used for flash memory, but now available for

general-purpose and specialized I/O, such as data acquisition and instrument control. PCMCIA isnow the expansion standard for notebook computers.

History http://pclt.cis.yale.edu/pclt/PCHW/BUS.HTMIn 1984 IBM was shipping its PC AT model. The CPU, memory, and I/O bus all shared a common

8MHz clock. This became the basis for all subsequent clone computers. The term "AT" is aregistered trademark of IBM, so this I/O bus became known as the ISA (Industry StandardArchitecture) bus. Every currently marketed PC supports some ISA interface slots. The bus andmatching adapter cards are simple and cheap. ISA is a 16-bit interface, which means that data can

be transferred only two bytes at a time. More importantly, the ISA bus runs at only 8 MHz and ittypically requires two or three clock ticks to transfer those two bytes of data. This is not a problem

for devices that are inherently slow like the COM port (modem), the printer port, the sound card, orthe CD-ROM. However, the ISA bus is too slow for high performance disk access and therefore isnot acceptable in Servers. It is also too slow for modern Windows display adapters.
http://pclt.cis.yale.edu/pclt/PCHW/BUS.HTMhttp://pclt.cis.yale.edu/pclt/PCHW/BUS.HTM


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In 1987 IBM introduced a new Microchannel (MCA) bus. It had clear advantages over the previousPC bus. It's 10 MHz clock was slightly faster. The cards could be automatically configured with autility program instead of setting physical switches and jumpers. The bus can transfer four bytes ofdata at a time and, in some configurations and with some cards, it can transfer data every clock tick.However, the Microchannel itself was expensive, the adapter cards were more expensive, and thetechnology remained encumbered by IBM licensing. The other vendors developed an extension of

the older ISA interface called EISA. An EISA slot contained the older ISA interface, and then anextra socket with additional connections. The user could plug either an old ISA card or a new EISAcard into the slot. The newer cards supported a 32-bit data interface and could therefore transferfour bytes of data per operation. However, to remain compatible with the old card, EISA still ran at8MHz. And the extra logic pushed up the cost of both the EISA system and each adapter card.

As the 486 CPU chip became popular, the idea of running I/O devices at 8 or 10 MHz collided witha mainboard that ran everything else at 33 MHz. The first solution was the VESA Local Bus(VLB), which became popular at the start of 1993. VESA is a consortium of companies makingdisplays and display adapters. Desktop machines began to include one or two Local Bus slots tosupport a high speed video card and, perhaps, one other high speed device. A few vendors produced

VESA SCSI adapter cards, or Local Bus LAN adapters. Nevertheless, VESA remained largely adisplay standard.

PCI - The Current StandardThe PCI bus was developed by Intel. Although it is mostly known for its CPUs, Intel also has ahistorical association with Ethernet, multimedia, and some disk interfaces. So Intel was unhappywith the VLB concentration on just the video interface and wanted to develop a general purpose

bus. The objective was an interface that was fast and inexpensive. It did not have to be simple(advances in chip technology took care of that) and could achieve a low cost by high volume

production.

PCI is a 64 bit interface in a 32 bit package. Figuring this out requires a bit of arithmetic. The PCI

bus runs at 33 MHz and can transfer 32 bits of data (four bytes) every clock tick. That sounds like a32-bit bus. However, a clock tick at 33 MHz is 30 nanoseconds, and memory only has a speed of 70nanoseconds. When the CPU fetches data from RAM, it has to wait at least three clock ticks for thedata. By transferring data every clock tick, the PCI bus can deliver the same throughput on a 32 bitinterface that other parts of the machine deliver through a 64 bit path.

The PCI bus has all the signals of the old ISA bus. This allows a PCI adapter card to emulate olderequipment. For example, a PCI disk controller can respond to the same addresses and generate thesame interrupts as the older disk controllers that the BIOS understands. However, PCI devices canalso be self-configuring and operate in a Plug and Play mode.

The PCI bus connects at one end to the CPU/memory bus and at the other end to a more traditional

I/O bus. The PCI interface chip may support the video adapter, the EIDE disk controller chip, andmaybe two external adapter cards. A desktop machine will have only one PCI chip, and so it willadd a number of extra ISA only slots. A server may add additional PCI chips, and extra server slotswill usually be EISA.

While ISA and EISA are exclusively PC interfaces, the PCI bus is now used in Power Macintoshsystems and PowerPC machines. It may be attractive for minicomputers and other RISCworkstations.

PC Card (formerly PCMCIA) and CardBusLaptop computers typically have two slots for "credit card" adapters. Originally this interface wascalled "PCMCIA" but that proved too technical for wide acceptance. Today there is an effort to

rename the interface as "PC Card."A credit card adapter is much smaller than the adapter cards that plug into the ISA or PCI slots of alaptop computer. They are also more expensive and slower. Although PC Card slots have been


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offered as an option in some models of desktop computers, the clear disadvantage over full sizedcard restricts their use to laptops.

The credit card slots are bridged to the main I/O bus of the computer. Laptops have been built to usean ISA, Microchannel, or VESA Local Bus internally. The most modern laptops now come with aninternal PCI bus. Credit card adapters can be connected to any of these systems.

A full sized card can come with switches or jumpers that can be used to configure its I/O address orIRQ. More advanced cards may be configured with a utility program. Since it is small project toremove the cover from a desktop system and switch cards, a desktop adapter is designed with theassumption that it will stay put.

A PC Card adapter is sealed in a metal case. It has no configuration switches. They are easy toinsert and remove, since a user may need a LAN card for use in the office and a modem card for useat home or when traveling. The PCMCIA standard was developed late enough to incorporate anearly version of "plug and play."

In the laptop, each socket is itself an I/O device. A PC Card adapter can be plugged into the systemat any time, even when the power is on and a system is running. The socket can query the card for

identifying information, and the adapter can be configured by the operating system to use availableI/O addresses, IRQs and similar resources.

Full support for PCMCIA was too complicated (and required too much memory) to easily fit intothe old DOS operating system. Laptops were not an important platform for Windows NT, so it has avery limited support for this architecture. The best PCMCIA support is found in Windows 95. It is

possible to plug a new adapter card into a running Windows 95 machine, have the operating systemrecognize it immediately, and have the system dynamically configure new driver support.

The main problem with the PCMCIA bus is performance. Current systems support only a 16 bitinterface to adapter cards. Adapter cards transfer data at a rather low clock speed, and there is no

provision for Busmaster data transfer. The maximum data transfer rate from a PC Card adapter to

the CPU or memory is only 2 megabytes per second. A PCI adapter, in contrast, can burst data at133 megabytes per second.

A 32 bit version of PCMCIA has been created under the label "CardBus". It is currently availableonly on the most powerful and expensive laptop systems. If you are looking for desktop

performance in a portable system, CardBus slots are highly desirable.

Current Status (1997)Although the ISA bus may be ten years old, it remains a perfectly reasonable option for devices thatdo not require highest performance. The consumer-oriented products all come with built-in videoand disk adapters. Those are the two components that have the greatest impact on home computersand probably most desktop business machines. There simply isn't any need for a higher speed to

support the sound card on a multimedia system, and the CD ROM is the slowest storage deviceavailable.

The higher end of the consumer market and the machines sold directly to corporations typicallyhave a few slots with a PCI interface. It is nice to have, but in the next year or so these slots mayremain empty. The pre-installed devices cover most requirements, and storage expansion is simpleand inexpensive using EIDE disks and devices.

A Server comes in a full sized floor standing tower. Some servers have room for 18 disk drives.There will certainly be a PCI bus, but there will also be several standard SCSI adapters to connectall the disks, tapes, and CD-ROM units. Every adapter in a dedicated Server should be a PCI card.Some SCSI controller may be built into the mainboard. An external PCI SCSI adapter can provide

additional function, cache memory, or RAID support. LAN adapters should plug into the PCI slot.Because the older ISA slots are much slower, there is a strong bias that any function that is notimportant enough to warrant a PCI adapter is something you probably shouldn't do on a server.


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Laptop computers are appearing with an internal PCI bus. This provides high speed support for theinternal connection to the video and disk controller chips. It may also provide for PCI cards whenthe unit is connected to a docking station.

12.6 Parallel busses with "cable interface":

IEEE-488: GPIB - General Purpose Interface Bus, see separate section in this compendium.SCSI: Small Computer System Interface ("skuzzy") - standard for connecting several disks andother units with transfer of large amount of data.SCSI-1: 4 Mbyte/s; SCSI-2: 10 Mbyte/s (20 Mbyte/s at 32 bit transfer)Up to 8 connected units, 6 - 25 m length depending on type of driver.The standard also defines the system architecture (software).

Centronics: Standard connecting printers. Simple measuring and control electronics is also readilyinterfaced since data already is latched. Figure 12.14 shows an example of a Centronics-interface.The connector at the computer end is a 25-pin DIN-connector. Table 5 show the "port"-addresses,data-bits, pin-numbers and signal names. Some IBM-computers use the addresses (hex) 3BC, 3BD,

3BE instead of 378, 379 and 37A. For further details and examples on how to use this port, see:http://www.geocities.com/SiliconValley/Bay/8302/
http://www.geocities.com/SiliconValley/Bay/8302/http://www.geocities.com/SiliconValley/Bay/8302/


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Table 5: Centronics signals, pin numbers and addresses.

Pin Name Address(hex)

Databit

Pin Name Address(hex)

Databit

1 Strobe' 37A 0* 10 ACKNLG' 379 6

2 Data bit 0 378 0 11 Busy 379 7*

3 Data bit 1 378 1 12 PE 379 5

4 Data bit 2 378 2 13 Select 379 4

5 Data bit 3 378 3 14 Auto feed' 37A 1*

6 Data bit 4 378 4 15 Error' 379 3

7 Data bit 5 378 5 16 Init' 37A 2

8 Data bit 6 378 6 17 Select in 37A 3*

9 Data bit 7 378 7 18-25 Ground

*) Hardware inverted by the Centronics interface.

Figure 12.14: Centronics port for PC. However, the connection of ACKNLG' to IRQ7 differsamong PC:s and is often active low and level sensitive.


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12.7 Serial communicationAlphanumeric communication between a computer and devices of moderate speed is mostfrequently done using the 7-bit ASCII code (American Standard Code for Information Interchange

-see Table 8), with bit serial transmission over a single line. Wiring is simplified and in particularmore convenient for long distances between computer and device. A modem (modulator -demodulator) can convert a serial bit stream to an audio signal, and vice versa, which can be sentvial telephone lines.

Although the CPU works with parallel information, data transfer may be serial by using shiftregisters. A shift register is a set of several D-flip-flops, with each output driving the next input, andwith a common clock input (see Figure 12.15). A pulse sequence on the input is clocked, bit by bit,and the result is presented in parallel form on the output (Q0 - Q3). The opposite is also possible.Data in parallel form are loaded to the shift register and shifted out in serial form (not shown inFigure 12.15).

Synchronous serial communication use a common clock-pulse line while asynchronouscommunication use separate oscillators at the transmitting and receiving end. Usually the protocolthen contains a "start-bit" to synchronize the data transmission and the two oscillator frequenciesmust only be set equal enough not to phase out the transmission of one pulse train (data package).

Figure 12.15: Principle of a shift register

RS-232 is the most common standard for serial communication and is used by terminals andmeasuring instruments. The original method, which dates back many decades, consists of switchinga 20 mA current - "current-loop" signaling. It is now superseded by the RS-232C standard of 1969and subsequent RS.232D of 1986. The definition of the pulse train is shown in Figure 12.16.

Start-bit + 7 or 8 data-bits + optional parity-bit + 1 (or 2) stop-bits.

Logical levels: between +3 and +15 V respectively -3 and -15 V. A data-1 is representedby the negative voltage level!

The LSB least significant bit is sent first of the data bits.

Figure 12.16: RS-232 serial data-byte timing waveform.

Asynchronous transmission is used with certain transmission speeds "baud-rates" (bit/s):300, 1200, 2400, 4800, 9600, 19200, ... baud.

The start-bit is used to synchronize the transmission. The two independent oscillators atthe transmitting and receiving ends need only be roughly equal so that the bits in one 7- or 8-bitdata are not out of phase.


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The parity bit is used to detect errors in the transmission. At even parity the number ofdata ones + the parity bit should be even, e.g. for ASCII-C (hex. 43 = 100 0011) the parity bit isset = 1 but not for A and B (100 0001 and 100 0010). Similarly for odd parity. If an incorrect

parity is detected the computer may ask for a new transmission of that character.

Example: start-bit + 7 data bits + parity-bit + 1 stop-bit and 9600 baud corresponds to 960characters/s transmission speed. One screen full of text contains about 1900 characters and takesabout 2 s to transfer. Modern (1997) modems transmit data with 56K bps over the telephone lines,using special data compression. More info:http://pclt.cis.yale.edu/pclt/COMISDN/ISDNIDEA.HTM .

This is the communications configuration panel from Windows Terminal. The use of 5 bits percharacter was used by very early Teletype equipment that was already obsolete in the 1950's, and nodevice built in the last 20 years has needed more than 1 stop bit. What is Xon/Xoff Flow Control?XON and XOFF are byte values. The Teletype had a device to read punched paper tape. The XONcharacter turned the tape reader on, and the XOFF character turned it off. Long after the last papertape was burned, computers have maintained the tradition that XOFF can optionally mean "stopsending data," in which case XON means "begin sending again." What is parity? Before modemsdid error correction, parity provided a simple mechanism to detect characters corrupted by phoneline noise. Today it is unnecessary and is typically disabled.

So in current use, the correct setting for the COM port is always 8-bit characters, no parity, 1 stopbit, hardware pacing (more about that later) and some speed faster that the native transmissionspeed of the modem.

Table 6: The 10 most important RS-232 signals (of 22) and the corresponding pin numbers on 25-pin and 9-pin connectors.

Name Pin #

(25)

Pin #

(9)

Direction

DTEDCE

Function as seen by DTE

TD 2 3 --> transmitted data

RD 3 2


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RTS 4 7 --> request to send (=DTE ready)

CTS 5 8 data terminal ready

DSR 6 6


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Figure 12.17: Different ways of connecting a DTE and a DCE. In particular fig b) and d) arecommon since only 3 wires are needed (but more often 4 with separate grounds).

Table 7: Different Serial standards

Serial data standards: RS-232C/D RS-423A RS-422A RS-485

Mode single-ended single-ended differential differential

Max number of drivers 1 1 1 32

Max number of receivers 1 10 10 32

Max cable length 15m (100m)1 1200m 1200m 1200m

Max data rate (bits/s) 19.2k (115k)1 100k 10M 10M

Transmit levels min / max 5V / 15V 3.6V / 6.0V 2V min 1.5V min

Receive sensitivity 3V 0.2V 0.2V 0.2V

Load impedance 3k - 7k >450 >100 >60


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Output current limit to gnd. 500mA 150mA 150mA 150mA

Driver Zout min (pwr off) 300 60k 60k 120k

1) Most RS-232 ports today are capable of far higher speeds and cable lengths than the rated standard.


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Standard serial communication is handled by a chip, called UART (Universal AsynchronousReceiver Transmitter), which implements the required transmitting and receiving, conversion ofdata from parallel to serial format and vice versa, etc. The Intel 16550 UART is the standard UARTfound in PCs today. The 8250 UART is found in older PCs.

The RS-232 and RS-422 standards specify only full-duplex communication, which means thattransmit and receive operations can take place simultaneously (separate lines). RS-485 alsospecifies half-duplex operation, in which a combined transmit and receive line is used - hence lesswires. Devices in a half-duplex network are used in a master/slave configuration, where slaves(devices) transmit only when they are instructed to do so by a master (PC).

In process industries and similar noisy environments a 4 - 20 mA analogue instrumentation is oftenstill used together with 20 mA current-loop digital transfer. This requires an extensive of point-to-

point wiring since each sensor or instrument must have its own pair to the controlling computer.

Fieldbus- "Fltbuss"(see http://hallen.ele.kth.se/~willi/Fieldbus.html ;http://rolf.ece.curtin.edu.au/~clive/Fieldbus/fieldbus.htm. and Elektroniktidningen 1, Jan.1997,

p.19.)Fieldbus is a generic-term which describes a new digital communications network which will beused in industry to replace the existing 4 - 20mA analogue signal. The network is a digital, bi-directional, multidrop, serial-bus, communications network used to link isolated field devices, suchas controllers, transducers, actuators and sensors. This new standard is on the way and has been sofor many years. The reason for the delay is due to the lack of an international Fieldbus protocolstandard which will ensure complete interchangeability and interoperability between differentsuppliers. Several company constellations have been fighting each others to have their ideas (anddeveloped chips) accepted. With consumers becoming impatient many companies have decided toreleased there own systems which work off different standards. Profibus is widely used in Germanyand Europe while DeviceNet is mostly popular in North America. CAN (Controller Area Network

http://www.kvaser.se) is based on DeviceNet.LANLocal Area Networkis the generic name of busses used for serial transmission with high speed between e.g. computers.

Ethernet: 10 Mbit/s, yellow thick coaxial cable with special connectors which avoids cutting thecable when a new unit is installed. From a "router" or a "hub" a group of computers are connectedvia "thin wire ethernet (usual coax. cable RG-58 with BNC-connectors) or twisted pair (TP).Information is sent in packages with address and data. All units may "talk", without any "chairman"- but special logic detects collisions. If the bus is busy the device waits a while and tries again. Mostcomputers and workstations at Uppsala University are connected through ethernet. The PC-computers at "Mttekniklab" are connected with a local thin wire Ethernet.

LocalTalk(former AppleTalk) is in particular used for connecting Macintosh and printers. 230kbit/s. Electrically as RS422 coupled to a transformer which allows both sending and receiving onthe same twisted pair of wires (differential driving) but the pulse train is different. Special logic toavoid collisions.

USB(Universal Serial Bus) will replace the old RS-232 port on most PCs from 1998 for externalcommunication with modems, instruments, mouse, keybord, etc. The USB is a "real" serial bus with12 Mb/s speed, where up to 127 units can be connected in a plug-and-play manner.

USB 1.1 USB 2.0 RS-232

12 Mbit/s (1.5) 480 Mbit/s 19.2 kbit/s (0.9 Mb/s)

Dynamic attach - detach, address assignment.
http://hallen.ele.kth.se/~willi/Fieldbus.htmlhttp://rolf.ece.curtin.edu.au/~clive/Fieldbus/fieldbus.htmhttp://www.kvaser.se/http://www.kvaser.se/http://hallen.ele.kth.se/~willi/Fieldbus.htmlhttp://rolf.ece.curtin.edu.au/~clive/Fieldbus/fieldbus.htmhttp://www.kvaser.se/


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Standard data format - "plug-and-play".Polled bus with a host controller.1) Token packet - with addressing (controller)2) Data packet (by sending device)3) Handshake packet (by receiving device).

More info: http://www.pcwebopedia.com/USB.htm andhttp://www.intel.com/design/usb/tour/homepage.htm

Firewire (IEEE 1394) is also a new serial bus which is supposed to take over the communicationwith fast units such as video signals and external data storage. The present maximum speed is 400Mb/s but 1600 Mb/s is on the way. More info: http://www.pcwebopedia.com/IEEE_1394.htm

Table 8 : 7 bit ASCII-code for characters. Additional 128 characters are possible with the 8:th bit=1, including the Swedish , but this code is not part of the standard. Email uses a 8-bit iso-8859-1 character set but "quoted printable" code for is safer to use since some computers masks the8th bit.The table gives the code in hexadecimal numbers.

hex 0 1 2 3 4 5 6 7 8 9 A B C D E F

00 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI

01 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US

02 SP ! " # $ % & ' ( ) * + , - . /

03 0 1 2 3 4 5 6 7 8 9 : ; < = > ?

04 @ A B C D E F G H I J K L M N O

05 P Q R S T U V W X Y Z [ \ ] ^ _

06 ` a b c d e f g h i j k l m n o

07 p q r s t u v w x y z { | } ~ DEL

acronym name acronym name acronym name

NUL null SOH start of heading STX start of text

ETX end of text EOT end of transmit ENQ enquire

ACK acknowledge BEL bell BS backspace

HT horizontal tab LF line feed VT verical tab
http://www.pcwebopedia.com/USB.htmhttp://www.intel.com/design/usb/tour/homepage.htmhttp://www.pcwebopedia.com/IEEE_1394.htmhttp://www.pcwebopedia.com/USB.htmhttp://www.intel.com/design/usb/tour/homepage.htmhttp://www.pcwebopedia.com/IEEE_1394.htm


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FF form feed CR carriage return SO shift out

SI shift in DLE data line escape DC1 device control 1

DC2 device control 2 DC3 device control 3 DC4 device control 4

NAK negative acknowledge SYN synchronous idle ETB end of transmit block

CAN cancel EM end of medium SUB substitute

ESC escape FS file separator GS group separator

RS record separator US unit separator SP space character


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13. GPIB - IEEE 488 Computer Based Measuring Techniques

The IEEE 488 interface, often called the "General Purpose

Interface Bus" (GPIB), is a standard defined by the "Institute ofElectrical and Electronics Engineers" (IEEE) that is used totransfer data between computers and instruments. It was firstdeveloped by Hewlett-Packard and is still often called HP-IB intheir instrument manuals. The first standard was accepted in 1975but has since then expanded, last time in 1992 (IEEE 488.2) withSCPI (Standard Commands for Programmable Instruments).

A more detaid description of this "instrument bus" may be found in "Instrument CommunicationHandbook" from Iotech, Inc., but also in most manuals to instruments with GPIB and catalogues. AGPIB-tutorial from National Instruments catalogue is available at http://www.ni.com (search for"History of GPIB").

13.1 GPIB featuresGPIB is a cable based bus with a special connector which allows several instruments to beconnected in a star or linear configuration or in any combination. Each cable end have a combinedmale and female connector to allow parallel connection of cables at any device. Some of the keyfeatures of the IEEE 488 interface are:- Up to 15 devices may be connected to one bus.- Total bus length may be up to 20m and the distance between devices may be up to 2m.- One byte (8 bit) digital information is sent in parallel each time.- Message transactions are hardware handshaked using special bus lines.- Maximum data rate is 1 Mbyte/s.The limitations in maximum distance and number of units may be avoided by using special units -

bus extenders, bus expanders - from various companies. National Instruments has also suggested anew transfer protocol HS488 which allows up to 8 Mbyte/s transfer rate on the usual GPIB-cable.
http://www.ni.com/http://www.ni.com/


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Figure 13.1: GPIB bus connector with pin numbers and signals.

GPIB-signal drivers must be open collector logic which allows for a parallel, multidrop, connectionof all devices. Logical TRUE and data 1 is defined for voltages +2V(ca. TTL-levels). The 24 bus lines group into 4 categories:

Data lines: 8 lines DIO1 - DIO8, used to transfer data and commands, one byte at a time.

Note that the numbers start with 1 which correspond to bit 0 (20) in the data byte according tothe usual convention.

Handshakelines: 3 - used to control (handshake) the transfer of information on the data lines.

DAV Data ValidNDAC Not Data AcceptedNRFD Not Ready for Data

Control lines: 5 - for general control of instruments and bus activities.ATN AttentionIFC Interface ClearREN Remote EnableSRQ Service RequestEOI End or Identify

Ground lines: 8 - for shielding and signal returns (see Figure 13.1).

The connected devices may either be a system Controller ("chairman"), Talker or Listener. Acomputer has all these three functions. The Controller manages the control lines. There is only oneactive Controller but this function may be transferred to another computer or device with a specialcommand. An instrument such as a digital multimeter (DMM) must be able both to listen and talkwhile for instance a printer only need the listen function built into it. The Controller decides,

through the users control program, which unit that is addressed as an Talker and what units that areListeners.

The GPIB uses three handshake lines in a "We are ready - Here is data - We have got it" sequence totransfer information across the data bus. This protocol assures reliable data transfer at the ratedetermined by the slowest Listener.

Figure 13.2: IEEE-488 handshaking


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DAV is controlled by the active Talker. Before sending any data, the Talker verifies that NDAC isasserted (pulled down, active low) which indicates that all Listeners have accepted the previous data

byte. The Talker then places a byte on the data lines and waits until NRFD is unasserted (released,high) by all Listeners (wired-OR open collector logic). This indicates that all addressed Listenersare ready to accept information. The Talker asserts DAV (active low) to indicate the data on the data

bus is valid. Each Listener then releases NDAC when they have received and interpreted the data

and when all units have released NDAC the NDAC-line goes high. In other words, data transfersare asynchronous and occur at the rate of the slowest participating device.

Addressing: Each device on the GPIB-cable must have an unique address. Maximum 15 devicesmay be connected but 31 different addresses are possible, from 0 to 30. The address is normally set

by DIP switches or by front panel controls. The Controller-card in the computer has also an addresswhich is set at the installation or initialization of the software. GPIB has no separate address bus butuses the data bus and the control line ATN.

Control lines:ATN (Attention) is controlled by the Controller and distinguish between data and commands senton the data lines. When asserted (low) the information on the data bus is a general GPIB command

(see Table 13.1), which all devices must read. When it is unasserted (high) the information isinstead data to the active Listeners, such as a measured value from a DMM to a computer, or aninstrument specific setting instruction to a DMM from a computer program.

IFC (Interface Clear) initiates ("cleanup") the bus and the instruments.

REN (Remote Enable) sets all connected instruments in remote operation, not allowing manualsettings from the front panel.

EOI (End or Identify) is used to signal the last byte in a transferred data string. EOI is not alwaysnecessary; instead the last byte might be a special character, such as "carriage return" CR or "line-feed" LF. However, according to the new IEEE 488.2 standard EOI should be asserted (low) whilesending a LF as the last byte.

SRQ (Service Request) is a wired-OR line that is asserted by any instrument that desires theattention of the Controller (interrupt). The instrument may have data to send or some error hasoccurred such as an illegal received setting instruction. The Controller uses either "Serial Poll" orParallel Poll" to determine which instrument requested service.


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Table 13.1: General GPIB-commands

Command 7 bit ASCII hex.code Description

Addressing

TAD Talker address x10xxxxx adr + 40 Device adr becomes a Talker.

LAD Listener address x01xxxxx adr + 20 Device adr becomes a Listener.

UNL Unlisten x0111111 3F Inactivate Listeners.

UNT Untalk x1011111 5F Inactivate Talker.

Universal

LLO Local lock out x0010001 11 Prevent manual settings from the frontpanel of all connected instruments.

DCL Device clear x0010100 14 Initiate all devices to "power-on"conditions.

PPU Parallel-pollunconfigure

x0010101 15 Disable parallel Poll response

SPE Serial-poll enable x0011000 18 Enable devices to output its serial-pollstatus byte instead of its normal datawhen becoming a Talker.

SPD Serial-poll disable x0011001 19 Disable the previous response.

For addressed devices

GTL Go to local x0000001 1 allow the manual front panel controls.

SDC Selective DCL x0000100 4 As DCL but for addressed devices.

PPC Parallel-pollconfigure

x0000101 5 Enable parallel-poll response of aninstrument.

GET Group ExecuteTrigger

x0001000 8 Allow simultaneous action (triggering)of a group of instruments, such assampling data.

TCT Take control x0001001 9 Pass the Controller function to another


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device.

When the Controller performs a Serial Poll it sends SPE (Table 13.1) to one device at the time,according to the user program. The polled device responds by returning its status byte on the datalines. Bit 6 (DIO7) is TRUE (low) if the device had requested an interrupt (SRQ). The other bitsoften indicate the reason for the SRQ (see Figure 13.3). A program example in C++ is available atwww.fysik.uu.se/kurser/fy660/compendium/GPIB/srq.htm.

With a Parallel Poll the Controller can (through the user program) determine which device thatrequested an interrupt by examining a 8 bit parallel answer. Then SPE or other instrument specificcommands may be used to find out the reason. Although Parallel Poll is faster, Serial Poll is moreoften implemented in various instruments and easier to program.

Figure 13.3: Status register model in IEEE 488.2
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13.2 SoftwareThe GPIB Controller in a computer is normally a plug-in card on the computer bus, such as on thePCI or ISA-bus in PC:s. User-friendly control routines for the communication with this card is

normally included with the delivery and "low level programming" with commands like those inTable 13.1 is avoided. Three different methods for "high level programming" of GPIB will bediscussed here: Program language libraries, Windows DLL and DOS device drivers.

The software to a GPIB Controller-card include several functions and subroutines to differentprogramming languages, such as C, Pascal, Fortran and various forms of Basic. These libraries mustbe linked to the user program after this has been compiled. In a modern C-developmentenvironment the library is often listed in a "project file" and the prototypes of the called functionsand arguments are specified in an "#include" header file. In TurboPascal the library is listed in the"Uses"-statement. The routine names and parameters varies between different GPIB-card types andtheir manuals has to be consulted.

In Windows an existing program may dynamically link and execute "DLL-functions" duringexecution. On Macintosh computer such functions are called "Resources". The great advantage isthat the programmers and suppliers of commercial measuring and control programs, such asLabView, need not implement a large number of program libraries for different GPIB-cards. Insteadthey call a DLL-routine from the GPIB-card supplier, which should be installed on the computer.

"DOS Device driver" is an old method for communicating with a GPIB-card. A DOS device driveris a memory resident program which is installed at the startup of the computer. It redirects andinterprets all file I/O for a particular file name, such as IEEE, just as DOS provides file I/O links forkeyboard/screen (CON), printer (PRN) or serial port (COM1, COM2). These DOS I/O files may beaccessed from any program, or program language, which can read and write text-files line by line.

No special program library need to be linked to the users own program. DOS Device Drivers are notused on modern 32-bit Windows systems (WIN95 and newer).

The Virtual Instrumentation Software Architecture (VISA) is a comprehensive package forconfiguring, programming, and troubleshooting instrumentation systems comprised of VXI, VME,PXI, GPIB, and/or serial interfaces. The VXIplug&play Systems Alliance, founded in 1993,developed one specification for I/O software: VISA. It provides a common foundation for thedevelopment, delivery, and interoperability of high-level multivendor system software components,such as instrument drivers, soft front panels, and application software. An instrument driver is a setof software routines that control a programmable instrument. Each routine corresponds to a

programmatic operation such as configuring, reading from, writing to, and triggering the

instrument. Instrument drivers simplify instrument control and reduce test program developmenttime by eliminating the need to learn the programming protocol for each instrument.

In 1998, National Instruments, along with several other companies, formed the InterchangeableVirtual Instrument (IVI) Foundation (www.ivifoundation.org/). One of the most important featuresof IVI drivers is their ability to allow instruments to be interchanged in a system without modifyingthe test software. The IVI Foundation has defined five classes of instruments: DMMs,Oscilloscopes/Digitizers, Signal Generators, Switches, and Power Supplies. An IVI instrumentdriver that conforms to one of these classes may be substituted with another instrument of the sameclass, regardless of manufacturer or bus connection (GPIB, VXI, or computer based like PCI).

The following C++ sample program example uses direct entry to access the 32-bit dynamicallylinkable library GPIB-32.DLL from National Instruments. This library calls other DLL-files (GPIB-16.DLL, GPIB.DLL) more specific for each GPIB-card installed on the computer.
http://www.ivifoundation.org/http://www.ivifoundation.org/


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- The frequency is set to 1.23 kHz on a HP function generator with the instrument specificinstruction "FR1.23KH" according to the instrument manual. Note that most instruments usedecimal point and misinterpret decimal comma. The HP function generator also requiresinstructions in capital letters, while most other instruments understand both.

- The measured value from a Fluke 45 digital multimeter is read by first sending a request for avalue "MEAS?" (according to the instrument manual) and then getting the value.

- All other settings of the instruments, such as wave form, amplitude, DMM-range, etc., aresupposed to be done manually. The HP-function generator has the GPIB-address 17 and the DMMthe address 7.

/* gpibdemo.cpp: console application using Microsoft Visual C++.

Uses NI-488.2 direct entry points to GPIB-32.dll driver from National Instruments:http://www.ni.com/gpib/win98_95cr.htmFor more info see: files included in the downloadable compat21.zip

NI-488.2M Function reference Manual for Win32 can be downloaded from:http://digital.ni.com/manuals.nsf/Coded by [email protected] Dec.2000

*/#include #include #include #include #include #include "decl-32.h" // type declarations used in GPIB-32.DLL

// NI-488.2 Function Prototypes used by this demo programstatic void (__stdcall *PSendIFC) (int boardID);static void (__stdcall *PEnableRemote) (int boardID, Addr4882_t * addrlist);static void (__stdcall *PSend)

(int boardID, Addr4882_t addr, PVOID databuf, LONG datacnt, int eotMode);static void (__stdcall *PReceive)

(int boardID, Addr4882_t addr, PVOID buffer, LONG cnt, int Termination);

static HINSTANCE Gpib32Lib = NULL; // global handle to DLLstatic int *Pibsta; // global status variablestatic int *Piberr; // global error variable

static long *Pibcntl; // global count variable

void main(void){char buf[80];LONG buflen;Addr4882_t addr[2]={7,17}; // used GPIB addressesfloat f,v;

// Call LoadLibrary to load the 32-bit GPIB DLL.Gpib32Lib = LoadLibrary ("GPIB-32.DLL");

if (!Gpib32Lib) {cout


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}// GPIB library is loaded. Get pointers to the requested functions and globals.Pibsta = (int *) GetProcAddress(Gpib32Lib, (LPCSTR)"user_ibsta");Piberr = (int *) GetProcAddress(Gpib32Lib, (LPCSTR)"user_iberr");Pibcntl = (long *)GetProcAddress(Gpib32Lib, (LPCSTR)"user_ibcnt");PSendIFC = (void (__stdcall *)(int))

GetProcAddress(Gpib32Lib, (LPCSTR)"SendIFC");PSend = (void (__stdcall *)(int, Addr4882_t, PVOID, LONG, int))GetProcAddress(Gpib32Lib, (LPCSTR)"Send");

PReceive = (void (__stdcall *)(int, Addr4882_t, PVOID, LONG, int))GetProcAddress(Gpib32Lib, (LPCSTR)"Receive");

PEnableRemote = (void (__stdcall *)(int, Addr4882_t *))GetProcAddress(Gpib32Lib, (LPCSTR)"EnableRemote");

if(!Pibsta || !Piberr || !Pibcntl ||!PSendIFC || !PSend || !PReceive || !PEnableRemote) {

cout


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MATLABMEX-files ("Matlab Executable") are dynamically linked subroutines produced from C or Fortransource code that, when compiled, can be run from within Matlab in the same way as m-files or

built-in functions. Using similar code as in the previous C/C++ program example one can call theGPIB-functions also from a Matlab program.ExcelUsing Visual Basic VBA-macros one can call the GPIB-32.dll driver in a similar manner as in theC/C++-program example. An example may be downloaded from www.ni.com (search on "Calling

NI-488.2 Functiuons Directly in Excel").
http://www.ni.com/http://www.ni.com/


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Some useful NI-488.2functionsThe full NI-488.2M Function reference Manual for Win32 can be downloaded from:http://digital.ni.com/manuals.nsf/

void DevClear (int boardID, Addr4882_t address)boardID: The interface board number

address: Address of the device you want to clearDevClear sends the Selected Device Clear (SDC) GPIB message to the device described by address.If address is the constant NOADDR, then the Universal Device Clear (DCL) message is sent to alldevices.

void EnableLocal (int boardID, Addr4882_t *addrlist)boardID: The interface board numberaddrlist: A list of device addresses that is terminated by NOADDREnableLocal sends the Go To Local (GTL) GPIB message to all the devices described byaddrlist. This places the devices into local mode. If addrlist contains only the constant

NOADDR, then the Remote Enable (REN) GPIB line is unasserted.

void EnableRemote (int boardID, Addr4882_t *addrlist)boardID: The interface board number

addrlist: A list of device addresses that is terminated by NOADDREnableRemote asserts the Remote Enable (REN) GPIB line. All devices described byaddrlist are put into a listen-active state.

void ReadStatusByte (int boardID, Addr4882_t address, short *result)boardID: The interface board numberaddress: A device addressresult: Serial poll response byteReadStatusByte serial polls the device described by address. The response byte is stored in result.

void Receive (int boardID, Addr4882_t address,

void *buffer, long count, int termination)boardID: The interface board numberaddress: Address of a device to receive datacount: Number of bytes to readtermination: Description of the data termination mode (STOPend or an EOS character)

buffer: Stores the received data bytesReceive addresses the device described by address to talk and the interface board to listen.Then up to count bytes are read and placed into the buffer. Data bytes are read until eithercount bytes have been read or the termination condition is detected. If the terminationcondition is STOPend, the read is stopped when a byte is received with the EOI line asserted.Otherwise, the read is stopped when an 8-bit EOS character is detected. The actual numberof bytes transferred is returned in the global variable, ibcntl.


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void Send (int boardID, Addr4882_t address, void *buffer, long count, int eotmode)

boardID: The interface board numberaddress: Address of a device to which data is sent

buffer: The data bytes to be sentcount: Number of bytes to be senteotmode: The data termination mode: DABend, NULLend, or NLend

Send addresses the device described by address to listen and the interface board to talk.Then count bytes from buffer are sent to the device. The last byte is sent with the EOI line assertedif eotmode is DABend, or sent without the EOI line asserted if eotmode is NULLend. If eotmode is

NLend then a new line character ('\n') is sent with the EOI line asserted after the last byte of buffer.The actual number of bytes transferred is returned in the global variable, ibcntl.

void SendIFC (int boardID)boardID: The interface board numberSendIFC: is used as part of GPIB initialization. It forces the interface board to beController-In-Charge of the GPIB. It also ensures that the connected devices are allunaddressed and that the interface functions of the devices are in their idle states.

void TestSRQ (int boardID, short *result)boardID: The interface board numberresult: State of the SRQ line: non-zero if the line is asserted, zero if the line is not assertedTestSRQ returns the current state of the GPIB SRQ line in result. If SRQ is asserted, thenresult contains a non-zero value. Otherwise, result contains a zero. Use TestSRQ to getthe current state of the GPIB SRQ line. Use WaitSRQ to wait until SRQ is asserted.

void WaitSRQ (int boardID, short *result)boardID: The interface board numberresult: State of the SRQ line: non-zero if line is asserted, zero if line is not assertedWaitSRQ waits until either the GPIB SRQ line is asserted or the timeout period has expired.When WaitSRQ returns, result contains a non-zero if SRQ is asserted.Otherwise, result contains a zero. Use TestSRQ to get the current state of the GPIB SRQline. Use WaitSRQ to wait until SRQ is asserted.


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14. Analog and digital.

D/A and A/D-converters (DAC - ADC)Digital-to-analog and analog-to-digital converters serve as the link between the digital world

inside the computer and the analog signals to actuators and from sensors. A simple D/A-converter may be constructed with weighted resistors in a summing amplifier based on a op-amplifier. A more elegant and better solution is to use a "R-2R ladder" (Figure 14.1).

Figure .1: 4-bit DAC based on a R-2R ladder. The current through any of the 2R from asingle Dn=V (with the others =0) is V/3R, but this current is then successively halved at

each junction on its way to the opamp. Hence the necessary weighting by 2, corresponding

to the binary number (D3 D2 D1 D0) is achieved. Rf determines the final amplification. The

output voltage is negative but may be reversed with yet another opamp.

A "multiplying DAC" is a D/A-converter with variable external reference voltage (orcurrent). Output voltage = reference voltage multiplied with the digital number on the input.This is achieved in Figure 14.1 by connecting the inputs to a reference voltage and groundrespectively, via FET-switches controlled by the digital signal.

DAC specifications:

Number of bits, resolution, and voltagerange.Offset error, linearity etc.Speed: Slew-rate and settling-time.

Typical voltage range is from 0 to +10V with 12 bit resolution and a settling time of about5 s.

Three different and often used ADC principles will be discussed: parallel-encoded,

successive approximation and dual-slope. Other circuits are also useful such as VFC /VCO - Voltage to Frequency Converters / Oscillators. Special voltage controlled oscillatorscan convert a voltage to a square wave and the pulses are then counted during a known timeinterval. The output from the counter gives the binary information. May be useful when theinformation has to be transmitted in serial form (single wire) over long distances. ADCcharacteristic specifications are similar as for the DAC but "speed" is discussed in terms ofconversion rate.

Parallel-encoded ADC (Flash-ADC) has one comparator for each value defined by theresolution. Hence, an ADC with 3 bit resolution has 7 comparators which are encoded (seeFigure 14.2). They are very fast (3-10 ns) but expensive and with a relatively low (4-10 bit)

resolution. Typical application is in digital oscilloscopes.
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Figure .2:Parallel-encoded ("flash") ADC. The priority encoder 148 generates a digitaloutput corresponding to the highest comparator activated by the input voltage Vin.

Ramp ADC. A counter chip counts up the input to a D/A-converter (see Figure 14.3). TheDAC output is compared with the Vin voltage using a comparator. When the DAC voltage is

higher than the "unknown" voltage the counter is stopped via an enable or gate input on thecounter chip. Alternatively the clock pulse to the counter is gated with an AND. Nextconversion is starting from 0 again (see Figure 14.4).

Figure .3: The principle of the RAMP and SERVO-ADC. The zenerdiode on the comparator

output ensures approximate TTL-levels even when an ordinary opamp is used with 12Vdriving.

Servo ("fljning"). A modification of the RAMP-ADC where the comparator outputcontrols if the counter should count up or down. The least significant bit (LSB) will flip upand down all the time which requires special care in the software.

Successive approximation ADC. The same construction, with a DAC and a comparator, asabove but using a binary search method("intervallhalvering").a) First the highest bit (2n) is tried. If VDAC < Vx keep it (DAC=2n).

b) Then try the next bit (DAC + 2n-1). If VDAC < Vx keep it (DAC=DAC+2n-1), else not(DAC=DAC). And so on until all bits are examined. For n bit resolution n values are tested.

The counter in Figure 14.3 is replaced by special control logic which performs the describedsearch. Figure 14.4 compares the three different methods. Successive approximation is

perhaps the most common ADC. It is cheep, relatively fast (1-50 s) and has a relativelyhigh resolution (12-16 bit).


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Figure .4:Illustration of the three search methods for ADC based on a DAC and acomparator.

Dual slope ("dubbelramp") ADC:First the "unknown" voltage V is integrated during a certain time tref (a certain number ofclock pulses from a accurate oscillator). Then a negative reference voltage Vref is integrateduntil the integral value is zero again. The time t for this is related to V by V tref = Vref t. Thedigital information comes from the number of clock pulses presented on a counter. Highaccuracy, noise is reduced by the time integration, a high resolution (many bits) is easilyachieved (by longer integration time) but slow (ca 30 ms for 20 bit). This type of ADC isused in digital multimeters (DMM). Some more advanced DMM can set the "rate" (e.g. thedual-slope integration time), which affects the resolution of the instrument. Additionalintegration of the input signal before conversion is often also possible to set.

S/H Sample and hold.W

base computer based measuring techniques

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