Chng ta bit MLS dng c ch flow-based caching . Packet u tin ca mt flow mi phi c a ln MLS-RP x l bng Software trc , sau mi to ra cc thng tin ca flow v ghi vao cache . Nu trong mt mi trng mng m c rt nhiu flow c to ra lin tip , khin MLS-RP phi lm vic rt nhiu v tr nn qu ti . CEF ra i cho php xy dng tt c cc thng tin v flow v lu vo cache nh Hardware v thng tin trong cache lun lun c xy dng trc khi mt packet ca flow c nhn . thc hin c iu ny , CEF phi xy dng nn 2 table quan trng , l : - FIB ( Forwarding Information Base ) : Bng FIB c xy dng trc tip t Routing table . Khi routing table va c to xong th FIB cng c to thnh . N lu ip address ca next-hop cho mi destination trong mng . - Adjacency table : nh ngha ra cc MAC address ng vi mi next-hop ip address

INCLUDEPICTURE "http://tinypic.com/fanceg.jpg" \* MERGEFORMATINET

Ta thy rng thng tin ca route table v ARP cache c to ra v qun l bi Control plane . Bng FIB l mt sub-table ca Route table , n ch lu thng tin no cn thit cho n m thi . Cc thng tin gm : Destination ip address , prefix , next-hop . Cc thng tin v giao thc nh tuyn ca Control plane s khng c lu vo . Bng Adjacency table cng c to ra bi ARP cache . Thng tin trong FIB v Adjacency table s c Dataplane dng v x l bng hardware . C 2 loi CEF l Distributed CEF v Accelerated CEF . dCEF l k thut lm cho mi line card c mt bng CEF ring , cho php nhiu hot ng data plane hot ng cng mt lc . Route processor to ra mt bng master FIB v Adjacency table , sau bng ny s c phn phi cho mi dCEF line card . aCEF l mt tnh nng mi cho php h tr vi Supervisor 720 v hot ng tng t nh MLS . Line card s gi packet u tin ca flow cho supervisor engine , packet s c switch bng hardware v s dng master CEF , thng tin forwarding s c chuyn xung cho CEF table line card . Cc packet tip theo ca flow s c x l ngay ti line card .