automated design architecture for 1-d cellular automata using quantum cellular automata

0018-9340 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. Seehttp://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TC.2014.2366745, IEEE Transactions on Computers

IEEE TRANSACTIONS ON COMPUTERS, 2014 1

Automated Design Architecture for 1–D CellularAutomata using Quantum Cellular Automata

Vassilios A. Mardiris, Member, IEEE Georgios Ch. Sirakoulis, Member, IEEE and Ioannis G. Karafyllidis

F

Abstract—Cellular Automata (CAs) have been widely used to model andsimulate physical systems and processes. CAs have also been successfullyused as a VLSI architecture that proved to be very efficient at least interms of silicon–area utilization and clock–speed maximization. QuantumCellular Automata (QCAs) as one of the promising emerging technologiesfor nanoscale and quantum computing circuit implementation, provides veryhigh scale integration, very high switching frequency and extremely lowpower characteristics. In this paper we present a new automated design ar-chitecture and a tool, namely DATICAQ (Design Automation Tool of 1–d CAsusing QCAs), that builds a bridge between 1–d CAs as models of physicalsystems and processes and 1–d QCAs as nanoelectronic architecture. TheQCA implementation of CAs not only drives the already developed CAs cir-cuits to the nanoelectronics era but improves their performance significantly.The inputs of the proposed architecture are CA dimensionality, size, localrule, and initial and boundary conditions imposed by the particular problem.DATICAQ produces as output the layout of the QCA implementation of theparticular 1–d CA model. Simulations of CA models for zero and periodicboundary conditions and the corresponding QCA circuits showed that theCA models have been successfully implemented.

Index Terms—Cellular automata (CAs), Quantum cellular automata(QCAs), design automation, nanoelectronic circuits.

1 INTRODUCTION

N ANOELECTRONIC circuits are expected to replacegradually the CMOS circuits in the years to come.

Several possible nanotelectronic technologies have beenproposed by researchers, such as carbon nanotubes, siliconnanowires, quantum–dot cellular automata (QCA), single–electron transistors (SETs) and circuits, resonant tunnelingdiodes, and single–molecule devices, as reported by ITRS[1].

Single electronics can be defined as the control of trans-port and position of a single electron or a small number ofelectrons in nanometer structures [2]. Significant research isbeing done on the field of modelling and simulation of SETdevices and circuits [3], [4], [5], [6] which is accompaniedby the development of an efficient single electron circuittheory [7].

QCA is a field–coupled computing approach. QCA cellschange their states due to interactions with neighboringcells via electrostatic or magnetic fields. QCAs also offer

Vassilios A. Mardiris is with the Technological Educational Institute ofKavala, Kavala GR–65404, Greece (e–mail: [email protected]).Georgios Ch. Sirakoulis and Ioannis G. Karafyllidis are with the De-partment of Electrical and Computer Engineering, Democritus Univer-sity of Thrace, Xanthi GR67100, Greece (e–mails: [email protected],[email protected]).

a new computation and information representation methodwhich is referred to as processing–in–wire. In terms ofintegration level, a few nanometer QCA cells can befabricated using a self–assembly process [8], [9]. For thesefeature sizes the integration can reach densities of 1012cells/cm2 and the circuit switching frequency can be closeto a terahertz [1]. QCAs were introduced in 1993 by Lent etal. [10] and since then several logic gates and circuits havebeen proposed such as the binary wire [11], the majoritygate, AND, OR, NOT and XOR gates [12], bit–serial adder,full adder [13], [14], multiplier [15], multiplexer [16], [17],[18], flip–flop [19], [20], arithmetic logic units (ALU) [21]serial or parallel memories [22], [23] and Cellular Automatacells or models [17], [24]. Automated QCA layout toolswere introduced in [25], [26].

Both individual QCA cells and multiple QCA cell ar-rangements, such as wires and majority logic circuits,have been fabricated and tested [27]. The major problemof the semiconductor and metallic QCA implementationsis that they can only operate at cryogenic temperatures;nevertheless very recently a new fabrication method hasbeen proposed which leads to QCA circuits operatingat room temperature [74]. Research is also underway tofabricate molecular and magnetic QCAs [8], [28], [29].These last implementations may also offer a solution tothe aforementioned problem because they can operate atroom temperature [30].

Cellular Automata (CAs) are models of physical systems,where space and time are discrete and interactions are local[31]. Prior and more recent works proved that CAs arevery effective in simulating physical systems and solvingscientific problems, because they can capture the essentialfeatures of systems where global behaviour emerges fromthe collective effect of simple components which interactlocally [32], [33]. Furthermore, they can easily handle com-plex boundary and initial conditions, inhomogeneities andanisotropies [34]. Moreover, the CA approach is consistentwith the modern notion of unified space–time. In computerscience, space corresponds to memory and time to process-ing unit. In CA, memory (CA cell state) and processingunit (CA local rule) are inseparably related to a CA cell[35]. As a result, CAs have also been successfully used asa VLSI architecture and special computing machines havealso been developed based on the CA architecture [36]. Interms of circuit design and layout, ease of mask generation,




silicon–area utilization, and maximization of clock speed,CAs are perhaps one of the most suitable computationalstructures for VLSI realization [34], [35], [36], [38], [37].

More specifically, from circuit designing point of view,according to Toffoli [34], there are four main factorsthat determine the cost/performance ratio of an integratedcircuit, namely, circuit design and layout, ease of maskgeneration, silicon–area utilization, and maximization ofachievable clock speed; for a given technology, the latter isinversely proportional to the maximum length of the signalpaths and this is also one of the critical factors in QCAcircuit designing. CA circuit design reduces to the designof a single, relatively simple cell and layout is uniform.The whole mask for a large CA array (the cells with theirinternal connections as well as the interconnections betweencells) can be generated by a repetitive procedure so nocircuit area is wasted on long interconnection lines andbecause of local processing the length of critical pathsis small when compared to others QCAs designs andimplementations found in literature and is independent ofthe number of cells.

In the last two decades a wide variety of one–dimensional(1–d) CA applications have been proposed on severalscientific fields like: simulation of physical systems [38],[40], [52], biological modelling involving models for self–reproduction, biological structures and DNA sequences[41], [42], image processing [35], [43], [44], languagerecognition [45], [46], computer architectures [47], fractalsand chaos [48], [49], cryptography [50], computer networks[51], etc.

In this paper an automated Cellular Automata QCA de-sign architecture and the corresponding tool, are presentedfor the first time. With the proposed architecture, CA rulesand models can be implemented using QCAs, resulting inmuch better circuit characteristics in terms of area, clockfrequencies and power consumption compared to the classi-cal VLSI implementations. The QCA computational modelintroduces highly pipelined architectures with extremelyhigh speeds. The information is encoded by the config-uration of electrical charges inside the cells and not byelectrical current flows, thus it has extremely lower powerconsumption compared to the classical CMOS technology[62]. For the proposed architecture the length of criticalpaths is kept to minimal values and is independent of thenumber of CA cells. Although the auto–generated designin this paper assumes metal–based QCA implementation,the underlying principles also apply to molecular QCA.

The proposed architecture uses several types of basicQCA configurable building blocks, that have been designedin order to be able to produce any 1–d CA model, by con-figuring and assembling them properly. All QCA buildingblock designs are based on an universal 1–d CA cell QCAdesign, developed by the authors and presented in [37]. Theproposed architecture can automatically design the QCAcircuit that implements any 1–d CA model that comprisesCA cells operating with the same or any variety (hybrid) ofCA Wolfram rules [33]. The proposed tool, which will becalled DAT ICAQ (Design Automation Tool of 1–d CAs us-

ing QCAs), is a web–based application developed using thePHP programming language, and produces as output, theQCA design directly to its graphical interface. DAT ICAQcan also generate the QCA Designer file enabling thus theimmediate use of the well known QCADesigner [57] in thecase where the user wishes to use the produced QCA designas a part of a larger circuit.

The paper is organized as follows. The necessary back-ground on CAs and QCAs is given in Section 2. Thearchitecture of the automated design of 1–d CA with QCAas well as some application paradigms are presented inSection 3. In Section 4 the structure and the operation ofDAT ICAQ are also given. Finally, conclusions are drawnin Section 5.

2 CA AND QCA CIRCUITS

2.1 Cellular Automata

In this section a more formal definition of a CA will bepresented [51]. In general, a CA requires:

1) a regular lattice of cells covering a portion of a d–dimensional space;

2) a set C(~r, t) = (C1(~r, t),C2(~r, t), . . . ,Cm(~r, t)) of vari-ables attached to each site ~r of the lattice giving thelocal state of each cell at the time t = 0,1,2, . . .;

3) a rule R=(R1,R2, . . . ,Rm) which specifies the timeevolution of the states C(~r, t) in the followingway: C j(~r, t + 1) = R j(C(~r, t),C(~r +~δ1, t),C(~r +~δ2, t), . . . ,C(~r+~δq, t)), where ~r +~δk designate thecells belonging to a given neighborhood of cell ~r.

In the above definition, the rule R is identical for all sitesand it is applied simultaneously to each of them, leadingto a synchronous dynamics. It is important to notice thatthe rule is homogeneous, i.e. it does not depend explicitlyon the cell position ~r. However, spatial (or even temporal)inhomogeneities can be introduced by having some cellstates C j(~r) constantly at 1, in some given locations ofthe lattice, to mark particular cells for which a differentrule applies. Furthermore, in the above definition, the newstate at time t + 1 is only a function of the previous stateat time t. It is sometimes necessary to have a longermemory and introduce a dependence on the states at timet−1, t−2, ..., t− k. Such a situation is already included inthe definition, if one keeps a copy of the previous state inthe current state.

The neighborhood of cell~r is the spatial region in whicha cell needs to search in its vicinity. In principle, there isno restriction to the size of the neighborhood, except thatit is the same for all cells. However, in practice, it is oftenmade up of adjacent cells only [53]. For two–dimensional(2–d) CA, two neighborhoods are often considered [52]:The von Neumann neighborhood, which consists of acentral cell (the one which is to be updated) and its fourgeographical neighbors north, west, south and east. TheMoore neighborhood contains, in addition, second nearestneighbors: northeast, northwest, southeast and southwest,that is a total of nine cells. In practice, when simulatinga given CA rule, it is impossible to deal with an infinite




lattice. The system must be finite and have boundaries.Clearly, a site belonging to the lattice boundary does nothave the same neighborhood as other internal sites. In orderto define the behavior of these sites, the neighborhood isextending for the sites at the boundary. Extending of theneighborhood leads to various types of boundary conditionssuch as periodic (or cyclic), fixed, adiabatic or reflection[52].

In this paper, we focus on 1–d CA with two possiblestates per cell, i.e., C ∈ 0,1. In this case, the local transitionrule R is a function R : 0,1n→ 0,1 and the neighborhoodsize n is usually taken to be n = 2δ+1 such that:

C (r, t +1) = R(C(r−δ, t), . . . ,C(r, t), . . . ,C(r+δ, t)) (1)

where δ (positive integer) is a parameter, known as theradius, representing the standard 1–d cellular neighborhood.We shall furthermore limit ourselves to the δ = 1 case, i.e.,so–called elementary CA, for which the neighborhood sizeis n = 3:

R : {0,1}3→{0,1}C (r, t +1) = R(C(r−δ, t),C(r, t),C(r+δ, t)) (2)

The domain of R is the set of all 23 3–tuples, which givesrise to 28 = 256 distinct elementary rules. We will useWolfram’s decimal numbering convention for describingthese rules [33], e.g. R(111) = 1, R(110) = 0, R(101) = 1,R(100) = 1, R(011) = 1, R(010) = 0, R(001) = 0, R(000) =0, is denoted rule 184. For two–state CA a configurationof a size N grid at time t is a binary sequence C(t). Forfinite–size grids, spatially periodic boundary conditions arefrequently assumed, resulting in a circular grid; formally,this implies that cellular indices are computed modulus N.

Beyond the fact mentioned before that CAs have beensuccessfully applied to many scientific fields, one of theirmost profound characteristics is related with their universal-ity, as they represent Turing machines connected in parallel.In specific, von Neumann proved that a CA consistingof cells with four orthogonal neighbors and 29 possiblestates would be capable of simulating a universal Turingmachine [31]. Recently, a Turing machine was explicitlyimplemented using a CA that executes the well knowngame of life by P. Rendell [66]. Most amazingly still, even1–d CA can be universal. In the first place, Wolfram [65]gave an example of a 19–state universal 1–d next–nearestneighbor CA in which a block of 20 cells was used torepresent each single cell in the CA being emulated. Later,Wolfram [65] proved even that two states and nearest neigh-bor rules are sufficient for providing universal computationin a 1–d CA; in particular, the rule 110 elementary CA isuniversal. The implementation of 1–d CA with two statesper cell using basic QCA configurable building blockscan successfully lead to the implementation of Turing–like universal computing machines implemented in QCAarchitecture.

2.2 Quantum Cellular Automata

QCA is a nanoelectronic digital logic architecture in whichinformation is stored as configurations of electron pairs inquantum dot arrays. QCA use arrays of coupled quantumdots to build Boolean logic functions and to perform usefulcomputations. QCA take advantage of quantum mechanicaleffects to significantly reduce the size of digital circuits andoperate at high speeds in very low power levels.

Conventional digital technologies use ranges of voltageor current to represent binary values. In contrast, QCA usesthe position of electrons in quantum dots to represent binaryvalues “0” and “1”. QCA’s primary advantages are theexceptionally high logic integration derived from the smallsize of dots, the simplicity and the notably low power–delayproduct [54].

The basic building block of QCA devices is the QCAcell presented in Fig. 1. It consists of four quantum dotsin a square array coupled by tunnel barriers. The physicalmechanisms for interactions between dots are the Coulombinteractions and quantum–mechanical tunnelling. Electronsare able to tunnel between the dots, but cannot leave thecell. If two mobile electrons are placed in the cell, inthe ground state and in absence of external electrostaticinfluence, Coulomb repulsion will force the electrons todots on opposite corners [10]. The two possible chargeconfigurations are presented in Fig. 1 and are correspondingto binary “1” and “0”.

For an isolated cell, the two polarization states are en-ergetically equivalent. However when a neighboring QCAcell is near, the equivalency breaks and only one of thetwo states becomes the cell ground state [10]. Polarization,P measures the extent to which the charge distribution isaligned along one of the diagonal axes. If we label the fourdots from 1 to 4 anti–clockwise starting from the upperright dot of the cell, and assign ρi as the electron densityof the ith dot, P is defined as:

P =(ρ1 +ρ3)− (ρ2 +ρ4)

ρ1 +ρ2 +ρ3 +ρ4(3)

The polarization of non–isolated cell is determined basedon interaction between neighboring cells. Fig. 2 illustratesthe cell to cell response function for two neighboring cells[54]. The figure’s curve shows how the polarization P2of cell 2 changes for different values of the driver cell 1polarization P1.

The stability of a QCA circuit is based on the assumptionthat the system falls to the ground state every time it

P = +1 P = −1

“1” “0”

Electron

1 2

3 4

Quantum-dot

Tunnel

Junction

Fig. 1. The basic QCA cell.




cell 1 cell 2

0.0 -0.5 0.5 -1.0 1.0

-1.0

-0.5

0.0

0.5

1.0

P2

P1

Fig. 2. Cell to cell response function for two neighboring QCAcells.

is excited by the inputs. However, this is not alwaysguaranteed; so in this case the system settles in a metastablestate, affecting the functionality of the design. This problemcan be solved by adiabatic switching [54]. In adiabaticswitching the system is always kept in its instantaneousground state by using a clocking scheme sequence of fourperiodic phases. QCA cells receive the clock signal throughan electric field which can raise or lower the tunnellingbarrier between dots inside the cell. When the barrier is lowthe electrons can move from one dot to another accordingto the overall external electrostatic influence. In case ofhigh barriers the electrons are locked inside the dots sothe external fields can not change the state of the cell.The adiabatic switching clocking scheme consists of fourphases: Switch, Hold, Release and Relax.

At the beginning of the Switch phase, the QCA cells inthe zone are unpolarized since the cell tunneling barriersare low. During the switch phase the barriers are raised andthe QCA cells become polarized according to the state ofthe cells that drive the zone. The driver cells must belong toa different clocking zone and specifically at the hold phase(90◦ phase difference, leading). Switch phase is the clockphase that the actual computation (or switching) occurs.At the end of switch phase, barriers are high enough toblock any electron tunnelling and this locks the state ofthe cell. Next phase is the Hold phase. During this phasethe barriers remain high so the zone outputs can drive theinputs of the next clocking zone sub–circuit. The next zone(which is driven from our reference zone) must be at switchstate (90◦ phase difference, leading). At the Release phase,barriers are gradually lowered and finally cells are allowedto relax to an unpolarized state. Finally, during the fourthclock phase, the Relax phase, cell barriers remain loweredand cells remain in an unpolarized state.

In order to use the adiabatic switching clocking schemethe QCA circuit must be partitioned into clocking zones insuch a manner so that all cells in a clocking zone are con-trolled by the same clock. The clocking zone partitioning,is a crucial factor of the QCA design because the orderof appearance of the four clocking zones in the circuit,controls the flow direction of the signals inside the QCAcircuit.

A row of QCA cells acts like a wire usually called binarywire [11]. In QCA circuit designs of binary wires, invertersand three–input majority gates are the fundamental parts.The inverters are constructed with a fork structure andthe majority gates with a cross structure [12]. Coplanarbinary wire crossovers can also be implemented in QCAdesigns which is a very useful technique for designing morerealizable circuits [12].

3 PROPOSED QCA DESIGN ARCHITECTURE

The objective of the proposed architecture is to implement auniversal 1–d CA model circuit using QCA. To accomplishthis objective, several versions of one CA cell QCA circuitimplementations have been designed, which will be used asbuilding tiles of the final CA model. As it will be shownall proposed versions of CA cell QCA implementationshave exactly the same functional behaviour but they differin signal manipulation in terms of interconnection andsynchronization. Moreover it should be noticed that despitethe fact that some designs found in literature as for examplein [71] are using multi-layer wire crossovers, unfortunatelytill now there are still questions about how these multi-layercrossover designs can be realized in practice, since theyrequire two overlapping active layers with via connections[72]. As a result, in the proposed QCA design architectureonly coplanar crossovers are presented in all cases.

3.1 CA Cells Tile Design Principles

The 1–d CA functionality as described in the previoussection, includes a row of CA cells in which every CAcell can communicate only with their two neighbours (westand east CA cell). Every CA cell has three inputs and oneoutput. The output value of each CA cell at a given timeis calculated from the previous time step output values ofthe two neighbouring cells and from the previous time stepoutput value of the same cell, according to its Wolframrule. For the CA cell designs of the proposed architecture,the mapping of every possible input value (coming fromthe neighbourhood cells) to its corresponding output, isimplemented by an 8 to 1 multiplexer [17], [18]. TheWolfram rule the CA cell performs, is applied in its binaryform, to the 8–bit input bus of the multiplexer and the 3–bitselection bus of the multiplexer is formed by: a) the outputof the west neighbouring cell, b) the output of this celland c) the output of the east neighbouring cell, ordered asmentioned, from most to least significant bit. So in all CAcell designs of the proposed architecture, the output signalof the 8 to 1 multiplexer is feedbacked to the 2nd bit oftheir selection bus and is leaded also to the neighbouringcells.

As it has been mentioned before the present state of eachCA cell is evaluated according to the temporal previousstates of their neighbouring cells. Because of that the designmust have the initialization capability in order to start itsoperation. At the proposed architecture the initializationfunction is implemented by a 2 to 1 multiplexer across thefeedback wire of the output signal. The multiplexer selects




between the feedback and the initial value, to pass as inputfor the next CA cell calculation.

Very important factor for the CA cell designs to be func-tional correct at the proposed architecture, is that the outputsignals of the neighbouring cells must arrive simultaneouslyat the inputs of every CA cell. This is obvious and verysimple to implement in conventional VLSI design, but notvery easy to implement in a QCA design. The reason forthat is that the signal propagation via interconnection binarywires in QCA technology, imports as much or even moredelay than the processing elements of the design. So thedelays imported by the processing elements and by theinterconnection wires must be carefully summed for everyparallel route, in order to check the synchronization of allthe signals. Additionally a CA model is a parallel model inwhich the output states of the cells, all produced at the sametime at every time step. So because of that, the input signalsmust not only be synchronized between the three CA cellsof a local neighbourhood, but between all CA cells of theCA model. So because of that, the input signals must notonly be synchronized between the three CA cells of a localneighbourhood, but between all CA cells of the CA model.This design requirement precludes the use of hybrid CA cellimplementations [24] because in that case different ruledCA cells leads to QCA areas with significantly differentdimensions and consequently the input signals mentionedabove would not be synchronized.

At the proposed design architecture, every CA cell im-plementation includes three parallel routes. All three routesinclude the two multiplexer circuits described above so thedelay inserted by the processing elements is equal for allroutes. Consequently the synchronization problem is fo-cused to equalize the delay inserted by the interconnectionwires.

3.2 Routing and Placement

Generally the routing principles of QCA circuits are muchdifferent from these of the conventional VLSI circuits [70].In QCA circuit design the processing by wire capability iswidely used and many of the interconnection lines becomeprocessing elements for the circuit [63]. Processing by wirein QCAs, allows information manipulation while the signalpropagates on a binary wire. A characteristic paradigmof processing by wire is presented in the inverter chainimplementation [11].

Taking into account the previous statements, routing prin-ciples must be realized in combination with the placementof the design blocks which compose the QCA circuit.According to the proposed design architecture, every CAcell is implemented by a QCA design block. The wholeCA model is constructed by placing all the QCA blocks(implementing CA cells) on specific places. The intercon-nection wires between these QCA blocks can easily destroythe synchronization of the whole circuit. To avoid this,no interconnection wires between blocks have been used.Special QCA blocks were designed so that they can fitone beside the other without using interconnecting wires.

Additionally special care has been taken for the route of thefeedback wire inside each CA block, because it must crossinput and output wires of the cell, using the QCA coplanarcrossing scheme [11]. It also must synchronize the outputsignal with the inputs receiving from the neighboring cells.

The block topology is strongly affected by the boundaryconditions of the CA model. For zero boundary conditions,the inputs of the boundary CA cells which are not receivingsignals from a neighbour are set to zero. In this case a N cellCA model is formed using three types of cell blocks whichare placed forming a row. At this scheme the leftmost blocknamed ble f t, is taking inputs only from its right neighbourand puts a fixed zero value to its left neighbour input. Therightmost block named bright, is taking inputs only fromits left neighbour and puts a fixed zero value to its rightneighbour input. The remaining N–2 blocks named down,are taking inputs from their neighbours (Fig. 4). Howeverin periodic boundary conditions the west input of the westboundary CA cell is evaluated from the output of the eastboundary CA cell. The east input of the east boundary CAcell is evaluated from the output of the west boundary CAcell. In this case the CA cell blocks are placed forming aring allowing thus the boundary CA cells to communicateas neighbours (Fig. 8).

3.3 QCA Design Robustness Issues

All CA model QCA designs, to be functional and robust,they must comply with a number of significant QCA designrules. Because of the propagation delays and power lossbetween cell–to–cell interactions, there should be a limiton the maximum signal propagation path length in eachclock zone. Additionally, short wire lengths result in circuitoperation in higher clock rates [14]. At nonzero Kelvintemperatures, higher operating temperatures lead to higherthermal fluctuations, which increase the probability for akink to occur (a QCA cell to align differently from itsexpected polarization) [10], [55]. It has been proved [10],that the maximum QCA line length for kink–free operationis given by:

N ≤ eEk

kbT (4)

where Ek represents the energy required for a QCA cellto encounter a kink, kb is the Boltzmann’s constant and Tis the temperature of operation. So it can be also impliedthat a QCA circuit having short wire lengths can operatewithout kinks at higher temperatures than a QCA circuitwith longer wire lengths. Short wire lengths result tosmall clocking zones which may lead to more complicatedclock distribution circuitry. In the proposed architecturethe two–dimensional wave clocking scheme [17] is usedto simplify clocking circuitry distribution using parallelclocking wires. The above clocking scheme also facilitatesthe clock distribution circuitry [17].

All QCA circuits implemented using the presented ar-chitecture have maximum wire length under 14 QCA cellsmuch less than the acceptable limit of 28 QCA cells wirelength for 1THz clock rate proposed at [56], [64], so that




taking into account equation 4 they can operate avoid-ing kinks at higher temperatures. Another design require-ment concerning interactions between different signals fromnearby wires is the minimum wire spacing. All designsproposed in this paper are following the minimum wirespacing limit of two (2) cells proposed in [64].

3.4 8 to 1 Multiplexer and CA Cell QCA Implementation

As have been mentioned in previous section, the 8 to 1 mul-tiplexer design is the key component of the CA model QCAdesign architecture. The proposed QCA implementation ofthe 8 to 1 multiplexer with the feedback path forming theCA cell is illustrated in Fig 3. The signal processing flowinside the proposed QCA circuit starts from the upper leftcorner and propagates on a diagonal profile to the bottomright corner, where the output is produced implementinga 2–d clocking scheme [16]. The 8 input signals of themultiplexer, corresponding to the 8–bit Wolfram rule, arecrossing the circuit through horizontal binary wires andthe selection bus input signals are crossing the circuitvertically through inverter chains forming an 8×3 wiregrid. The QCA coplanar crossing scheme is taking placeon every crossing point of the previous mentioned wires.Additionally next to every crossing point, an AND gatebetween the two crossing signals is implemented, in orderfor the selection signals to enable or disable the horizontalpropagation of the input signals. Only one of the eightinput signals is allowed to propagate horizontally to theright edge of the grid and this signal is forwarded to themultiplexer’s output trough a sequence of OR gates. Thenthe output signal is forwarded through binary wires: (a) toselection bus least significant bit of the west neighbouringCA cell, (b) to selection bus most significant bit of the eastneighbouring CA cell and (c) to the selection bus 2nd bitof this CA cell. The signal in this feedback path is crossingthrough a 2 to 1 multiplexer. The selection bit (load init)of the 2 to 1 multiplexer decides if the feedback signal orthe CA cell initialization signal (init) will pass to the 2nd

bit input of the CA cell.

3.5 CA Cell Tiles QCA Implementations

In order to apply the proposed design architecture asdescribed previously, several versions of the basic CAcell QCA implementations must be implemented. Theseimplementations for zero and periodic boundary conditionsCA model are presented below.

3.5.1 Zero Boundary Conditions

In case of zero boundary conditions, as have been men-tioned before CA cell blocks are placed on a row and threetypes of CA cell blocks are used (Fig. 4). The leftmostblock named ble f t which is taking inputs only from its rightneighbour. The rightmost named bright which is takinginputs only from its left neighbour. And the block nameddown which is taking inputs from both its neighbours.Every block includes a QCA circuit which is formed byan arrangement of QCA cells on the grid. In the proposed

Fig. 3. QCA implementation of the basic CA cell whichconsists of an 8 to 1 multiplexer and the feedback path ofits output to the CA cell’s input through a 2 to 1 multiplexer.

architecture, the QCA implementations of all three blockshave the same height in rows and communicate with eachother only through row 53 and 59 on the grid counting frombottom to top. More specifically, the down block receivesthe output of its left neighbour from the left edge of row53 and sends its output to its right neighbour through rightedge of row 53. The down also receives the output of itsright neighbour from the right edge of row 59 and sends itsoutput to its left neighbour through left edge of row 59. Theble f t block receives only the output of its right neighbourfrom the right edge of row 59 and sends its output only toits right neighbour through right edge of row 53. And thebright block receives only the output of its left neighbourfrom the left edge of row 53 and sends its output onlyto its left neighbour through left edge of row 59. Usingthis input/output signal arrangement it is obvious that ifthe blocks are placed on a horizontal row according to Fig.4 the implemented CA cells will communicate successfullyforming a CA model. The model outputs its next state every6 clock cycles or 24 clock phases, which is the time everyCA input signal needs to propagate to its neighbouring CAcell input. It should be stated that this propagation time isindependent of the length of the CA model.

All blocks include the initialization input signals init and




load init in order to set the initial state of the CA cell.The init signal defines the value of the initial state andthe load init signal controls when the initialization will bedone. The 8–bit CA rule is representing by the 8 fixedvalued QCA cells on the left side of the block, which areevaluating the multiplexer’s input bus.

Fig. 5 depicts the QCA implementations of the threeblocks required as tiles by the proposed CA model QCAdesign architecture in the case of zero boundary conditions.All the QCA circuits are using a 2–d clocking scheme[16], [17], [18] propagating the signals from the left upto the right down design’s corner on a diagonal profile asmentioned before. The QCA circuits were designed andsimulated using the QCA Designer tool. In the environmentof the previous mentioned tool, the overall QCA celldimensions are defined to 18× 18nm2, the dot diameterto 5nm and the inter–cell distance to 2nm.

According to the QCA Designer tool the design of theble f t and down blocks consists of 670 and 676 cells,respectively and they are both covering an area of 28×65.5QCA grid cells or 558× 1308 nm2 that is approximately0.73µm2. The bright block design consists of 639 cells cov-ering an area of 26×65.5 QCA grid cells or 518×1308nm2

that is approximately 0.68µm2. All QCA implementationsof the proposed CA blocks were simulated exhaustivelyusing the QCA Designer simulator to confirm their func-tional correctness. For the simulation, the Euler Method,coherence vector simulation engine of the QCADesignertool is been used, with Relaxation time 1e−15sec, Timestep 1e−16sec, Radius of Effect 80nm and 1THz clockrate, which are the proposed values of the Simulator. Thesimulation input vectors are generated automatically by theDATICAQ tool taking into account the data entered in thecontrol panel of the user interface.

A paradigm of a QCA design for a five (5) cellsCA model which uses rule 30, implemented accordingto the proposed architecture, is presented in Fig. 6. Theresulting design consists of 3337 cells covering an areaof 2758× 1308nm2 that is approximately 3.61µm2. It iscovering an area of 138× 65.5 grid cells and the ratio ofthe area covered by QCA cells to the overall area of thelayout is about 0.369 more than 1/3.

In general by using the here proposed architecture, fora QCA design implementing a CA model consisting of nnumber of CA cells, in case of zero boundary conditions,the area that it covers in grid cells can be calculated using

Block

bleft …

Block

down

Block

down

Block

bright

Fig. 4. Block diagram for the CA model implementation withzero boundary conditions.

load_init

init-1

-1

CAval

-1

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

load_init

init-1

-1

CAval

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

load_init

init-1

-1

CAval

1

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

(a) (b) (c)

Fig. 5. QCA implementations of the three blocks used by thetool in the case of zero boundary conditions: a) ble f t block,b) down block, c) bright block.

the equations:

Circuit Area =CircuitWidth×CircuitHeight =

(ble f tWidth+(n−2)×downWidth+brightWidth)

×downHeight = (28+(n−2)×26)×65.5(5)

which eventually equals to:

Circuit Area = 1834×n−131 (6)

and the number of the QCA cells of the design can becalculated using the equation:

Number o f QCA cells

= ble f tCells+(n−2)×downCells+brightCells

= 670+(n−2)×676+639(7)

which results to:

Number o f QCA cells = 676×n−43 (8)

The ratio (R) of the area covered by QCA cells to theoverall area of the circuit layout can be calculated usingthe following equation:

R = (676×n−43)/(1834×n−131) (9)

where n is the number of the CA cells.The simulation results of the design, acquired by the

QCA Designer coherence vector simulation engine, are pre-sented in Fig. 7. The input signals are presented with bluewaveforms and the output signals with brown waveforms.In the beginning of the simulation, all the load init signalsare set to zero in order to set the initial state of the CAmodel 00010 using the values of the init signals. At thenext time step the load init signals are set to one directingthe circuit to operate in normal mode which is the CAevolution process with Wolfram rule 30. The circuit outputsthe next state of the CA model every 6 clock cycles. At theright upper corner of the figure, a frame is appearing which




load_init_4

init_4-1

-1

cell_4

-1

-1

-1 -1 -1

1 1

1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

-1 1

-1 -1 -1

-1

1

load_init_3

init_3-1

-1

cell_3

-1

-1 -1 -1

1 1

1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

-1 1

-1 -1 -1

-1

1

load_init_2

init_2-1

-1

cell_2

-1

-1 -1 -1

1 1

1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

-1 1

-1 -1 -1

-1

1

load_init_1

init_1-1

-1

cell_1

-1

-1 -1 -1

1 1

1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

-1 1

-1 -1 -1

-1

1

load_init_0

init_0-1

-1

cell_0

1

-1

-1 -1 -1

1 1

1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

-1 1

-1 -1 -1

-1

1

Fig. 6. The QCA design of a 5 cells zero boundary conditionsCA model.

max: 1.00e+000

min: -1.00e+000load_init_4

max: 0.00e+000

min: -1.00e+000init_4

max: 1.00e+000


max: 0.00e+000

min: -1.00e+000init_3

max: 1.00e+000


max: 0.00e+000

min: -1.00e+000init_2

max: 1.00e+000


max: 1.00e+000

min: 0.00e+000init_1

max: 1.00e+000


max: 0.00e+000

min: -1.00e+000init_0

max: 9.76e-001

min: -9.76e-001cell_4

max: 9.94e-001

min: -9.94e-001cell_3

max: 9.94e-001

min: -9.94e-001cell_2

max: 9.94e-001

min: -9.94e-001cell_1

max: 9.94e-001

min: -9.94e-001cell_0

0 99 198 297 396 495 594 693 792 891 990 1089 1188 1287 1386 1485 1584 1683 1782 1881 1980 2079 2178 2277 2376 2475 2574 2673 2772 2871 2970

Simulation Results

Fig. 7. Simulation results of the QCA circuit for a 5 cells CAmodel with zero boundary conditions.

presents the expected states of the corresponding 1–d CAmodel through the evolution process.

3.5.2 Periodic Boundary Conditions

In case of periodic boundary conditions the CA cell blocksare placed on a ring in such a way so that every CA cellcommunicates with its two neighbors. The block placementarchitecture used by the tool in the case of periodic bound-ary conditions is presented in Fig. 8. The ring shape isconstructed by two curves (left and right) and two rows (upand down). The left curve is composed of the blocks le f t,le f t−up and le f t−down and the right curve is composedof the blocks right, right−up and right−down as shown inFig. 8. The up row is composed of n identical blocks named

up and the down row is composed of n identical blockednamed down and are exactly same with the down blocksthe system uses in the case of zero boundary conditions.The number of the blocks in up and down rows must bethe same in order for the ring structure to be completed.

Because of the circuit request described in subsection 3.2about the synchronization of CA cells’ output signals, thewires carrying the CA cells’ input/output signals must beas short as possible. Consequently the communication ringformed by the CA cells must be as short as possible. Inmore details and in order for the architecture to complywith this requirement, the up–row blocks must providetheir communication signals near their bottom side, thedown–row blocks must provide its communication signalsnear their top side, the left–curve blocks must provide itscommunication signals near their right side and the right–curve blocks must provide their communication signals neartheir left side.

Implementing the above scheme in the proposed architec-ture, the QCA implementations of the blocks le f t−down,down, right−down, le f t−up, up and right−up all havethe same height in rows. The down and le f t−down blocksreceive neighbour signals from row 53 left–side and row59 right–side, respectively and send their signals throughrow 59 left–side and row 53 right–side counting frombottom to top, as described previously. The right− downblock receives neighbour signals from row 53 left–side andcolumn 9 top–side and sends its signal through row 59 left–side and column 3 top–side, counting from bottom to topand from right to left. The up and right−up blocks receiveneighbour signals from row 59 left–side and row 53 right–side and send their signals through row 53 left–side and row59 right–side counting from top to bottom. The le f t−upblock receives neighbour signals from row 53 right–sideand column 9 bottom–side and sends its signal through row59 right–side and column 3 bottom–side, counting from topto bottom and from left to right. Finally, the le f t blockreceives neighbour signals from column 53 top–side androw 7 right–side and sends its signal through column 59top–side and row 1 right–side, counting from bottom totop and from left to right, while the right block receivesneighbour signals from column 53 bottom–side and row 7left–side and sends its signal through column 59 bottom–side and row 1 left–side, counting from top to bottom andfrom right to left, respectively. The model outputs its next

Block

left-up

…

Block

up

Block

up

Block

right-up

Block

left

Block

right

Block

down

Block

left-down

…

Block

down

Block

right-down

Fig. 8. The block placement diagram in case of periodicboundary conditions.




state every 6 clock cycles or 24 clock phases, as in thecase of zero boundary conditions and the propagation timeis also independent from the length of the CA model.

All blocks include the initialization signals init andload init and the CA rule is represented by a row of fixedvalued QCA cells setting the input bus of the 8 to 1 mul-tiplexer as have been described before for the case of zeroboundary conditions. Using the above input/output signalarrangement, if the blocks are placed on the ring schemaof Fig. 8 they will communicate successfully forming a CAmodel.

The QCA implementations of the eight blocks requiredas tiles by the proposed CA model QCA design architecturein case of periodic boundary conditions are representedin Fig. 9. For all block implementations it can be seenthat the feedback’s path delay is 14 clock phases and isequal to the delay of paths carrying CA cell’s output tothe neighbouring cells. The QCA circuits were designedand simulated using the QCA Designer tool with the sameparameters as in the case of zero boundary conditions.According to the QCA Designer tool the design of thetool the blocks le f t, le f t − up, right and right − downconsist of 669, 665, 669 and 665 QCA cells, respectivelyand they are covering an area of 26× 65.5 QCA gridcells or 518× 1308nm2 that is approximately 0.68µm2.The blocks up, right − up, down and le f t − down, allconsist of 675 QCA cells and they are covering an areaof 28× 65.5 QCA grid cells or 558× 1308nm2 that isapproximately 0.68µm2. All QCA blocks were simulatedsuccessfully using the QCA Designer Simulator with thesame parameters mentioned before.

Fig. 10 presents a QCA layout of a ten cell circuit thatmodels CA rule 90 with periodic boundary conditions. Thecircuit consists of 6718 cells covering an area of 4458×2818nm2 that is approximately 12.56µm2. It is coveringan area of 223× 141 grid cells and the ratio of the areacovered by QCA cells to the overall area of the layout isabout 0.214.

The simulation results of the aforementioned circuitdesign, acquired by the QCA Designer coherence vectorsimulation engine and in accordance with the previousones mentioned in case of zero boundary conditions, arepresented in Fig. 11. In this figure the upper eleven wave-forms correspond to input signals, and the remaining tenwaveforms, presented in different color, correspond to theten CAs’ output signals. The four clock signals and theload init signals are omitted intentionally for readabilityreasons. For the simulation all load init signals have thesame shape like the load init 0 which is presented.

At the simulation time, firstly all the load init signals areset to zero in order to set the initial state of the CA modelto 0000000100 using the values of the init signals fromload init 9 (msb) to load init 0 (lsb). At the next time stepthe load init signals are set to one directing the circuit tooperate in normal mode which is the CA evolution processwith Wolfram rule 90. The circuit gives the next state of theCA model every 6 clock cycles. After a new state appearson the outputs, the signals remain stuck at their current

load_init

init

-1

-1

CAval

-1

-1

-1

-1

1

1

1

1

-1

-1

-1

1

1

1

1

-1

-1

-1

-1

1

-1

1

-1

-1

-1

-1

1

(a)

load_init

init

-1

-1

QCAval

-1

-1

-1

-1

1

1

1

1

-1

-1

-1

1

1

1

1

-1

-1

-1

-1

1

-1

1

-1

-1

-1

-1

1

(b)

load_init

init -1

-1

CAval

-1

-1-1-1

11

11

-1-1-1

11

11

-1-1-1

-11

-11

-1-1-1

-1

1

load_init

init-1

-1

CAval

-1

-1-1-1

11

11

-1-1-1

11

11

-1-1-1

-11

-11

-1-1-1

-1

1

load_init

init-1

-1

-1

-1-1-1

11

11

-1-1-1

11

11

-1-1-1

-11

-11

-1-1-1

-1

1

(c) (d) (e)

load_init

init-1

-1

CAval

-1

-1 -1 -1

1 1

1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

-1 1

-1 -1 -1

-1

1

load_init

init-1

-1

CAval

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

load_init

init-1

-1

CAval

-1

-1 -1 -1

1 1

1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

-1 1

-1 -1 -1

-1

1

(f) (g) (h)

Fig. 9. QCA implementations of the three blocks used bythe tool in case of zero boundary conditions: a) le f t block,b) right block, c) le f t− up block, d) up block, e) right− upblock, f) le f t− down block, g) down block, h) right− downblock.

values until the next state arrives on circuit outputs. At theright upper corner of the Fig. 9, a frame is appearing whichpresents the expected states of the corresponding 1–d CAmodel through the evolution process.




load_init_9

init_9

-1

-1

cell_9

-1

-1

-1

-1

1

1

-1

1

-1

-1

-1

1

1

1

1

-1

-1

-1

-1

1

1

1

-1

-1

-1

-1

1

load_init_8

init_8-1

-1

cell_8

-1

-1-1-1

11

-11

-1-1-1

11

11

-1-1-1

-11

11

-1-1-1

-1

1

load_init_7

init_7-1

-1

cell_7

-1

-1-1-1

11

-11

-1-1-1

11

11

-1-1-1

-11

11

-1-1-1

-1

1

load_init_6

init_6-1

-1

cell_6

-1

-1-1-1

11

-11

-1-1-1

11

11

-1-1-1

-11

11

-1-1-1

-1

1

load_init_5

init_5-1

-1

cell_5

-1

-1-1-1

11

-11

-1-1-1

11

11

-1-1-1

-11

11

-1-1-1

-1

1

load_init_4

init_4

-1

-1

cell_4

-1

-1

-1

-1

1

1

-1

1

-1

-1

-1

1

1

1

1

-1

-1

-1

-1

1

1

1

-1

-1

-1

-1

1

load_init_3

init_3-1

-1

cell_3

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

load_init_2

init_2-1

-1

cell_2

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

load_init_1

init_1-1

-1

cell_1

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

load_init_0

init_0-1

-1

cell_0

-1

-1 -1 -1

1 1

-1 1

-1 -1 -1

1 1

1 1

-1 -1 -1

-1 1

1 1

-1 -1 -1

-1

1

Fig. 10. The QCA design of a 10 cells periodic boundary conditions CA model.

In general, for a QCA design produced according to theproposed architecture and implementing a CA model withn CA cells in case of periodic boundary conditions, thearea that it covers in grid cells can be calculated using thefollowing equations:

Circuit Area =CircuitWidth×CircuitHeight

= (le f t.le f tup.CornerWidth+[(n−6)/2]×upWidth

+ rightup.rightCorner.Width)× (upHeight

+ blanc.spaceHeight +downHeight)

= (76+[(n−6)/2]×28+91)×65.5+10+65.5(10)

which eventually equals to

Circuit Area = 1974×n+11703 (11)

The number of the QCA cells of the design can becalculated using the equations:

Number o f QCA cells

= le f tCells+ le f tupCells+ le f tdownCells

+[(n−6)/2]×upCells+[(n−6)/2]×downCells

+ rightCells+ rightupCells+ rightdownCells

= 669+665+675+670+[(n−6)/2]×675+669+675+665

(12)

or in another words:

Number o f QCA cells = 675×n−32 (13)

The ratio (R) of the area covered by QCA cells to theoverall area of the circuit layout can be calculated usingthe equation:

R = (675×n−32)/(1974×n−11703) (14)

where n is the number of the CA cells.

4 DAT ICAQ: TOOL DESCRIPTION

The DAT ICAQ is an automated CA design tool using QCAtechnology as an implementation medium. It can automati-cally create the QCA design layout of any binary 1–d CA.No manual designing or programming is required becausethe CA model is created and simulated using a user–friendlygraphical user interface (GUI). The proposed tool createsthe QCA design layout and simultaneously creates the QCAdesign simulation test vectors in order to make it easyfor the tool user to compare the results of the simulatedCA model to the results of the QCA design simulation.DAT ICAQ is a web–based application which has beenimplemented using the PHP programming language [73].The proposed tool is open source and platform independent.The tool can run on any web server and is not requiringthe installation of any application. DAT ICAQ can be usedvia any computer connected to the Internet.

The proposed tool produces automated QCA designs intwo steps as presented in Fig. 12. In the first step therequested CA model has to be defined and simulated inorder to confirm the model functionality. In the second




Fig. 11. Simulation results of the QCA circuit for a 10 CA cellmodel with periodic boundary conditions. Please notice thatall the init signals, here omitted intentionally for readabilityreasons, are found at ’0’ with the exception of init 2 which isfound at ’1’.

step the QCA design of CA’s model is automaticallyproduced and at the same time the test vectors for func-tional verification of the QCA design are produced. Morespecifically, in the first step the user must define the numberof cells which compose the CA model to be designed, theWol f ramRuleNumber [33] to be used for the CA evolutionand the type of boundary conditions of the CA model.Furthermore, the initial state of CA cells, the number ofevolution steps and the evolution period to be displayedmust also be defined to enable the tool to simulate anddisplay the simulation results of the requested CA model.By pressing Test CA button in the GUI, the simulationresults of the defined CA model are presented in the rightwindow of DAT ICAQ’s interface.

The simulation results are presented on a grid in which,the first row represents the initial state and the followingrows present the time evolution of the CA model. In thegrid presentation, value “0” corresponds to white colorcells, while value “1” corresponds to red color cells. Forreadability reasons, the initial state of the simulation ispresented in gray color.

The second step includes the main functionality of thetool which is the production of the automated QCA design.In order for the tool to produce the automated CA model’sQCA circuit design, the previously presented architecturehas been used.

The proposed tool can implement binary 1–d CA modelsusing any Wolfram rule which is inputted by the tool’s user

Step 1: CA

model’s parameters

definition and CA

functional

Step 2: QCA

Circuit and

Simulation Test Vectors

Outputs: a. The QCA design file in QCA Designer file format

b. The Simulation Test Vectors File in QCA Designer Simulator File Format

Fig. 12. Functionality block diagram of DATICAQ tool.

in the first step of design’s production. Because of this, CAcell block designs are implemented dynamically by a PHPfunction in order to produce adaptive CA cells using anyrequested rule. More specifically the designs of the differentCA cell blocks are described in text files using a specialformat presented below. Every QCA cell in the design islocated on one row in the text file. For every QCA cell,the following nine descriptors are used to describe theirproperties:

1) The horizontal position of the QCA cell from the leftedge of the design, in nanometers.

2) The vertical position of the QCA cell from the topedge of the design, in nanometers.

3) A number from 0 to 3 representing one of thefour clock zones clk0,clk1,clk2 or clk3, respectively,which controls the tunneling energy barriers of thecell.

4) The type of the QCA taking one of the followingvalues: QCAD CELL NORMAL for a normalcell, QCAD CELL INPUT for an input cell,QCAD CELL OUTPUT for an output cell,QCAD CELL FIXED for a cell with fixed value.

5) The polarization for the QCA cells with fixed values.The value of this descriptor can be 0, 1 or rule0 torule7. The value rule0 represents the least significantbit and the rule7 the most significant bit of therequested Wolfram’s rule byte.

6) A flag value of 1 or 0 indicates if the cell is rotatedby 45◦ or not.

7) A text value for the label of the QCA cell.




8) The horizontal position of the label.9) The vertical position of the label.The final QCA layout is presented in the right frame of

the tool’s interface and additionally three buttons appearon the top of the frame. By clicking on the first button, theQCA layout of the produced circuit can be downloadedin QCADesigner format [57]. With the second button,a stimuli file is produced containing a complete set ofsimulation vectors for the circuit, according to the initialCA state and the number of CA evolution step valuesthat have been given by the user in the first step of theDAT ICAQ operation. Concequently, the stimuli file com-plies with the requirements of the QCADesigner Simulator[57] in order to provide the user with an easy way tosimulate the produced circuit. By clicking on the thirdbutton appearing in the frame, the tool provides to the usera useful simulation instructions help window, in order totake advantage of the produced files without making anymistakes.

Finally, the realization of hybrid CA models [58] can besucceeded by creating a file which provides the mappingbetween CA cells and the corresponding rules. DAT ICAQreads the mapping information from the file and builds theappropriate QCA circuit.

Comparing CA implementations using QCA to CA im-plementations using conventional CMOS technology wecan be confident to say that QCA implementation exceedsCMOS implementation in terms of area and operationfrequency [59]. The QCA implementation can operate near1 THz against 0.35µm CMOS implementation which canoperate near 120 MHz. The area covers a CA implementa-tion using QCA is 0.68 to 0.73 and the area covers a CAimplementation using 0.35µm CMOS technology is near100µm [59]. Moreover, we have designed the analogous 1–d CA grid with rule 90 described in subsection 3.5.2 byusing 0.13µm CMOS technology and the area covered bythis CA implementation in the specific CMOS technologyis near 62µm while its clock frequency is less than 1GHz.The above superior results of CA design with QCA whencompared with CMOS technology can be also confirmedwith other CMOS CA implementations like the ones foundin [60], [61]. Even more recent CA implementations of thepast three years like a single CA crowd evacuation model inField Programmable Gate Array (FPGAs) [68] by using anAltera Stratix device of 0.13µm, or a dedicated FPGA CAprocessor for modeling wildfire by using Altera Stratix–Vof 40nm [69] or a massively parallel implementation fora floating–point–based CA in FPGA cluster [67] by usingXilinx Virtex–4 FPGAs does not provide any significantdifferences in terms of timing operation, while in areaconfiguration due to FPGA special purposes they alsocame short when compared to the above QCA designs. Ingeneral, regarding the benefits in terms of calculated powerdissipation for the molecular–scale QCA desing like the oneproposed in this paper, compared to existing and projectedtechnology, these can be found in [62]. There the powerdissipated per device versus propagation delay for QCA andits relation to complementary metal–oxide–semiconductor

CMOS technology are given analytically. The upper boundfor the QCA region is based on the worstcase scenariowherein every device performs a logically irreversiblefunction and thus switches nonadiabatically, dissipating anamount of energy of order Ek during a switching period.While comparisons between proposed devices and existingdevices should be made cautiously, these data indicatethat QCA may offer a way to achieve the ultralow powerdissipation required for molecular scales of integration.

5 CONCLUSIONS

In this paper a logic design methodology resulting to anew QCA design architecture and the corresponding designtool, are presented that can produce the QCA layout forany 1-d CA model. The example QCA layouts and thesimulation results have been provided in terms of metalor semiconductor implementation logic. According to veryrecent work [74], this implementation logic seems to befabricable at approximately 2×2nm QCA cell dimensionsusing Silicon Atomic Quantum Dots and can operate atroom temperature. In spite of that, the basic principlesof the proposed methodology are compatible and can beeasily applied on molecular or magnetic implementations,since the 2-d wave clocking scheme [16] that the proposedmethodology uses, can be applied to these implementations.Most recently QCA research is focusing on molecular [75],[76] and magnetic implementations [77], [78]; as a result,in future work the presented methodology can be altered inorder to produce designs based on new clocking schemesthat have been proposed for molecular or magnetic imple-mentations [79], [80], [81], [82]. The proposed architectureand the presented tool, named DAT ICAQ [73], offer thepower of automated modelling and QCA implementation ofCAs, while the latter is an interactive web–based tool hidingarchitecture and programming issues from the user. It canmodel dynamic complex phenomena and produce automati-cally the QCA layouts in QCADesigner format. The inputsto the presented architecture are the CA dimensionality,size, local rule, and the initial and boundary conditionsimposed by the particular problem. Due to the friendlyinterface of the proposed systems no prior knowledge ofQCA designing is required by the user. Research workerswith different scientific backgrounds that use CAs and haveno specific knowledge of either software programming orQCA designing are able to use DAT ICAQ. Furthermore,the proposed system helps the user to easily test severalCAs and decide which one is appropriate for the problemin hand. Having in mind that 1–d CA and 2–d CA havebeen proven equally really efficient for VLSI design [83],[58], [59], [60], [61], [67], [68], [69], in our future work,research will be focused on finding possible extensionsof the proposed architecture in order to produce 1–d CAmodels with larger neighborhoods as well as to introduceCA implementations in larger dimensions, i.e. in 2–d and3–d CA models, enabling the depiction of several CAapplications in modern nano–architectures.




REFERENCES

[1] International Technology Roadmap for Semiconductors (ITRS),http://www.itrs.net, 2007.

[2] C. Wasshuber, “About single electron devices and circuits,” Ph.D.dissertation, Faculty of Elect. Eng. and Inf. Technol., Tech. Univ. ofWien, Wien, Germany, 1997.

[3] T. Oya, Y. Takahashi, M. Ikebe, T. Asai, and Y. Amemiya, “Asingle–electro n circuit as a discrete dynamical system,” Superlatti.Microstruct., vol. 34, pp. 253–258, 2003.

[4] I. G. Karafyllidis, “Design and simulation of a single–electronrandom–access memory array,” IEEE Transactions on Circuits andSystems I, vol. 49, pp. 1370–1375, 2002.

[5] J. M. Wang, “Simulation and design of nanocircuits with resonanttunnelling devices,” IEEE Trans. Circuits Syst. I. Reg. Papers, vol.54, no.6, pp. 1293–1304, Jun. 2007.

[6] G. Zardalidis and I. G. Karafyllidis, “SECS: A New Single–Electron–Circuit Simulator,” IEEE Trans. Circuits Syst. I. Reg.Papers, vol. 55, no.9, pp. 2774–2784, Oct. 2008.

[7] J. Hoekstrag, “On circuit theories for single–electron tunnelingdevices,” IEEE Trans. Circuits Syst. I. Reg. Papers, vol. 54, no. 11,pp. 2353–2359, Nov. 2007.

[8] C. Lent, B. Isaksen, and M. Lieberman, “Molecular quantum–dotcellular automata,” J. Amer. Chem. Soc., vol. 125, pp. 1056–1063,2003.

[9] Y. Lu, and C. S. Lent, “Theoretical Study of Molecular QuantumDot Cellular Automata,” J. of Computational Electronics, vol. 4, no.1/2, pp. 115–118, 2005.

[10] C. S. Lent, P. D. Tougaw, W. Porod, and G.H. Bernstein, “QuantumCellular Automata,” Nanotechnology, vol. 4, no. 1 pp. 49–57, Jan.1993.

[11] C. S. Lent, P. D.Tougaw. “Lines of interacting quantum–dot–cells: abinary wire,” Journal of Applied Physics, vol 74, no. 10, pp. 6227–6233, 1993.

[12] P. D. Tougaw and C. S. Lent, “Logical devices implemented usingquantum cellular automata,” Journal of Applied Physics, vol. 75, no.3, pp. 1818–1825, 1994.

[13] W. Wang, K. Walus, and G. A. Jullien, “Quantum–dot cellularautomata adders,” in Proc. IEEE International Conference on Nan-otechnology IEEE–NANO, Los Angeles, California, U.S.A., 2003,vol. 2, pp. 461–464.

[14] K. Kim, K. Wu, and R. Karri, “The robust QCA adder designsusing composable QCA building blocks,” IEEE Transactions onComputer–aided Design of Integrated Circuits and Systems, vol. 26,no. 1, pp. 176–183, 2007.

[15] H. Cho and E. E. Swartzlander, “Adder and Multiplier Design inQuantum–Dot Cellular Automata,” IEEE Transactions on Comput-ers, vol. 58, no. 6, pp. 721–727, June 2009.

[16] V. Vankamamidi, M. Ottavi, and F. Lombardi, “Two–DimensionalSchemes for Clocking/Timing of QCA Circuits,”, IEEE Trans.Comput. Aided Design Integr. Circuits Syst., vol. 27, no. 1, pp. 34–44, Jan. 2008.

[17] V. A. Mardiris and I. G. Karafyllidis, “Design and simulation ofmodular 2n to 1 quantum–dot cellular automata (QCA) multiplex-ers,” Int. J. Circ. Theor. Appl. [online], Apr. 2009.

[18] V. A. Mardiris and I. G. Karafyllidis, “Design and Simulation ofModular Quantum–Dot Cellular Automata Multiplexers for MemoryAccessing,” Journal of Circuits, Systems, and Computers, vol. 19,no. 10, pp. 349–365, 2010.

[19] J. Huang, M. Momenzadeh, and F. Lombardi, ”Analysis of missingand additional cell defects in sequential quantum–dot cellular au-tomata,” Integration, the VLSI Journal, vol.40, pp. 503–515, 2007.

[20] A. S. Shamsabadi, B. S. Ghahfarokhi, K. Zamanifar, and N. Mova-hedinia, “Applying inherent capabilities of quantum–dot cellularautomata to design: D flip–flop case study,” Journal of SystemsArchitecture, vol. 55, no. 3, pp. 180–187, Mar. 2009.

[21] M. T. Niemier, M. J. Kontz, and P. M. Kogge, “A design of anddesign tools for a novel quantum dot based microprocessor,” inProc. 37th Design Automation Conference, Los Angeles, California,U.S.A., 2000, pp. 227–232.

[22] V. Vankamamidi, M. Ottavi, and F. Lombardi, “A serial memoryby quantum–dot cellular automata (QCA),” IEEE Transactions onComputers, vol. 57, no. 8, pp. 606–618, 2008.

[23] B. Taskin and Bo Hong; “Improving Line–Based QCA Memory CellDesign Through Dual Phase Clocking,”, IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems, vol. 16, no. 12, pp. 1648–1656, Dec. 2008.

[24] M. Bubna, S. Mazumdar, S. Roy, and R. Mall, “Designing CellularAutomata Structures using Quantum-dot Cellular Automata,” in14th annual IEEE International Conference on High PerformanceComputing (HiPC 2007), Goa, India, Dec. 2007.

[25] T. T. Teodosio, “Quantica: arquitecturas e simulacao de operacaode dispositivos,” M.Sc. thesis, Electrical and Computer Engineering,Technical University of Lisbon, Sept 2007.

[26] R. Singhal, Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA), ProQuest, UMI Dissertation Publish-ing, 2012.

[27] A. Orlov, R. Kummamuru, R. Ramasubramaniam, C. Lent, G.Bernstein, and G. Snider, “Clocked quantum–dot cellular automatashift register,” Surf. Sci., vol. 532, pp. 1193–1198, 2003.

[28] Y. Lu, M. Liu, and C. Lent, “Molecular quantum–dot cellularautomata: From molecular structure to circuit dynamics,” J. Appl.Phys., vol. 102, no. 3, pp. 034311–1–034311–7, 2007.

[29] J. Jiao, G. Long, L. Rebbouh, F. Grandjean, A. Beatty, and T.Fehlner, “Properties of a mixed–valence (Fe II)2(Fe III)2 squarecell for utilization in the quantum cellular automata paradigm formolecular electronics,” J. Amer. Chem. Soc., vol. 127, no. 50, pp.17819–17831, 2005.

[30] M. Baseer Haider, J. L. Pitters, G. A. DiLabio, L. Livadaru, J. Y. Mu-tus, and R. A. Wolkow, “Controlled Coupling and Occupation of Sil-icon Atomic Quantum Dots at Room Temperature,” Phys.Rev.Lett.,vol. 102, pp. 46805–46808, 2009.

[31] J. Von Neumann, Theory of Self–reproducing Automata, Universityof Illinois Press, Urbana, 1966.

[32] R. P. Feynman, “Simulating physics with computers,” Int. J. ofTheoretical Physics, vol. 21, no. 6/7, pp. 467–488, 1982.

[33] S. Wolfram, “Theory and Applications of Cellular Automata,” WorldScientific, Singapore, 1986.

[34] T. Tofolli, “Cellular Automata as an Alternative to (rather thanan approximation of) Differential Equations in Modelling Physics,”Physica, vol. 10d, pp. 117–127, 1984.

[35] G. Ch. Sirakoulis, I. Karafyllidis, A. Thanailakis, and V. Mardiris,“A methodology for VLSI implementation of Cellular Automataalgorithms using VHDL,” Advances in Engineering Software, vol.32, pp. 189–202, 2001.

[36] G. Ch. Sirakoulis, I. Karafyllidis, and A. Thanailakis, “A CADsystem for the construction and VLSI implementation of CellularAutomata algorithms using VHDL,” Microprocessors and Microsys-tems, vol. 27, no. 8, pp. 381–396, 2003.

[37] V. A. Mardiris, I. G. Karafyllidis, “Universal cellular automaton cellusing quantum cellular automata,” Electronics Letters, vol.45, no.12,pp. 607–609, June 2009

[38] I. Karafyllidis, “Design of a dedicated parallel processor for theprediction of forest fire spreading using cellular automata and ge-netic algorithms,” Engineering Applications of Artificial Intelligence,vol.17, no.1, pp.19–36, 2004.

[39] G. Ch. Sirakoulis, I. Karafyllidis, and A. Thanailakis, “A cellularautomaton methodology for the simulation of integrated circuitfabrication processes,” Future Generation Computer Systems, vol.18, no. 5, pp. 639–657, 2002.

[40] N. Margolus, T. Toffoli, and G. Vichniac, “Cellular AutomataSupercomputers for Fluid Dynamics Modeling,” Phys. Rev. Letters,1986.

[41] M. Arbib, “Simple Self–Reproducing Universal Automata,” Infor-mation and Control, vol. 9, pp.177, 1966.

[42] C. Mizas, G. Ch. Sirakoulis, V. Mardiris, I. Karafyllidis, N. Glykos,and R. Sandaltzopoulos, “Reconstruction of DNA sequences usinggenetic algorithms and cellular automata: Towards mutation predic-tion?,” BioSystems, vol. 92, no. 1, pp. 61–68, 2008.

[43] K. Preston, M. J. Duff, S. Levialdi, P. E. Norgren, and J. I. Toriwaki,“Basics of Cellular Logic with Some Applications in Medical ImageProcessing,” Proc. IEEE, IEEE Press, Piscataway, N.J., pp.67, 1979.

[44] L. Nalpantidis, A. Amanatiadis, G. Ch. Sirakoulis, and A. Gaster-atos, “An Efficient Hierarchical Matching Algorithm for ProcessingUncalibrated Stereo Vision Images and its Hardware Architecture,”accepted for publication in IET Image Processing.

[45] A. R. Smith(III), “Real–Time Language Recognition by One–Dimentional Cellular Automata,” J. Computing and Sys. Sciences,vol. 6, pp. 233–253, 1972.

[46] O. H. Ibarra, M. A. Palis, and S. M. Kim, “Fast Parallel LanguageRecognition by Cellular Automata,” Theoretical Computer Science,vol. 41, pp. 231–246, 1985.

[47] W. D. Hillis, ’The Connection Machine: A Computer ArchitectureBased on Cellular Automata,” Physica D, vol. 10, pp. 213–238, 1984.




[48] S. Willson, “Computing Fractal Dimensions for Additive CellularAutomata,” Physica D, vol. 24, pp. 190–206, 1987.

[49] S. Takahashi, “Cellular Automata and Multi Fractals: DimensionsSpectra of Linear Cellular Automata,” Physica D, vol. 45, pp. 36–48, 1990.

[50] S. A. Chatzichristofis, D. A. Mitzias, G. Ch. Sirakoulis, and Y. S.Boutalis, ”A Novel Cellular Automata Based Technique for visualmultimedia content encryption,” Optics Communications, vol. 283,no. 21, pp. 4250–4260, Nov. 2010.

[51] V. Mardiris, G. Ch. Sirakoulis, C. Mizas, I. Karafyllidis, and A.Thanailakis, “A CAD System for Modeling and Simulation ofComputer Networks Using Cellular Automata,” IEEE Transactionson Systems, Man, and Cybernetics Part C, vol. 38, no. 2, pp. 253–264, March 2008.

[52] B. Chopard and M. Droz, Cellular Automata Modelling of PhysicalSystems. Cambridge, U.K.: Cambridge Univ. Press, 1998.

[53] A. Adamatzky, Identification of Cellular Automata, Taylor & FrancisGroup, 1994.

[54] I. Amlani, A. O. Orlov, G. H. Bernstein, C. S. Lent, and G. L.Snider, “Realization of a Functional Cell for Quantum–Dot CellularAutomata,” Science, vol. 227, no. 5328, pp. 928–930, 1997.

[55] S. Bhanja, and S. Sarkar, “Thermal Switching Error Versus DelayTradeoffs in Clocked QCA Circuits,” IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems, vol. 16, no. 5, pp. 528–541,2008.

[56] K. Kim, K. Wu, and R. Karri, “Towards designing robust QCAarchitectures in the presence of sneak noise paths,” in Proc. Design,Automation and Test in Europe, Messe Munich, Germany, Mar. 7–11, pp. 1214–1219, 2005.

[57] K. Walus, T. J. Dysart, G. A. Jullien, and A. R. Budiman, “QCADe-signer: A Rapid Design and Simulation Tool for Quantum–DotCellular Automata,” IEEE Transactions on Nanotechnology, vol. 3,no. 1, pp. 26–31, 2004.

[58] I. Karafyllidis, I. Andreadis, Ph. Tsalides, and A. Thanailakis “Non–linear hybrid cellular automata as pseudorandom pattern generatorsfor VLSI systems,” VLSI Design, vol. 7, pp. 177–189, 1998.

[59] R. J. Chen, and J. L. Lai, “VLSI implementation of the universal2–D CAT/ICAT system,” in Electronics, Circuits and Systems, 2004.ICECS 2004. Proceedings of the 2004 11th IEEE InternationalConference on, pp. 187– 190, 13–15 Dec. 2004.

[60] R. J. Chen, Y. T. Lai, and J. L. Lai, “Architecture design of there–configurable 2–D von Neumann cellular automata for image en-cryption application,” in Proceedings of the International Symposiumon Circuits and Systems ISCAS 2005, Kobe, Japan, pp. 3059–3062,2005.

[61] R. J. Chen, Y. T. Lai, and J. L. Lai, “Architecture design andVLSI hardware implementation of image encryption/decryption sys-tem using re–configurable 2D Von Neumann cellular automata,” inProceedings of the International Symposium on Circuits and SystemsISCAS 2006, Island of Kos, Greece, 2006.

[62] J. Timler and C. S. Lent, “Power gain and dissipation in quantum–dot cellular automata,” Journal of Applied Physics, vol. 91, no. 2,pp. 823–831, 2002.

[63] M. T. Niemier and P. M. Kogge, “Problems in Designing withQCAs: Layout=Timing,” International Journal of Circuit Theory andApplications, vol. 29, no. 1, pp. 49–62, 2001.

[64] K. Kim, K. Wu, R. Karri, “Towards Designing Robust QCA Archi-tectures in the Presence of Sneak Noise Paths,” in Proceedings ofDesign, Automation and Test in Europe (DATE), pp.1214–1219 vol.2, 7–11 March 2005.

[65] S. Wolfram, “A New Kind of Science,” Champaign, IL: WolframMedia, 2002.

[66] A. Adamatzky (Ed.). “Collision Based Computing,” Springer–Verlag,pp. 397–514, 2001.

[67] S. Murtaza, A. G. Hoekstra, P. M. A. Sloot, “Cellular AutomataSimulations on a FPGA cluster,” International Journal of HighPerformance Computing Applications, vol. 25, no. 2, pp. 193–204,May 2011.

[68] I. G. Georgoudas, P. Kyriakos, G. Ch. Sirakoulis, and I. Andreadis,“An FPGA Implemented Cellular Automaton Crowd EvacuationModel Inspired by the Electrostatic–Induced Potential Fields,” Mi-croprocessors and Microsystems, vol. 34, pp. 285–300, 2010.

[69] P. Progias, G. Ch. Sirakoulis, “An FPGA processor for modellingwildfire spreading,” Mathematical and Computer Modelling, vol. 57pp. 1436–1452, 2013.

[70] R. Zhang, P. Gupta, L. Zhong, N. K. Jha, “Threshold networksynthesis and optimization and its application to nanotechnologies”IEEE Trans. on CAD, vol. 24, no. 1, pp. 107-118, 2005.

[71] H. Cho and E. Swartzlander, “Adder designs and analyses for quan-tumdot cellular automata,” IEEE Transactions on Nanotechnology,vol. 6, no. 3, pp. 374–383, 2007.

[72] H. Cho, and E. Swartzlander, “Serial Parallel Multiplier Design inQuantum-dot Cellular Automata,” in Proceedings of the 18th IEEESymposium on Computer Arithmetic (ARITH’07), pp. 7–15, 2007.

[73] DATICAQ: http://infoman.teikav.edu.gr/daticaq[74] R. A. Wolkow, L. Livadaru, J. Pitters, M. Taucer, P. Piva, M. Sa-

lomons, M. Cloutier and Bruno V.C. Martins, “Silicon Atomic Quan-tum Dots Enable Beyond-CMOS Electronics,” in Field-CoupledNanocomputing Paradigms, Progress, and Perspectives, Neal G.Anderson, SanjuktaBhanja (Eds.), Springer, 2014.

[75] A. Chaudhary , D. Z. Chen , X. S. Hu and M. T. Niemer, “Fabricat-able interconnect and molecular QCA circuits,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 26, no. 11, pp.1977–1991,Nov. 2007.

[76] A. Pulimeno, M. Graziano, A. Sanginario, V. Cauda, D. Demarchi,and G. Piccinini, “Bis-ferrocene molecular QCA wire: Ab initiosimulations of fabrication driven fault tolerance,” IEEE Trans. Nan-otechnol., vol. 12, no. 4, pp. 498–507, Jul. 2013.

[77] A. Orlov, A. Imre, G. Csaba, L. Ji, W. Porod, and G. H. Bernstein,“Magnetic Quantum-Dot Cellular Automata: Recent Developmentsand Prospects,” Journal of Nanoelectronics and Optoelectronics,vol.3, pp. 1–14, 2008.

[78] M. Crocker, M. Niemier, and X.S. Hu, “A Reconfigurable PLAArchitecture for Nanomagnet Logic,” ACM Journal on EmergingTechnologies in Computing Systems, vol. 8, no. 1, February 2012.

[79] F. Karim, K. Walus, and A. Ivanov, “Analysis of field-driven clockingfor molecular quantum-dot cellular automata,” J. Comput. Elect., vol.9, pp. 16–30, 2010.

[80] K. Hennessy and C. S. Lent, “Clocking of molecular quantum-dotcellular automata,” J. Vac. Sci. Technol. B, vol. 19, no. 5, pp. 1752–1755, 2001.

[81] C. S. Lent and B. Isaksen, “Clocked Molecular Quantum-dot CellularAutomata,” IEEE Trans. On Electron Devices, vol. 50, pp. 1890,2003.

[82] M. Graziano, M. Vacca, A. Chiolerio and M. Zamboni, “A NCL-HDL Snake-Clock Based Magnetic QCA Architecture,” IEEE Trans.Nanotechnology, vol. 10, no. 5, pp. 1141–1149, Sept. 2011.

[83] P. P. Chaudhuri, D. R. Chowdhury, S. Nandi and S. Chattopadhyay,Additive Cellular Automata: Theory and Applications, Volume 1,Wiley-IEEE Computer Society Press, 1997.

automated design architecture for 1-d cellular automata using quantum cellular automata

Documents