author : fabrice bernard-granger september 18th, … · mtj resistive states ... semiconductor...

Author : Fabrice BERNARD-GRANGER

September 18th, 2014

Fabrice BERNARD-GRANGER

September, 18th 2014 Keysight Semiconductor Devices Characterisation Seminar 2

Spintronic Introduction

Spintronic Design Flow and Compact Modelling

Process Variation and Design Impact



Electronic Spintronic

information is conveyed using electron charge (e-) . Generation, manipulation, detection of charge currents: flow of electrons The most used material is semiconductor (Si)

information is conveyed through electron spin (e↓ or e↑). Generation, manipulation, detection of spin currents: flow of magnetic moments. The material of choice is ferromagnetic alloy (Fe, Co, Mg)

M magnetization vector of a ferromagnetic layer

50% e↑

50% e↓ electron

flux

with X << Y

Electron flux

spin polarized

Albert Fert, French physicist, was awarded the 2007 Nobel Prize

Magneto resistance

effect in multi

layer stack

Spin polarized current

Electron spin

Current I

Y% e↑

X% e↓



A Magnetic Tunnel Junction

is the basic device used for storing information in a MRAM

Free layer

Reference Layer

r low resistance R large resistance

R r

AP state = 1 P state = 0

Oxide layer

MTJ stack

Free layer magnetization dynamic

during writing process

MTJ resistive states

M magnetization vector of a ferromagnetic layer



Use electron spin added

to its electric charge

Standalone MRAM,

TMR (early 00’s)

HDD, GMR

(early 80’s)

Embedded MRAM &

Distribute non-volatility

within logic

(development)

Field Induce

Magnetic Switching

(FIMS, Toggle)

Thermally

Assisted Switching

(TAS)

Spin Torque

Transfer

(STT)

Spin-Based

Logic ?

…Spin Orbit

Torque

(SOT)



MRAM an emergent and credible candidate for SRAM and flash replacement



Q3, 2014

Altera has taken the lead in enabling ST-MRAM within memory and storage markets supported by high performance, low power FPGAs

20 Japanese & US Cies joined their efforts on MRAM development Q4, 2013



XMC a Chineese foundry, plan to developp MRAM process in 2015 http://www.xmcwh.com/technology/process-technology/

Q1, 2014

Q3, 2014

The mobile chip giant Qualcomm has also been working on STT-MRAM, and in a recent test of TDK-Headway’s chips, it found no errors in data retention after 528 hours at 150 °C.

http://www.xmcwh.com/technology/process-technology/







Spintronic Design Flow and

Compact Modelling




Schematic

design entry

Simulations

Layout

entry

DRC/LVS/xRC

Runset

Tape out

IP flow

Monte Carlo simulation

Dynamic Cell Switching

Static cell hysteresis

Circuit simulation

*SPITT = Spintec sPIn Torque Transfert

ANALOG flow

DIGITAL flow



SPITT*

core

Extraction/fit module (in progress with LETI) Dedicated fitting algorithm

ICCAP tool plugin

Physics

TCAD

SPICE model SPITT

(Spintec sPIn Torque Transfert)

Modes (accuracy vs. speed)

Physical phenomenon

SPICE

simulator

STTRAM

Raw data Model card

parameters

corners and statistic



State - V I-V R-V

SPITT Model

Merits figures





Process Variation and Design

Impact



5 corners set to catch process variation in a MTJ based on

the following parameters:

• RA (sheet resistance) [Ω.um²] (+/- 3 σ*)

• TMR (Tunneling Mangeto Resistance = ∆R/R) [%] (+/- 3 σ*)

• ISW (Switching Current) [uA] (+/- 3 σ*)

SWITCHING CURRENT

RESISTANCE

* σ = Gaussian distribution width



Reduction to speed up the development phase

3 T

25 P 3 V

Full MRAM = MRAM Cell + all CMOS logic / analogic

MRAM Cell = MTJ + Nmos transistor

# MRAM Process corners = 25

= 5 MTJ corners * 5 MOS corners

P

V

T

# MRAM Voltage corners = 3

Vdd –x%, Vdd, Vdd +x%

# MRAM Temprature corners = 3

Tmin, 27°C, Tmax

225 corners



5 functionals architectures @ nominal conditions

225 corners

around 10 times less

Electrical simulations across all PVT

σMTJ large σMTJ small

Design functionality loss due to inaccurate MTJ characterization



Logic

Arithmetic Logic Unit Standard cell library (latch, flip flop, register..) Nano processor (based on spintronics cells)

FPGA

Look Up Table (silicon proven)

Memory, IC Design

Test chip circuit (test device oriented) STT-RAM Full 256kb, 1 Mb and 4Mb single port compiler oriented (design on going) 8x8b SOT-RAM + peripheries (tape out ongoing)

Standard Cell

Circuit

Memory

• Fabless

• Design analog-numeric-system

• Control processors data centric



Spintronic technology

Non volatility key for power reduction

Ready for MRAM production

New technology = new flow to set-up

Silicon characterization

PDK and Full Design plateform developement

Spintronic impact @ system level

Architecture tremendously modified

New functionality arising

www.spintec.fr

http://www.spintec.fr/

author : fabrice bernard-granger september 18th, … · mtj resistive states ... semiconductor...

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