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IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 9, SEPTEMBER 2008 Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors. Assaf Shacham , Member, IEEE, Keren Bergman, Senior Member, IEEE, and Luca P. Carloni, Member, IEEE - PowerPoint PPT Presentation


A Multi-Standard Mobile Digital Video Receiver in 0.18um CMOS process


IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 9, SEPTEMBER 2008Photonic Networks-on-Chip for FutureGenerations of Chip MultiprocessorsAssaf Shacham, Member, IEEE, Keren Bergman, Senior Member, IEEE, andLuca P. Carloni, Member, IEEE

A. Shacham is with Aprius Inc., 440 N. Wolfe Rd., Sunnyvale, CA 94085. E-mail: Bergman is with the Department of Electrical Engineering, Columbia University, 500 W. 120th St., 1300 Mudd, New York, NY 10027. E-mail: Carloni is with the Department of Computer Science, Columbia University, 466 Computer Science Building, 1214 Amsterdam Avenue, Mail Code: 0401, New York, NY 10027-7003. E-mail:

2011. 06. 08.Kim Yeo-myung








RFAD LAB, YONSEI UniversityINTRODUCTIONParallel Computational CoreNew commercial release for driving performanceThe role of interconnect and associated global communication infrastructure is becoming central to the chip performance

Issue of Network-on-Chip(NoC)Large Bandwidth & stringent latency requirementsElectrical NoC can provide enough performance but required large power consumption Photonic NoC

Photonic NoCs can deliver a dramatic reduction in power expended on intrachip global communi-cations while satisfying the high bandwidths requirements of CMPs

Hibryd NoC Architecture Photonic + Electronic

RFAD LAB, YONSEI UniversityPhotonic elements have recently become available as library cells in standard CMOS processes.As a result of low loss optical waveguides, once a photonic path is established, the data is transmitted end-toend without the need for repeating, regenerating, or buffering.The power consumption of optical switching elements, conversely, is independent of the bit rate, so, once generated, high-bandwidth messages do not consume additional dynamic power when routedwepropose a hybridNoC microarchitecture that combines a photonic circuit-switched network with an electronic packet-switched network.

Silicon photonic photonic CMOS .Low-loss wave guide repeating, regenerating, buffering .Data rate electrical NoC switching, regenerating dynamic power optical power bit-rate bandwidth Off-chip communication .Hybrid NoC microarchitecture (photonic circuit switched network + electronic packet-switched network)

: CMOS 3~4 additional layer through silicon via POINTs -> Simulator (to quantitatively evaluate critical design aspects such as deadlock avoidance/recovery, optimal message size, path multiplicity (PM), and alternative flow control mechanisms)3RELATED WORKRelative performance of optical and electrical on-chip interconnects The penetration of on-chip optical interconnects can be envisioned in lengths larger than 1,000 times the wavelength where they can have lower power and latency than electronic interconnects

Multicore processor architecture where remote memory accesses are implemented as transactions on a global on-chip optical bus A latency reduction as high as 50 percent for some applications and a power reduction of about 30 percent over a baseline electrical busRFAD LAB, YONSEI UniversityOptical communication is widely accepted as an interconnection medium for long and medium-reach distances, typically above 10 m.A large body of research work exists on the design, fabrication, and performance analysis of optical interconnects for short-reach applications such as chip-to-chip interconnection.

Optical 10m chip to chip short range intra chip . power .

4RELATED WORKAn optical NoC based on a wavelength-routed crossbar The crossbar, comprised of passive resonator devices and routing between an input-output pair, is achieved by selecting the appropriate wavelengthProblem : requires either widely tunable laser sources or large arrays of fixed-wavelength sources with fast wavelength-selection switches

Benefits of optical intrachip interconnectsWhile optical clock distribution networks are not especially attractive, wavelength division multiplexing (WDM) does offer interesting advantages for intrachip optical interconnects over copper in deep-submicron processes.RFAD LAB, YONSEI University5HYBRID NOC MICROARCHITECTUREMeaning of HybridOptical + ElectronicCircuit-switched network(bulk message) + packet-switched network(short message)

Why Hybrid?Photonic packet switching? Two necessary functions for packet switching, namely, buffering and header processing, are very difficult to implement with optical devicesElectronic NoC Problem? Electronic NoCs do have many advantages in flexibility and abundant functionality, but tend to consume high power, which scales up with the transmitted bandwidthRFAD LAB, YONSEI University6HYBRID NOC MICROARCHITECTUREOperation of optical circuit switchingElectronic control packet is transmitted routed in the electronic network & setting up a photonic pathBuffering takes place for the electronic packets during the path-setup phaseThe established paths are optical circuits between processing cores enabling low power, low latency, high BW.

Advantage of photonic pathBit-rate transparency : (bit-rate) Dynamic power dissipation scales with the bit rate in electronics(switching power). But photonic switches switch on and off once per message and their energy dissipation does not depend on the bit rateLow loss in optical wave guides

RFAD LAB, YONSEI University7HYBRID NOC MICROARCHITECTUREExploiting Photonics in NoC Design


Optical SwitchModulatorWaveguide & FiberCoupling lensThe construction of the photonic NoC in a single layer, above the metal* Torus Networks* Off-Chip Laser* Optical Clock Distribution Network* WDM(Microring-resonator structure)The proposed NoC is comprised of broadband 2 X 2 photonic switching elements (PSEs) interconnected by optical waveguides.The network gateways also include some circuitry for clock synchronization and recovery and serialization/deserialization.When traditional approaches are used, this circuitry can be expensive both in terms of power and of latency.An example of such an opportunity is an optical clock distribution network which can provide a high quality low-power clock to the entire chip, simplifying the clock recovery in the gateways.8HYBRID NOC MICROARCHITECTURELife of a Message in the Photonic NoCA write operation that takes place from a processing unit in a core to a memory that is located in another core is start.As soon as the write address is known a path-setup packet is sent on the electronic control network.The control packet is routed in the electronic network, reserving the photonic switches along the path for the photonic message which will follow it.When the path-setup packet reaches the destination port, the photonic path is reserved and is ready to route the message.A short light pulse can then be transmitted onto the waveguide in the opposite direction (from the destination to the source), signaling to the source that the path is open.After the message transmission is completed, a path teardown packet is sent to free the path resources for usage by other messages.RFAD LAB, YONSEI UniversityProcess core Memory core Address Electronic control network path setup packet Photonic switch Memory Path-setup packet photonic Memory process light pulse path packet

9NETWORK DESIGN(Building Blocks)Photonic Switching Element(PSE)

Microring-resonator structure(similar device : optically pumped)OFF state: The resonant frequency of the rings is different from the wavelengthON state: The switch is turned on by the injection of electrical current into p-n contacts surrounding the ringsSwitching time : 30 psTheir merit lies mainly in their extremely small footprint, with ring diameters of approximately 12um, and their low power


Their merit lies mainly in their extremely small footprint, with ring diameters of approximately 12 m, and their low power consumption of less than 0.5 mW of DC power when ON and approximately 1 pJ for modulating narrowband single-wavelength signals. For switching multiwavelength broadband signals, the ring resonators are designed as comb-pass filters with somewhat larger footprints, consuming 10 mW when ON [15], [18]. When the switches are OFF, they act as passive devices consuming nearly no power. Ring-resonator-based switches exhibit good crosstalk properties (> 20 dB), and a low insertion loss,approximately 1.5 dB [38]. 10NETWORK DESIGN(Building Blocks)Photonic Switching Element(PSE)

4 X 4 switches (controlled by electronic circuit termed an ER)Control packets are received in the ER, processed, and sent to their next hop, while the PSEs are switched ON and OFF accordinglyBlocking Relation is exist. (Nonblocking switches offer improved performance and simplify network management and routing.)RFAD LAB, YONSEI University

11NETWORK DESIGN(Topology)4 X 4 folded torus networkThe communication requirements of a CMP are best served by a 2D regular topology such as a mesh or a torus

A regular 2D topology requires 5 X 5 switches which are overly complex to implement using photonic technology.Therefore use a folded-torus topology as a base and augment it with access points for the gateways.RFAD LAB, YONSEI University

12NETWORK DESIGN(Topology)4 X 4 folded torus network

The access points for the gateways are designed with two goals in mind: 1) to facilitate injection and ejection without interference with the through traffic

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