arm architecture basics.pdf

8/13/2019 ARM Architecture Basics.pdf

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CENE FO DEELOMEN OF ADANCED COMING

AM A B


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IBM

M

Motorola

Panasonic

Qualcomm Sharp

Sanyo

Sun Microsystems

Sony

Symbian

Texas Instruments

Toshiba Wipro

.And many more


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AM A

Apple iPod Nano Ford Sync In-Car Comm &

Entertainment System

Nokia N93 Sony Playstation 3 (60GB)


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AM


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AM A


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IC D

IC

A .I IC

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AM D

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AM D

AM IC A I

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HMB

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AM F


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AM

Incrementer

Address Register

ALU

Barrel Shifter

MAC

Register Filer0 r15

Sign Extend

InstructionDecoder

Read

Data

A B Acc

Rd

ResultBA

r15

pc

Rn Rm

N

Address


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AM L A

G

37 , 32

17 18 16

2


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M

0 12 G

13 ()

14 L ()

15 C () C C

R0R1

R2

R6

R3

R5

R4

R7

R8

R9R10

R11

R14

R13R12

R15

CPSR

SPSR


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C

N Z C V I F T Mode

31 30 29 28 7 6 5 4 0

Condition Flags Processor ModeInterruptMasks

Thumb State

Function

Bit

FieldsFlags Status Extension Control

AM


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M

D

& NA

F I

I

Privileged

Nonprivileged


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B

B

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B 16

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C

r0

r1

r2

r3

r4

r5

r6

r7

r8r9

r10

r11

r12

r13 sp

r14 lrr15 pc

cpsr

-

User Mode

r13_irq

r14_irq

spsr_irq

InterruptRequest

Mode

This change causes user

register r13 and r14 tobe banked

The user registers are

replaced with registersr13_irq and r14_irq

spsr stores the previous

mode cpsr


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M

: 4:0

A 10111

F I 10001

I 10010

10011

11111 11011

10000

cpsr is not copied into the spsrwhen a modechange is forced due to a program writingdirectly to the cpsr.


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O M

M C4:0

10000

FI 10001

I 10010

M 10011A 10111

I 11011

11111


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M

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I

AM

J

The Jazelle instruction set is a closed instruction set and isnot openly available.

To take advantage of Jazelle extra software has to belicensed from both ARM Limited and Sun Microsystems.


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( 1)

I 32 16

C I 58 30

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C


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C

0 0 1 0 0 1 0 10011

31 30 29 28 7 6 5 4 0

nzCvq svci F tFunction

Bit

FieldsFlags Status Extension Control

0

24

0

27

j

cpsr = nzCvqjiFt_SVC


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I IC

AM7


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AM7

F

D

E

Fetch Decode Execute


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ADD

SUB ADD

CMP SUB ADD


Cycle 1

Cycle 2

Cycle 3

Time

F A

AM9 F


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AM9 F

Fetch Decode Execute Memory Write

H

L

I 13% 5

1.1 D MI MH

AM9 F


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AM9 F

F

D

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M (B/D)

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AM10


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AM10

Fetch Decode Execute Memory WriteIssue

I 34% 6

1.3 D MI MH

C AM7 AM9 AM10

AM I


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AM I

MSR

ADD

AND

SUB

MSR

ADD

AND

MSR

ADD

cpsrIFt_SVC

cpsrIFt_SVC

cpsriFt_SVC


Cycle 1

Cycle 2

Cycle 3

Time

Cycle 4

C


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C

A

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AM E


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AM E

AM I, , C,

Exceptions

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,

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,

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A

/

EE 000000000 00000

I NDEF 000000004 00004

I I 000000008 00008

A AB 00000000C 0000C

D A DAB 0000000010 00010

0000000014 00014

I I 0000000018 00018

F I FI 000000001C 0001C

E , I,


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DescriptionParts Bits Architecture

Mode 4:0 all processor mode

T 5 ARMv4T Thumb stateI & F 7:6 all interrupt masksJ 24 ARMv5TEJ Jazelle stateQ 27 ARMv5TE condition flag

V 28 all condition flagC 29 all condition flagZ 30 all condition flagN 31 all condition flag

AM


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AM7, AM9, AM10 AM11

7, 9, 10, 11

AM


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(+ cache)

ARM11

eight-stage3350.4 mW/MHz

1.2Harvard16 x 32

ARM7

three-stage800.06 mW/MHz

0.97Von Neumann8 x 32

ARM10

six-stage2600. 5 mW/MHz

1.3Harvard16 x 32

(+ cache)

ARM9

five-stage1500.19 mW/MHz

1.1Harvard8 x 32

(+ cache)

Pipeline depthTypical MHz

MIPS/MHz

MultiplierArchitecture

mW/MHz

AM F


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A


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Revision Example coreImplementation

ISA enhancement

ARMv1 ARM1 First ARM Processor26 bit addressingARMv2 ARM2 32 bit multiplier

32 bit coprocessor supportARMv2a ARM3 On chip cache

Atomic swap instruction

ARMv3 ARM6 & ARM7DI 32 bit addressingSeparate cpsr & spsrNew modes UNDEF, ABORTMMU support virtual memory

ARMv3M ARM7MARMv4 StrongARM Signed & unsigned long multiplyLoad store instructionNew Mode - System

A


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Revision Example coreImplementation

ISA enhancement

ARMv4T ARM7TDMI & ARM9T ThumbARMv5TE ARM9E & ARM10E Superset of the ARMv4TExtra inst. added for changing statebetween ARM & ThumbEnhanced multiply instructions

Extra DSP type instructionsFaster multiply accumulate

ARMv5TEJ ARM7EJ & ARM926EJ Java acceleration

ARMv6 ARM11 New multimedia instructions

I A


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2

4 *

5 * *

5 * * *

6 * * * *

6 * * * * *

62 * * * * *

AM


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AM7 F

AM7EJ

AM7DMI

AM7DMI

AM720

AM9/9E F

AM920

AM922

AM926EJ

AM940

AM946E

AM966E

AM968E

F F

F10

AM10 F

AM1020E

AM1022E

AM1026EJ

ARM11 Family

ARM1136J-S

ARM1136JF-S

ARM1156T2(F)-S

ARM1176JZ(F)-S

ARM11 MPCore

Cortex Family

Cortex-A8

Cortex-M1 Cortex-M3

Cortex-R4

Other Processors/Microarchitectures

StrongARM (DEC-Intel) Xscale (Intel- Marvell Tech)

Other

C F


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AM CA -A O

AM CA8, AM CA9

AM C -E

AM C4(F)

AM CM E , M

AM CM0, AM CM1, AM CM3


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AM

E =1

AME =0

A


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AM D G B AN. , D , C

AM O C A B

. B. F.

AM A M BD .


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arm architecture basics.pdf

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