analog circuit design techniques at 0.5 v shouribrata chatterjee department of electrical...
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Analog Circuit Design Techniques at 0.5 V
Shouribrata Chatterjee
Department of Electrical Engineering,
Indian Institute of Technology Delhi
2
Fully integrated 0.5 V analog circuits
• Gate and body-input OTAs• PLL-tuned filter and track-and-hold circuits• Operation from 0.45 V to 0.6 V• True low-voltage circuits for the nano-scale era
Track-and-holds
Biasing circuits
Master Slave
1.2 mm1.2 m
mFilter PLL
OTAs
1 mm
1 mm
Biasing circuits
3[ITRS'04]
Thick Oxide Vdd
Thin Oxide Vdd
Threshold
Technology node [nm]
Vol
ts
Deep-sub-1 V for nano-scale CMOS devices
4
Latch-up
• Positive feedback structure if Q2 switches ON• Requires VDD to be more than at least one diode drop
5
Body effect
6
Body effect
0.5 V OTA design
8Assuming |VGS - VT | ≈ 0.15 V, |VT | = 0.5 V
OTA design challenges
0.15 V
0.5 V
0.65 V
0.8 V
-0.15 V
0.15 V
0.15 V
0.3 - 0.35 V
9
Basic body-input OTA stage
[S. Chatterjee, Y. Tsividis, P. Kinget, ESSCIRC 2004]
0.25 V 0.5 V 0.25 V
0.25 V 0.15 - 0.35 V0.1 V
10
Two-stage fully-differential body-input OTA
Pole splitting using Miller capacitor
11
Micro-photograph
Chip prototype
• 0.18 µm CMOS mixed-signal process:– Standard nMOS and pMOS devices,– High resistivity poly resistors, – MIM capacitors.
• Die Area: 0.026 sq. mm
Layout
12
Assuming |VGS - VT | ≈ 0.15 V, |VT | = 0.5 V
Basic gate-input OTA
0.5 V
0.4 V
0.4 V
0.15 - 0.35 V
0.4 V
0.25 V
0.1 V
0.1 V
13
0.5 V gate-input OTA gain stage
[S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]
14
Two stage gate-input OTA
• Common-mode output of first stage is 0.4 V
• 55 dB gain, 15 MHz GBW, 60º PM for diff 10pF load
0.25 V
0.4 V
0.4 V
0.4 V
15
Two-stage gate-input fully differential 0.5 V OTA with Miller compensation
16
Setting common-mode voltages for the gate-input OTA
0.4 V
0.4 V
Rb = 2/3 • Ri||Rf
0.25 V 0.25 V
0.5 V
0.5 V
Gate-input OTA automatic biasing circuits
18
Error amplifier for biasing
• 20 kHz GBW for 1 pF load• 2 µA current• Controlled body voltage sets the amplifier threshold
Vin Vout
Vo
ut [
V]
Vin [V][S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]
19
On-chip biasing circuits
Vbn generating circuit
Level shift biasing circuit
(Simplified OTA)
20
OTA dc transfer characteristics and VNR generation
VNR generating circuit
Replica of OTA stage 1
Input differential voltage [mV]
Out
put
diff
vol
t age
[V
]
Increasing VNR
0.5 V body and gate-input OTA measurements
22
Body-input OTA open-loop frequency response
DC gain: 52 dB
GBW: 2.5 MHz
Phase Margin: 450
Simulation
Measurement
Frequency [Hz]
23Frequency [Hz]
Gai
n [d
B]
350 mV (Automatic gain-boosting)
50 mV
Increasing gain-boosting bias
GBW: 10 MHz
Gate-input OTA open-loop frequency response
0.5 V measured performance summaryParameter Body OTA Gate OTA
Power dissipation [µW] 110 75
Area [mm2] 0.026 0.017
Load capacitance [pF] (single-ended) 20 20
Offset standard deviation (20 samples) [mV] 3 2
Open-loop DC gain [dB] (diff.) 52 62/42
Open-loop unity-gain BW [MHz] (diff.) 2.5 10.0
Slew rate [V/µsec] (diff.) 2.9 2.0
Closed-loop unity-gain BW [MHz] (diff.) 2.2 5.0
CMRR @ 5 kHz [dB] 78 74
PSRR @ 5 kHz [dB] 76 81
Input ref. noise @ 10kHz [nV/sqrt-Hz] (diff.) 280 225
Input ref. noise @ 1MHz [nV/sqrt-Hz] (diff.) 80 70
Output amp. for 1% THD [mV p-p] (diff.) 400 712
Clo
sed
lo
op
Op
en l
oo
p
0.5 V weak-inversion varactor for frequency tuning
26
Filter tuning challenges at 0.5 V• Gm-C• MOSFET-C• Switching banks of R’s and C’s• Varactor-R techniques
Gate (0.4 V) Source
Drain (0.25 V)
Body (Vtune)
Vgate-Vtune or VGB [V]
Cg
s/C
ox
VGS = 0.15 V
VGS = 0.20 V
VGS = 0.25 V
[S. Chatterjee, Y. Tsividis, P. Kinget, VLSI 2005]
27
Capacitance characteristics
VGS [V]
Cg
s/C
ox
Region of interest for use as weak-
inversion varactor
Charge Sheet ModelChannel doping =
3.5e17/cm3 VFB = -1 V
Increasing VGB from -0.1V to 0.4V
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5th order elliptic low-pass filter using tunable integrators
Frequency [Hz]
Gai
n [d
B]
280 kHz
135 kHz
[S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]
29
Block diagram
30
Chip micrograph
• 0.18 µm CMOS• MIM capacitors• High-res resistors• Standard VT
• Triple well devices
Filter PLL
Biasing circuits
OTAs
1 mm
1 mm
31Frequency [Hz]
Gai
n [d
B]
Measured filter response for different supply voltages
32
Filter tuning through the varactor
Frequency [Hz]
Gai
n [d
B]
Notch at 120kHz, -42dB
200kHz, -50dB
VB [V]
Notch depth (sim.) [dB]
Notch depth
(meas.) [dB]
0.5 -45 -42
0.3 -47 -44
0.0 -53 -50
33
Filter performance summary at 27C VDD [V] 0.45 0.50 0.55 0.60
-3 dB cut-off frequency [kHz] 135.0 135.0 135.0 135.0
Total current [mA] 1.5 2.2 3.3 4.3
Noise [µV rms] 87 74 68 65
Input [mV rms] (100kHz / 1% THD) 50 50 50 50
In-band IIP3 [dBV] -5 -3 -3 -3
Out-of-band IIP3 [dBV] 3 5 3 5
Dynamic range [dB] 55 57 57 58
Tuning range [kHz] Vtune = VDD
Vtune = 0.0 V
96.5
153.0
88.0
154.5
84.5
148.0
69.0
150.5
VCO feed-thru @280kHz [µV rms] 104 85 72 72
Functionality tested from 5C to 85C at 0.5 V
• Measured CMRR (10 kHz common mode tone): 65 dB• Measured PSRR (10 kHz tone on power supply): 43 dB
0.5 V fully-differential track-and-hold circuit
35
Sampling challenges at 0.5 V
Large VDD
Small VDD
Enough headroom
No headroom
36
Basic track-and-hold architecture
•Voltages on both sides of the switches are signal independent.
•Signal-independent charge injection.
•Does this work at a 0.5V power supply?
voutvin
[Ishikawa, JSSC Dec 89]
37
Differential implementation at 0.5V
•Gate-input OTA used.
•Track phase during 1, hold phase during 2.
•During track phase, pole and zero cancel out to enable fast response.
•pMOS switches have VT of about 0.5V.
38
Track mode operation
• Resistors to 0.5V maintain required OTA input CM voltage of 0.4V.
• To enable better switching, both gate and body of the switch are used.
• No voltage swing on either side of the switches.
39
Hold mode operation
• Gate and body of the switch used for better switching.
• No signal swing on both sides of the switches.
• OTA input voltages held constant.
40
0.5 V fully-differential OTA
[S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]
41
0.5 V fully-differential OTA
[S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]
42
0.5 V fully-differential OTA
[S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]
43
0.5 V fully-differential OTA
[S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]
44
Design targets
• 1MHz of sampling rate.• 60 dB of signal to noise-distortion range.
• OTA worst case gain-bandwidth of 20MHz.• Worst case slew rate of 6V/µs.• Sampling capacitor of 1pF.
• To be designed using devices with VT 0.5 - 0.6V
• Switches sized to optimize resistance for settling, minimize noise, feedthrough.
45
Test plan: two track-and-holds in cascade
CLKA
CLKB
[Vorenkamp, JSSC Jul 92]
46
Prototype-chip block diagram
47
Track-and-hold chip micrograph
•0.25µm CMOS
•|Vt|= 0.6V
•MIM capacitors•Triple-well
devices•High-resistivity
resistors•Chip fabrication
supported by
Philips.
Track-and-holds
Biasing circuits
Master Slave
1.2mm
1.2mm
48
Some simulated results at 0.5V, 1M-sample/sec
Time [sec]
Ou
tpu
t tra
nsi
ent
[V]
Input at FS/2 x
127/128
Output at FS/2 x 1/128
Input amplitude [dBV]
SN
DR
[dB
]62dB simulated dynamic
range
49
Typical time-domain output waveform
Time [µsec]
Out
put
diff
eren
tial v
olta
ge [
mV
]
Re-sampled 25kHz output for a 200mVpp input at 475kHz
50
Measured SNDR
Input differential rms [dBV]
SN
DR
[dB
]
51
T/H noise analysis and measurements
€
vn2 =10 kT
C⋅
1
1+6/(ωgbRC)
Integrated rms differential input-refd noise:
Simulated Noise: 200µVRMS
OTA GBW: 20MHz
MeasuredNoise: 188µVRMS
OTA GBW: 15MHz
52
Measured performance
Power supply 0.5V
Current consumption 600µm
Sampling rate 1Msps
Diff. input refd. integrated noise 188µVRMS
Peak SNDR fIN=50kHz; Vin,diff=178mVRMS 60dB
Peak SNDR fIN=495kHz; Vin,diff=100mVRMS 57dB
Hold mode droop rate on diff. output 7.6µV/µV
Pedestal on diff. output 0.8mV
Track mode bandwidth 3.9MHz
53
Conclusions
• Developed true low voltage design techniques for 0.5 V analog circuits.
• 0.5 V gate and body-input OTAs designed - can be used as building blocks.
• Robust automatic biasing techniques developed.
• Weak-inversion MOS varactor developed.
• PLL-tuned 5th-order LPF demonstrated.
• 0.5 V track-and-hold circuit proposed.
• Step towards nano-scale circuits.
54
Further reading
• S. Chatterjee, Y. Tsividis, P. Kinget, “0.5-V Analog Circuit Techniques and Their Application to OTA and Filter Design”, IEEE Journal of Solid State Circuits, Dec. 2005, vol. 40, no. 12, pp. 2373-2387.
• S.Chatterjee, P.Kinget, “A 0.5-V 1-Msps Track-and-Hold Circuit with 60-dB SNR”, IEEE Journal of Solid State Circuits, Apr. 2007, vol. 42, no. 4, pp. 722-729.
• K. Pun, S. Chatterjee, P. Kinget, “A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-to-Open DAC”, IEEE Journal of Solid State Circuits, Mar. 2007, vol. 42, no. 3, pp. 496-507.