an overview of full adders in qca technology...full adder. in the last part we compare all of these...

International journal of Computer Science & Network Solutions December.2013-Volume 1.No4 http://www.ijcsns.com ISSN 2345-3397

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An Overview of Full Adders in QCA Technology A. Ammar Safavi, B. Mohammad Mosleh

Department of Computer Engineering, Dezfoul Branch, Islamic Azad University, Dezfoul, Iran [email protected]

Department of Computer Engineering, Dezfoul Branch, Islamic Azad University, Dezfoul, Iran [email protected]

Abstract

Quantum dot Cellular Automata (QCA) is a branch in nano-electronic for design the logical gates and circuits. The QCA logic gates composed from basic elements which are named as QCA cells. A QCA cell is a nanometer structure that constructed from nanometer semiconductors and capacitors. In QCA scope, we just have majority and inverter logic gates because of this fact that QCA cells perform their logical functions based on columbic forces between them and other QCA logic gates can be constructed by majority and inverter gates and QCA wires. Clock signals controls the QCA cells activities and states and the clocked QCA cells perform the delays and other features for design the conventional and sequential logic circuits. We demonstrate the clocking in QCA circuits using some examples in this paper. Since basic computing elements, in particular full adders are used in different parts of processing and computing circuits such as Arithmetic Logic Unit (ALU), Creating address for caches and main memories they are counted as major and fundamental part of processors. They extremely affect the speed, occupied space and power consumed of processors. In this paper at first step, we present the fundamentals of QCA technology including concepts, QCA logical gates. In the following, we present the famous designs for a 1-bit QCA full adder. In the last part we compare all of these 1-bit full adders using QCA DESIGNER simulator .We compare the cell count and delay time and occupied area and robustness against the temperature features. After review the QCA full adders we find this point that a good full adder have an efficient and compromised logical function using low number of majority and inverter gates. Also this point is important to know that most efficient full adders use the crossover and multilayer connections for reducing the occupied area and delay time and noises.

Keywords: Quantum dot Cellular Automata (QCA), Full Adder (FA), Majority gate, Clocking

I. Introduction

The QCA logic gates and circuits composed from some basic and simple elements which named as QCA cells. A cell is a nanometer structure like a square that has four Quantum dots and these Quantum dots are placed in four corners of the cell. The Quantum dot is a nanometer sized conductive materials which surrounded by an insulating material. So this structure could trap the electrons in three dimensional space and If an electron comes into a Quantum dot, it can’t escapes from the Quantum dot without enough electrical potential. Two extra electrons are intruded into QCA cell and these electrons have the ability of tunneling between Quantum dots. Each Quantum dot has a polarity and its polarity denote the electrical charge of the dot. Two extra electrons in the cell have columbic interaction together and they can have two possible arrangements due the columbic forces and their polarities. These two arrangements which have negative or positive polarities represent the binary 0 or 1 for the cell. Four Quantum dots are connected together using tunnel junctions and we can control the voltage of the tunnel junction to freeze

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state or active state of device like a enable signal that allows to control the state of QCA cells. Two types of QCA cells could be used in QCA circuits which are normal cells and diagonal cells(Lent et al,1997). Physical and electrical structure of a QCA cell and two types of QCA cells and their possible polarities showed in Figure1. The polarities of the Quantum dots labeled as p1 and p2 and p3 and p4.

Figure.1. a) QCA cell structure. b) QCA cell electrical structure. c) Normal clocked QCA cell. d) diagonal QCA cell

II. Backgrounds

A. Basic QCA gates

In simplest schema, if we have two neighbors QCA cells and an external polarity induced to one of them as an input signal, then the next cell copies a polarization from neighbor cell polarity because of columbic interaction between cells and its copied polarity depended on the position of this cell. If we place some QCA cells close together in a horizontal or vertical chain, so these neighbor cells act as a QCA wire. The columbic force between two cells is calculated by KINK ENERGY formula and this energy between two neighbor cells is calculated by Eq.1. In this equation, r is the distance between cells and θ is the degree between cells. Due the Eq.1 if the QCA cells be closer then the kink energy is greater and then the neighbor cells copy a better signal. If the polarizations for the Quantum dots be as p1 and p2 and p3 and p4 then the polarization of the cell could be calculated with Eq.2.



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= ( )(cos (4 )) (1) P= [(p2+p4)-(p1+p3)] / (p1+p2+p3+p4) (2)

We have two possible selections for placement the neighbor cells. As showed in Figure2, The Kink energy between cells in Figure2.a is greater than energy between two neighbor cells in Figure2.b because of the greater distance and different θ [1]. Of course, the polarity of the output cells in these two schemas is different together. We can construct the non-inverter gates like majority gate and QCA wires using the first schema (Fig2.a) and the inverter gate using the second schema. The polarization of output cell in this Fig2.b is opposite to polarization of the input cell.

Figure.2. KINK energy between two QCA cells

We can build a QCA wire to act as an intermediate connection between QCA gates and circuits. We can use normal or diagonal cells to construct a QCA wire. Other two basic QCA logical gates are the inverter and 3-input majority gate. We can build logic AND gates and the logic OR gates using 3-input majority gates. So, we can translate conventional logic circuits using inverter and majority gates to the QCA logic circuits. We can see the basic QCA gates in Figure3. Algebra equation for 3-input majority gate is as Eq.3.

MV3 (A,B,C)=AB+BC+CA (3)

As mentioned, we can implement the logic AND gate and the logic OR gate using 3-input majority gates. Algebra equations for these implementations are as Eq.4 and Eq.5 (Hashemi et al,2007).



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MV3(A,B,0)=AND(A,B) (4) MV3(A,B,1)=OR(A,B) (5)

Figure.3. Famous QCA gates and two types of QCA wires

Also we can use the majority-minority gate and 5-input majority gate in QCA designs and these two gates are very useful for design QCA circuits and some efficient full adders designed using these gates. Algebra equations for these gates are as Eq.6 for the 5-input majority and Eq.7 and Eq.8 for the majority-minority gate (Rahimi et al,2007).

MV5(A,B,C,D,E)=ABC+ABD+ABE+ACD+ACE+ADE+BCD+BCE+BDE+CDE (6) O1= ̅ + ̅ + ̅ ̅ (7) O2=AB+BC+CA (8)

We can see the QCA layout and the logic symbol for these two gates in Figure4.As we know ,the logical QCA gates like other technologies have some input lines and some output lines.If we notice to the basic QCA gates we find this point that all of them have odd number of inputs. In the QCA scope we just have the columbic forces between cells and most QCA gates have odd number of inputs. The force of input cells is equal together and if we have even numbers of inputs for a QCA gate and the polarity of half of these inputs be at logic 0 and the polarity of reminder inputs be at logic 1, then the sum of these forces is



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zero and so the polarity of output cell is not recognizable because of this fact that kink energy at the output cells is zero. This is like a high impedance output in transistor based circuits. Of course we assume that the distances between the output cell and each of input cells is equal. for example if we have a 4-input majority gates with A,B,C,D inputs and an F output. So if we give to the inputs of 4-inputs majority gate some polarities like {A=1 ,B=1 ,C=0, D=0 è F=?} or {A=1 ,B=0 ,C=1 ,D=0 èF=?} , then the polarity of the output F is invalid because the sum of the Kink energies between the input cells in a hand and the output cells in other hand is being equal to zero. So we design just the QCA gates with an odd number of inputs and so we can recognize the polarity for any output or intermediate cell. We can see the 4-input majority gate and its problem in Figure4.c.

Figur.4. A)5-inputs majority gate(Rahimi et al,2007). b) majority-minority gate. c) 4-input majority gates can’t be implemented.

B .QCA clocking

The Clock signals divide the QCA circuits into some sections and each section performs its duty in a clock phase. The clock signal in QCA circuits usually is been divided into four phases and if our circuit has more than four sections then our circuit completes its logical function or calculation in more than 1 clock cycle delay. A QCA gate needs enough time for calculating its output and in another hand, the number of QCA cells in a section of a circuit or a gate must not be so great (Bhanja et al,2007). QCA cells act as an amplifier and amplify the cross talk and other noises and the input signals mustn’t propagates across the high number of cells in a clock phase. If we use a 3-inputs majority gate then the number of cells in all inputs of majority gate must be equal and the number of used cells for construct the majority gate must not be greater than 15 cells and this majority gate must act in one or more than one clock phase delay. Also if a majority gate acts in more than one clock phase then the majority gate act better because of this fact that it has more delay and more time for working and then give us a stronger



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signal on its output. In most books and journals and all simulation software’s for QCA circuits, four dashed colors are used for presentation the four clock phases. Assume that we have a circuit like Figure5 and this circuit has seven inputs as a, b, c, d, e, f, g wires and two outputs as out1, out2 wires. As we can see in Figure5, three gates which labeled as gate1, gate2, gate3 are placed in phase0. Note that logical gates like gate1 and other gates may have similar or different structures and the intermediate wires may be different in length and shape. The Gate1 and gate2 and gate3 complete their calculation at the end of phase0 and at the beginning of phase1, the gate1 and gate2 send their outputs for the input of gate4 via the wire1 and wire2. Simultaneously, the gate3 send its output to the second section of wire3 (wire3-2). The Second section of wire3 acts in phase1. The Gate4 calculate its two outputs and at the beginning of phase2 send its outputs to the wire4 and gate5 .simultaneously, the second section of wire3 (wire3-2) send its polarity to the input of the gate5. The Gate5 and the second section of wire4 act in the phase2 and at the beginning of phase3, they send their outputs and polarities to the section3 of wire4 and gate6 and then the gate6 and wire4 generate the outputs out1 and out2 at the end of phase3. If we look at Figure4, we find this point that clocked QCA circuits act like the pipelined circuits. We assume that wire1 be taller than wire2 and wire3 and the gate1 have more propagation delay than gate2 and gate3. So we calculate the propagation delay of gate1 and add this delay to the delay of wire1. So we have the Eq.9.

Estimated delay of phase0 = (delay_of_gate1) + (dalay_of_first Section of (wire1)) (9)

So we can calculate the delay of other phases and then we can calculate the period of clock cycle and period time for a clock phase using Eq.10 and Eq.11.

Clock cycle period time=4*longest estimated delay of (phse0, phase1, phase2, phase3) (10) Period time for any phase=clock cycle period time/4 (11)

Figure.5. Clock cycles make the circuit to act as a pipeline

Each QCA cell spends four states during a clock cycle. QCA cell states are named as switch and hold and release and relax states (Ottavi et al,2004). As we know, the clock signals coming periodically from the clock source and so four clock phases’ signals are activated periodically and in each clock phase, a part or sub circuit of a circuit is activated periodically in its clock phase. When we place some QCA cell in a



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clock phase such as phase0, then these cells go to switch state when the phase1 signal is being activated. In switch state, a QCA cell could take a logic 0 or 1 polarization from the input cells or its neighbor cells. at the end of switch state ,the next clock phase signal is coming and the QCA cell go to the hold state and those QCA cells which are placed in the next clock phase(phase1) go to the switch state and can be affected by those cells which are placed in the previous clock phase. A QCA cell that is in the hold state, hold its polarity and after a clock phase by coming the next clock phase signal, it comes into the release state. In the release state, the QCA cell releases its polarity and can’t be affected by the input signals or neighbor cells. In the next clock phase the QCA cell go to the relax state. In the relax state the QCA cell has not any polarity and can’t be affected by neighbor cells. The two final cell states which are named as release and relax generate delay time and we can use these states for design sequential logic circuits (Askari et al ,2011). We can see states of the cells of a QCA wire in their clock phases in Figure6. This QCA wire act as a D-Flip Flop and hold its polarity for a clock phase delay and could not be affected by input signals or neighbor cells for two clock phases. So the inputs of a QCA gate or wire can be isolated from its output for two clock phase’s duration and this structure is like a master-slave flip flop.

Figure.6. Clock phases and cell states

The clock wires are surrounded below the QCA surface and each wire is corresponded to some QCA cells. The clock wires can control the activity of a QCA cells and the state of QCA cell is depended to the state of clock signal waveform .As we can see in the Figure6, the clock phases signals have rising edge and falling edge and zero state and one state (Ganesh et al,2005). The rising edge of a clock phase force its corresponding cells to go to switch state. The rising edge of a clock phase signal ended after a clock phase delay and then the clock phase signal go to its high level amplitude for a delay time equal to a clock phase delay. The high level signal in a clock wire force its corresponded cells to go to hold state. The falling edge and low level state of clock phase signals force their corresponded cells to go to release and relax states. We can see two clocked QCA circuits in Figure7 for an example. Conventional function for OUTPUT1 circuit is as Eq.12 and conventional function for OUTPUT2 is as Eq.13.

OUTPUT1= ( ( , , ), , ( , , )) (12) OUTPUT2= ( ( , ( , , ), ), , ( , , )) (13)



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Figure.7. An example for clocking in QCA circuits

As showed in Figure7 .a, we connect the A and B and C inputs to a 3-input majority gate. Input QCA wires and 3-inputs majority gate are placed in the phase0 of clock signal and this gate perform the majority function .we can place the cells of input wires A and B and C and the majority gate in phase0 but in the Figure7.b we change the B input by the output of a 3-inputs majority gate (F1 wire). So in Figure6 .b, the input signals H and B and N must come into the inputs of this gate simultaneously but the A and C inputs come faster than output of the majority gate that is labeled as F1 wire. So we must place the input wires A and C and majority gate in phase0 and place the next majority gate in the next phase. So the A and F1 and C signals are ready on the inputs of the next majority gate at the final of phase0 duration and the next majority gate perform a true calculation at the start of phase1. So the circuit1 has a lower delay and perform OUTPUT1 function in three clock phases and circuit2 has more delay and perform OUTOUT2 function in four clock phases (Zhang et al,2004).

C. coplanar crossover and multi-layer crossover connections

In complicated QCA circuits we have two possible alternatives for reducing the circuit’s occupied area. One of these ways is coplanar crossing connections. As showed in Figure8.a, a coplanar connection uses a diagonal wire which passed across the normal wire without any problem. Of course if the circuits be very complicated it is possible that normal wire signal be destroyed because of the distance between its two sections. If we want to have a good signal transformation in crossover connections, we must place two coplanar wires in two different clock phases. In the first phase one of our signals passed and in the next phase another signal is passed without crosstalk with other signal. This methodology is used in Hanninan-Takala full adder and we present this full adder in the next section. A better way for passing a QCA wire across other wires or circuits is multi-layer crossover connections. In Figure8.b, a wire that carries the logic 0 is passed from its main layer and another wire come to the second and third layers and then passed from third layer and then come down to its main layer(Haruehanroengra et al ,2007). We present some QCA full adder circuits in the next section which use coplanar and multilayer connections. Using multilayer connection, we are not worry about the clocking cells and crosstalk noises.



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Figure.8. Coplanar and multilayer connections (Haruehanroengra et al ,2007)

We must know that polarization of the second section of normal wire in a coplanar connection like Figure8.a is depended in placement of normal cells. As we can see in Figure9, if we place the QCA wires like Fig9.a then we have a copy of normal wire input signal in output of the normal wire and in Figure9.b we have the inverse of the input signal and in Figure9.c we have both copy of input signal and inverse of the input signal at out1 and out2. We can also use from inverter gate that is showed in Figure9.d. These inverter and non-inverter coplanar wires that implement invert and non-invert logics are used in some QCA full adders such as Wang-Walus and Tougaw-Lent.

Figure.9. Some inverter and non-inverter gates using coplanar crossover wires

II. QCA full adders

Now we are ready to study the 1-bit QCA full adders. The basic and most important part of any Arithmetic and Logic Units and other important circuits is adder circuit and most adder circuits are composed from 1-bit full adders. The block diagram of a 1-bit full adder is showed in Figure9. A full adder has three inputs A and B and carry-in and two outputs SUM and CARRY-OUT. Algebra equations for generating the SUM and CARRY-OUT are as Eq.14 and Eq.15.

SUM=XOR (A, B, Cin ) (14) Cout=A.B+B.Cin+Cin.A (15)



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But we know that in QCA scope we just have majority and inverter logics .So we must rewrite these equations using majority and inverter gates. As mentioned later, we can implement the logic AND gate and the logic OR gate using 3-inputs majority gate. But using this method, the number of QCA cells becomes very high and this is not a good way. We can do a better action and rewrite the Eq.13 and Eq.14 and change them to Eq.16 and Eq.17. Now we have better equations which use just the majority and inverter gates and also are simpler than previous equations.

SUM=MV(MV(A, ,Ci),MV(A,B, ),MV( ̅,B,Ci)) (16) Cout=MV (A ,B ,Ci ) (17)

If we implement a QCA 1-bit full adder using AND-OR gates we need ten majority gates and two inverter gates but if we implement the full adder using MV3 and NOT gates then we need five majority gates and three inverter gates. As showed in Figure10, implementation of the full adder using MV3 and NOT gates is so better than design full adders using AND-OR gates.

Figure.10. a) Conventional full adder block diagram. b) Conventional logic circuit for a full adder. c) Logical circuit using QCA gates for a full adder.

A. Tougaw and Lent QCA full adder

The first design for a 1-bit QCA full adder was proposed by Tougaw and Lent. The algebra equations for this adder are as Eq.15 and Eq.16. The Tougaw-Lent [1] design is showed in Figure11 .In this design some coplanar connections are used for translate and passing the input signals to the core of circuit. Input signal A is passed across the B and C wires and B signal passed across the C wire. As showed in Figure10, the A signal passed throw the three paths and the B signal passed throw three paths. These paths are as follow:

Path1_A:{a1-a2-a3} , path2_A:{a4-a5-a6} , path3_A:{a7-a8-a9}

Path1_B:{b1-b2} , path2_B:{b3-b4} , path3_B:{b5-b6}



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We present some inverter and non-inverter gates which constructed using coplanar crossing connections in previous section. We have a high number of coplanar crossing connections in Tougaw-Lent full adder. As mentioned later about the coplanar connections, it is better that two crossover wires (a normal wire and a diagonal wire) to be in two different clock phases. But in Tougaw-Lent full adder, all of coplanar crossover wires are in a same phase (phase0). Another problem in this adder is that all of its QCA cells placed in one clock phase. So this full adder is just important as a basic full adder and is not applicable. The designers implement some good QCA full adders such as Wang-Walus and Zhang full adders which are similar to Tougaw-lent full adder in layout and we present these full adders in next sections.

Figure.11. Tougaw and Lent QCA full adder cell layout [1]

This layout designed using 192 QCA cells and has 0.20 um2 occupied area. High number of cells in this full adder is because of the huge coplanar crossover connections. Notice to this point that passing input signals using coplanar crossover connections and placement the cells is difficult.

B.Wang- Walus QCA adder

We can change the Eq.15 using algebra manipulations and use the Eq.18 for generating the sum output. So we have a better and efficient logic function for generating the sum output. This design proposed by Wang and Walus (Wang et al, 2003) .We can see the QCA logic circuit for generating the sum and carry



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outputs in Figure12. The number of QCA gates is reduced in compare with Tougaw-Lent full adder and it also has a better clocking.

SUM=MV(MV( ̅, , ),MV(A,B, ),Ci) (18)

Figure.12. Wang and Walus QCA full adder logic circuit (Wang et al, 2003)

Wang and Walus also present a QCA layout for this design. In this adder the coplanar crossover connections are used for translating the input signals to the core of the adder and the coplanar crossover connections make this design like to Tougaw and Lent adder. The QCA layout for this design is showed in Figure13. This adder has 5 clock phases delay time and implemented by 145 cells and 0.17 um*2 occupied area (Wang et al, 2003). Notice that these two full adders are similar together in passing the input wires across together ( by coplanar crossover connections) but the Wang-Walus full adder has lower number of QCA gates and also Wang-Walus full adder has a different logic for generating the sum output.



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Figure.13. Wang-Walus QCA full adder cell layout (Wang et al, 2003)

The high number of cells in this full adder is because of huge coplanar crossover connections but the input signals A and B and C have not the crosstalk problem between input lines because of good clocking. As we can see in Figure13, the input wire A is passed across the wires B and C via the {a1-a2-a3} and {a4-a5-a6} paths. Similarly, the B input wire passed across the C wire via the {b1-b2} and {b3-b4} paths. In passing the A wire across the B wire and in passing the wire B across the wire C we have not any problem because of good clocking. When input signals pass across the other wires in coplanar crossover connections, then the output signals may be inverted or non-inverted. We present the coplanar crossover later .a variety of coplanar crossover connections are used in Tougaw-Lent full adder.

C. Zhang QCA full adder

Zhang full adder is similar to Wang-Walus adder but this adder is designed using multilayer crossover connections and lower number of cells and lower delay in compare with previous QCA full adders (Haruehanroengra et al ,2007). We can implement this full adder using 108 QCA cells and 1 clock cycle (4 phases) delay and 0.1 um*2 occupied area. An implementation of this adder is showed in Figure13. This full adder is a robust full adder against the temperature. Notice to this point that the Zhang full adder has lower cells in compare with Figure13 and we can implement the Zhang full adder with smaller wires and lower number of cells and we draw the Figure14 with 172 cells for better learning.



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Figure.14. Zhang QCA full adder (Haruehanroengra et al ,2007)

Notice that in Tougaw-Lent and Wang-Walus and Zhang full adders, we give the input signals to the inputs of full adders via the three horizontal or vertical lines A and B and C. this way make our design regular and give us some alternatives for passing input signals across each other . But this method will increase the number of used cells. Of course, this way is better for design modular n-bit adders and we can construct an n-bit adder using these 1-bit full adders simpler and more regular.

D. Hannian and Takala full adder

This adder is showed (Hanninan et al ,2007) in Figure15 and designed using coplanar crossover connections .the wire A is placed in phase0 and we want to pass the A input across B and C inputs. If the wire a1 and wire a2 and wire a3 be in phase0 like Tougaw-Lent full adder, so it is possible that A or B signals be destroyed because of crosstalk noise, but in this adder the signal A pass from a1 and a2 and a3 wires and signal B pass from b1 and b2 wires. Using this timing the input signals pass from other wires without any problem. Of course the delay of this design is two clock cycles (8 clock phases). This design has 102 cells and 0.1 um*2 occupied area. This full adder is a robust QCA full adder and its high delay and the high number of cells is for robustness against the temperature and other unwanted noises.



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Figure.15. Hannian and Takala QCA full adder (Hanninan et al ,2007)

E. Cho,s QCA full adder

Another QCA adder that is based on Wang and Walus full adder layout and its algebra equations is the Cho full adder (Cho et al,2009) (Heumpil et al,2009). Using multilayer crossover connections we can change the layout of Wang- Walus full adder and make it efficient in number of used cells and delay. This design is showed in Figure16. This full adder has 86 cells and its occupied area is 0.11 um*2. We have not any coplanar crossover connection here and so the number of cells is reduced to 86 cells.



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Figure.16. Cho,s QCA full adder cell layout (Cho et al,2009)(Heumpil et al,2009)

F. Azghadi QCA full adder

We presented the 5-inputs majority gate in this paper. As showed in Figure17, using this QCA gate we can generate SUM and CARRY (Rahimi et al,2007) .this design was proposed in Azghadi et al. Algebra equations for generating the sum and carry outputs are as Eq.19 and Eq.20.

Cout=MV3(A,B,C) (19) SUM=MV5(A,B,C, , ) (20)



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Figure.17. Azghadi QCA full adder logical circuit (Rahimi et al,2007)

In the next parts we study some QCA full adders which are based on Azghadi QCA full adder.

G. Hashemi QCA full adder

This QCA full adder is based on Azghadi design and proposed in Hashemi et al. As showed in Figure18 , This design uses 51 cells and has three clock phases delay and its occupied area is 0.04 um*2. Like the Cho adder the multilayer crossover connections used for reduction the occupied area (Hashemi et al,2007).

Figure.18. Hashemi QCA full adder cell layout(Hashemi et al,2007)

H. Navi QCA full adder

Another adder is Navi QCA full adder (Navi et al,2004). This adder is similar to Azghadi adder but it has two inverter gates and its layout is different from Hashemi's full adder. As showed in Figure19 the



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multilayer connections used very good and reduced the occupied area to 0.04 um*2. This design has 73 cells and three clock phases delay.

Figure.19. Navi QCA full adder logical circuit and cell layout (Navi et al,2004)

We have a problem with this full adder. If we want to build an n-bit QCA full adder using this full adder then we can’t connect the input lines with A and B and C input cells from the main layer and layer2. We must give the inputs from another layer via the vertical QCA cells. So we must route the input lines to intermediate layer and then connect them to the input cells of Navi full adder and use at least 15 extra cells. We can see this problem in Figure20. In this Figure we add an intermediate layer for routing the inputs and use 15 extra cells which are not colored (white cells). If the input lines for an n-bit QCA adder be in the main cell layer then the design is being complicated.



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Figure.10. Navi full adder problem

IV. Comparisons

In this section we compare the QCA full adders together and focus on delay and occupied area and number of used QCA cells and gates and polarization and robustness of these adders against the temperature factors.

A. Number of used gates comparison

In table1 we compare the number of used QCA gates for these full adders. We can find three types of full adder’s .If the algebra equations for generating the outputs of a full adder are being simple and use less number of QCA gates then we can build a better full adder. The first type of full adders such as Hashemi and Navi full adders use the 5-inputs majority gate as the main building block. The Hashemi full adder uses the Azghadi equations for generating the sum and carry-out outputs and is the best full adder in number of used gates factor with 3 QCA gates. In fact this full adder is an implementation from Azghadi full adder. Navi full adder with four gates uses the algebra equations which are same as Azghadi equations but Navi full adder has one inverter gate more than Azghadi full adder and also it is different



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from Hashemi in QCA layout. The second type of full adders such as Cho and Wang-Walus and Zhang and Hanninan-Takala full adders use same algebra equations for generating the sum and carry outputs and all of these full adders are based on Wang-Walus full adder equations. The full adders in this type have 5 QCA gates and use the 3-inputs majority gates as the main building block. The third type of full adders includes just the Tougaw-Lent full adder and its algebra equations are very simple. As we can see in Table1, Tougaw-Lent full adder is the first QCA full adder and use 8 QCA gates. So in comparison the full adders in number of used gates feature, the Hashemi is better than other full adders and this feature make this full adder efficient in number of cells feature.

TABLE I COMPARISON OF QCA FULL ADDERS IN USED GATES FACTOR

Full adder name No. Gates Tougaw and lent[1]

8gates=5 MV3+3 NOT

Wang and walus(Wang et al, 2003)

5gates=three 3-inputs majority gates+ two NOTs

Zhang(Haruehanroengra et al ,2007)


Cho[6]


Navi(Navi et al,2004) 4gates=one 5-inputs majority +one 3-inputs majority+ 2 NOTs

Hashemi(Hashemi et al,2007) 3gates= one 5-inputs majority +one 3-inputs majority+ 1 NOTs

Hanninen and Takala(Hanninan et al ,2007)


B. Number of used cells comparison

In Table2 we compare the QCA full adders in number of used cells factor. As we can see in this table, the first type QCA full adders like Hashemi is the best full adders in number of used cells and this efficiency is because of the low number of used gates and multilayer connections. Between the second type of full adders like Wang-Walus and its similar full adders the Cho full adder is better than others because of comfortable multilayer connections. Also the Wang-Walus and Zhang full adders are not so good in number of used cells feature because their coplanar crossover connections consume many QCA cells. The Tougaw-lent full adder with 192 cells is the worst full adder in number of cells feature and of course it is not applicable. The Wang-Walus and Hanninan-Takala full adders need high number of cells for implementation but they are robust against the temperature. As mentioned in the previous section, the Navi full adder needs at least 15 extra QCA cells for passing inputs into the core of full adder. So the Navi full adder needs 88 cells and takes place after the Cho full adder in number of cells factor. Except Navi full adder, other full adders are scalable and the input lines can simply be connected to the core of the full adder.



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TABLE II COMPARISON OF QCA FULL ADDERS IN NUMBER OF USED CELLS FEATURE.

Full adder name No. Cells Tougaw and lent[1] 192

Wang and walus(Wang et al, 2003) 145 Zhang(Haruehanroengra et al ,2007) 108

Cho[6] 86 Navi(Navi et al,2004) 73+15 extra cells=88 cells

Hashemi(Hashemi et al,2007) 51 Hanninen and Takala(Hanninan et al ,2007) 102

C. Delay comparison

In Table3 we compare the QCA full adders in delay features. Like previous comparisons, the Hashemi and Navi and Cho full adders are better than others and this efficiency is because of the less number of used cells. As we can see in Table3, the Hanninan-Takala has a long time delay because its high delay time make this full adder robust. If QCA gates act in more clock phases and have more time for performing their logical function then they give a better and stronger output.

TABLE III

COMPARISON OF QCA FULL ADDERS IN DELAY FACTOR

Full adder name Delay(clock phases) Tougaw and lent[1] Not applicable

Wang and walus(Wang et al, 2003) 5 Zhang(Haruehanroengra et al ,2007) 4

Cho[6] 3 Navi(Navi et al,2004) 3

Hashemi(Hashemi et al,2007) 3 Hanninen and Takala(Hanninan et al ,2007) 8

D. Occupied area comparison

At this point, we want to compare the QCA full adders in occupied area factor. As we know, this factor is depended in other features such as number of used cells and the used alternatives for building the layout of full adder such as multilayer and coplanar crossover connections. As we can see in Table4, the Hashemi and Navi and Cho full adders are better than other full adders because of low cell count and multilayer connections. Some QCA full adders such as Zhang and Tougaw-Lent full adders occupy a high area because of using coplanar crossover connections and high cell count.



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TABLE IV

COMPARISON OF QCA FULL ADDERS IN OCCUPIED AREA FACTOR

Full adder name Occupied area(um*2) Tougaw and lent[1] 0.2

Wang and walus(Wang et al, 2003) 0.17 Zhang(Haruehanroengra et al ,2007) 0.22

Cho[6] 0.1 Navi(Navi et al,2004) 0.04

Hashemi(Hashemi et al,2007) 0.04 Hanninen and Takala(Hanninan et al ,2007) 0.1

E. Robustness against the temperature

Now we want to compare QCA full adders in another feature. This feature is polarization against the temperature. We can see this comparison in Diagram1. As we can see in this diagram, the Zhang full adder is the best in robustness against the temperature factor and Cho full adder is in better than hashemi and Navi full adders. These QCA full adders are simulated by QCA DESIGNER software and the coherence vector options for these simulations are as follow:

{temperature:-10 to +20 Kelvins , Relaxation time= 1.000000e-015, time step=1.000000e-016 ,total simulation time=7.000000e-011 ,clock high=9.800000e-022 ,clock low=3.800000e-023 ,clock shift=0.000000e+000, clock amplitude factor=2.000000,Radios of effect=80.000000,relative permittivity=12.900000,layer separation=11.500000}.

The Zhang QCA full adder is the most robust QCA full adder between compared full adders because of high cell count and great occupied area and good timing for coplanar connections.



34

Diagram1. Compare the QCA full adder in robustness against the temperature

E. Conclusion

We discuss the QCA cell and its properties and then the QCA wires and logical gates and then the QCA clocking. The coplanar crossover connections and multilayer connections are so useful for design QCA circuits. As we can see in the Table1, using the coplanar crossover connections we can design robust full adders. After we learn the basics of QCA we present the QCA full adders and then compare the QCA full adders. Like the transistor based circuits and devices the QCA circuits must have the low delay and low area and power dissipation. So an efficient QCA full adder must has low delay and low number of cells and low area. Of course low number of cells in any QCA design cause the low delay and low area. We mentioned later that if our algebra equations that produce the outputs of circuit be simpler then the circuit is efficient in cell count and delay and other features. As we show in previous chapters, low cost QCA full adders and low delay full adders are so robust against the temperature. We did not use the Hanninan-Takala full adder in our comparison because of this fact that Hanninan-Takala is a robust adder and its robustness is because of high delay time and so it is not comparable with low count full adders like Cho full adder. Also we know, The Zhang full adder is a low delay full adder but it has a good robustness against the temperature because of it has 108 cells and it is a high cost adder. So, at the first step we must write the efficient algebra equations for outputs of our circuit and then we can use the comfortable multilayer connections for reducing the cell count. Using comfortable clocking scheme we can reduce the

0.00E+00

1.00E-01

2.00E-01

3.00E-01

4.00E-01

5.00E-01

6.00E-01

7.00E-01

8.00E-01

9.00E-01

1.00E+00

-10 -5 1 2 3 6 7 10 14 20 kelvins .

zhang

cho

hashemi

navi



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delay time for fast circuits or increase the robustness of circuit using more delay time. In last step we must include some tradeoffs between delay and cell count and the robustness features and then we can compromise our circuit.

References

i. Dr.E.N.Ganesh , Professor ,Implementation and Simulation of Arithmetic Logic Unit ,Shifter and Multiplier In Quantum dot Cellular Automata, International Journal Of Computer Science and Engineering, vol.02,No.05,2010,1824-1829

ii. Cho et al, Adder design and analyses for quantum-dot cellular automata , IEEE, Transactions On Computer, Vol. 58, No. 6, 2009.

iii. Ismo Hanninan and Jarmo Takala , Robust Adders Based On Quantum dot Cellular Automata , Pl553,33101 tampere finland,2007.

iv. K.Navi et al, A New Quantum Dot Cellular Automata Full Adder, Microelectronics Journal, Vol.41, No. 12, pp. 820-826, 2010.

v. Marco Ottavi Member IEEE and Sarah Frost-Murphy Student Member , Partially Reversible Pipelined QCA Circuits: Combining Power and Throughput, IEEE

vi. Mehdi Askari and Maryam Taghuizadeh, Logic circuit design in nano-scale using Quantum Dot Cellular Automata , European journal of scientific research ISSN 1450 -216X vol.48 No.3, 2011.

vii. Mostafa Rahimi Azghadi and o.kavehei and K.navi ,A Novel Design For Quantum-Dot Cellular Automata Cells and Full Adders , Journal of Applied Sciences, Vol. 7, No. 22, 2007.

viii. Heumpil Cho and Earl E.swartzlander , Adder and Multiplier Design in Quantum dot Cellular Automata, IEEE transactions on computers vol.58 No.6, june 2009

ix. S.Lent and P.Douglas Tougaw , A Device Architecture for Computing with Quantum Dots, proceeding of the IEEE ,VOL 85,NO.4,APRIL 1997.

x. Sansiriu Haruehanroengra and Wei Wang, Efficient Design of QCA Adder Structures, Solid State Phenomena vols.121-123, 2007.

xi. Sara Hashemi and Mohammad Tehrani and Keivan Navi, An Efficient Quantum-dot Cellular Automata Full Adder, Scientific Research Essays Vol.7(2) pp.177-189 , 16 January 2012

xii. Sanjukta Bhanja and Marco Ottavi and SalvatorePpontarelli and Fabrizio Lombardi , QCA Circuits For Robust Coplanar Crossing, Tampa, (FL) 33620 , USA

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an overview of full adders in qca technology...full adder. in the last part we compare all of these...

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