107

An autolayout system for a hierarchical i.c. design environment *

H.K.E. Liesenberg and D.J. Kinniment Department of Electrical and Electronic Engineering, The Merz Laboratories, The University of Newcastle upon Tyne, Newcastle upon Tyne, NE1 7RlJ. United Kingdom

Received 5 June 1983

Abstract. Ideally, the high level language input to a silicon compiler should only contain information relevant to the structure and behaviour of the system specified, abstracting out as much as possible to the physical detail. This can be achieved by autolayout software which computes the placement of components and the routes required by connections, but layouts achieved by present algorithms are not usually as good as those produced by manual designs based on a structured methodology. The extra area required by the connections in a poor layout limits the chip performance as well as increasing the chip size and the placement phase of the process is often a major cause of poor layout.

This paper describes work aimed at integrating a layout system with a high level structural design language to provide the layout element of a silicon compiler, and consists of two main areas. Firstly, an autolayout program is described which presently interfaces to a relatively simple cell based hierarchical description language, and secondly moves towards integrating the program with a more advanced language are outlined.

The algorithm used for routing has a global phase in which connections are assigned to channels followed by a detailed phase in which the channel space required is evaluated and actual connection paths are determined. The autolayout itself is hierarchical so that advantage can be taken of regularity and structure in the input description and the amount of computation will not become prohibitive in a large design.

Work is then described aimed at the use of autolayout in a more sophisticated ‘silicon compiler’ environment where an input language captures the structural, functional and some of the physical aspect of the design. From the autolayout point of view a number of constructs exist to allow composition of parts in a hierarchical manner. These include declarations of connection points and structures of these points, association of points and

* This research has been financially supported by Grants from SERC (UK), CNPq (Brazil) and UNICAMP (Brazil).

North-Holland INTEGRATION, the VLSI journal 1 (1983) 107-119

0167-9260/83/$3.00 0 1983, Elsevier Science Publishers B.V. (North-Holland)

108 H.K. E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment

structures in nets, instantiation of blocks and the relative placement of these instances as well as more usual constructs. The description will be metric free, but a degree of control of the floor plan is possible as a result of the specification of relative placement so that compara- tively good layout can be achieved without the necessity to consider the details of the design. Examples are given of both the language and layout.

Keywords. Hierarchical i.c. design, VLSI design methodology, silicon compilation, autolayout, relative placement.

Hans K.E. Liesenberg received the BSc (1977) and the MSc (1980) degrees in Computer Science from the Universidade Estadual de Campinas (Unicamp), Brazil. Since April 1982 he has been undertaking a post-graduate course leading to the degree of Ph.D. in the Faculty of Engineering at the University of Newcastle upon Tyne, England. His main topic of interest is CAD tools.

David J. Kinniment graduated from Manchester University (United Kingdom) in 1962, and from 1964 to 1978 was concerned with a number of aspects of research into large computer systems in the Department of Computer Science at Manchester. During this period he contributed to the later stages of the ATLAS project as well as being largely responsible for the development of associatively accessed mem- ories in MU5 Computer System. He currently holds the Chair of Electronics at the University of Newcastle upon Tyne where he has initiated a major research project in VLSI design methodology and i.c. design tools.

1. Introduction

One of the aims of a silicon compiler is to provide a fast, simple and correct path from a procedural specification language to technology dependent detailed mask description files. This process is often likened to the compilation of an algorithm in a high level language into machine dependent object code. There is, however, a major difference in the difficulty of the two tasks because of the rigidly two-dimensional nature of the silicon medium which contrasts with the freedom of access to most locations in the machine code. In order for one processing element to pass information or control flow to another, it must be physically connected to it by means of conductive paths which themselves occupy silicon area, and limit performance of the hardware because the transfer takes a time which depends on the connection length.

At the dimensions necessary for VLSI these effects become a major determi- nant of a system’s performance and cost (see Kinniment [4]) so that it is important that any silicon compiler manage connections effectively.

H. K.E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment 109

Autolayout is common in the gate array environment [2,6] where the ideal of abstracting out the physical details of the implementation have been most nearly achieved, but at the cost of poor utilisation of the medium. If sufficient space is allowed between cells to provide a high chance of success in the layout stage, a large chip size results. The design philosophy also prevents the efficient imple- mentation of structures which do not decompose into gate level primitives. Many of these routers use techniques in which the whole of the chip area is considered when the layout is evaluated. Since every connection interacts with every other, the computation required to find a good solution increases with chip size at a prohibitive rate.

An alternative approach [8,3] uses a floor planning stage, composition by abutment and a very considerable involvement in the layout on the part of the designer. This is undoubtedly a more elegant use of the medium but is not easily automated and therefore will be limited in application to systems where cost and performance are at a premium rather than a simple design process.

Our approach is to attempt to provide compilation facilities in which most of the layout details can be abstracted out, but allow some limited control of placement or design style where performance or area may be important.

2. Hierarchical router

The router used handles rectangular cells. Thus, the bounding box of a cell is the ‘smallest’ rectangle which contains all the shapes of this cell. The set of pins are points on the bounding box via which the inner system might be connected to its outside world. Since a hierarchical approach was adopted, certain restraints are imposed on the bounding box and the set of pins so that the cell can be used at a higher level of the design hierarchy as a ‘black box’ with regard to design rules. Possible and at the moment adopted restraints are the following:

(i) Since it is not known in advance which layer a pin might be connected externally, each pin must be able to ‘tolerate’ a possible contact. This means, no design rule inside the bounding box should be violated if a contact is required at a pin’s location.

(ii) All internal shapes (except connections to pins) must be separated by at least half the minimum distance from the edges of the bounding box required by the design rules for the worst case of adjacent shapes. This restraint allows cells to be abutted whenever possible. Overlapping of cells is not allowed.

The bounding box and the set of pins of a cell defines the ‘frame’ of that cell.

2. I. Input information

The router is expected to produce a cell (the resulting cell) from a certain number of smaller cells by interconnecting pins. Each smaller cell is, at a lower level, either an instance of a primitive cell or an instance of a composition of even smaller cells.

110 H.K.E. Liesenberg, D.J. Kinniment / A hierarchical i.e. design environment

At any given hierarchical level the router requires at least the following information:

(i) the frame descriptions of the cell types involved, (ii) instances of those cell types (internal cells) to be used,

(iii) the relative location of the pins of the cell to be produced, and (iv) description of disjoint sets of pins (called nets) to be interconnected. Information (i) is either obtainable from the component library or from a lower

level of the design hierarchy. The rest will be generated by the compiler or by the user if he (she) wishes to use the router as a stand-alone tool.

In a silicon compiler, the layout information would ideally be abstracted out by the use of an automatic placement algorithm to position internal cells. Currently an algorithm which produces adequate results in an acceptable time does not exist, and it is normal to call upon the designer to provide information concerning the organisation of the system important to good placement.

A requirement for absolute positioning information would be an overburden to the designer and it could even endanger a solution (e.g., lack of space for connections between cells). Thus, a ‘loose’ positioning (which cell is placed next to which) is more desirable, and provide guidance to the compiler allowing it to arrive to a solution close to the optimum without a large effort on the part of the user.

2.2. Positional expression

The developed router is a channel router. The loose placement and conse- quently the channels are supplied to the router via a positional expression. This kind of expression is a linear notation for the ‘channel intersection graphs’ used by Press and vancleemput [7].

Two binary and four unary operators are available to construct a positional expression. The operands are cell instances or subexpressions which already define a complete set of positional relations between the operands they contain. The unary operators represent the clockwise and anticlockwise 90 degree rotations and the reflections along the x- and the y-axis. An operand may be preceded by any number of unary operators. The binary operators ‘;’ and ‘v’ represent the relations ‘ to the left of and ‘below’ (horizontal and vertical neighbourhood), thus defining a horizontal or vertical channel running between the two operands.

An example of a simple language for stand alone use illustrating the descrip- tion of the composition of a block is shown in Fig. 1. Here the example is divided into 5 sections,

LD (design rules) POS (positional expression) CD (block definition) NET (net descriptions) ICD (component block definition)

In addition to the operators ; and . the unary operators > , A and < give mirroring, and + and - give rotation in the positional expression.

The capacity of a channel to hold connections is considered to be unlimited.

H.K.E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment 111

This implies that a solution is always possible. Whenever more space is needed the operands of the binary operator which defines the channel are moved apart in such a way that the required space is created and no positional relation is destroyed.

2.3. Algorithm

Since the input of the router is geometrical and structural top-down descrip- tion of a cell, a cell is described in terms of smaller cells which in turn are described in even smaller cells and/or are primitives. The router works in a bottom-up manner. The cells described at the lowest level are the first ones to be laid out. They can then be handled as frames at the next higher level as any

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Fig. 2. Channel graph induced from the positional expression of Fig. 1.

112 H.K.E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment

H.K. E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment 113

primitive cell because the dimensions of their bounding boxes are now defined. In order to implement a cell at a certain level in the hierarchy, the router

performs two distinct operations, called global and detailed routing. During the first stage, global routing, connections are assigned to a specific

channel. In order to do this a ‘channel’ graph is firstly derived from the positional expression. This channel graph is then used by a variant of Dijkstra’s [l] minimum path algorithm to generate ‘ tree’-like connections. For each net the router decides which channel to use for the connections. The connections result- ing during the first stage are called the main connections. The secondary connec- tions are those connections which link the pins on an instance to the appropriate main connection and they are determined during the second stage. Fig. 2 shows the channel graph derived from the positional expression of Fig. 1.

At the beginning of the second stage, detailed routing, the number of main

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114 H. K. E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment

connections in each channel are known. During this stage the steps performed are as follows: Step A. The cells are placed as near as possible so that the positional expression

is satisfied.

block multipller( n : integer) having (a, b : mcand CS> ) : product CN)

type ncand .= wireCn3 product :. = wireC2 * nl wire : .= pin

! Author: A. N.Qther Date of Design: 12th April 1983 ! Block design: Recursive multiplier for use in Signal Processing Applications

assert (2 <= n) & (n <= maxmultsire) L power2(n)

specification (true): multiplier ::= binarytintegerca) l integer(b))

within (10 + bitlength(binary(msx(a,b)))) case

(n > 2) : < ! The ntiltiplier is implemented by dividing the inputs a and b

! into a least significant half and a most significant half. ! Four n/2 multipliers are then used to multiply the least and ! most significant halves together, with the results being added ! in a :ull adder (except for the lowest n/2 and the highest n/2 bits) ! The result of the full adder is added with the highest n/2 bits ! of the multiplier stage to determine the carry, and the result is ! combaned with the low n/2 bits of the multiplier stage to form ! the result.

define lowbito( : pairCn1) : := XCII. s

! T:e type ‘pair’ is inherited from parallelfulladder ! and has components(s.c).

remainder(X : pdirEn3) : := CXCll. cI tail(X)> ! Tte ,C. .> operation is used to make a selection of bits.

multsize = n / 2

inherit carrypropagateadder~parallelfulladder from “Cdesignlibldrith.mdl”

instar?rt lowmult~midmultl~midmult2~highmult: multiplier(multrize) cp: carrypopagateadder(n) pa: parallelfulladder(n)

case (n = 1) : (pldce cp/pa/(lowmult~midmultlimidmult2i highmult)) (n > a) : {place cp/pa/(lowmultimidmultl~/~midmult2ihighmult~>

end

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midmult2, sdding(lasthdlf(lowmult),

firsthalf(highmult))) lowsult(firsthalf(d~~firsthrlQo~ highm~lt(ldsthalf(a), lastha-lP(b)) midmultl(firsthdlf(d), ldsthdlf(b)) midnult2(lestha1f(a~,firsthalf~b~~

make multiplier ::= product(firsthdlf(lowmult),

1 lowbit CP)

Fig. 5. Multiplier description.

H. K. E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment 115

Step B. At each channel its main connections are allocated in metal whenever possible.

Step C. If there is not enough space between the cells to accommodate the channels, then the resulting cell is expanded and the control returns to Step B.

Step D. At each channel pins are linked to the appropriate main connections. A secondary connection is first tried in the same layer as the pin is defined. If this is not possible, then polysilicon is used.

Step E. If Step D could not be carried out satisfactorily, then an expansion is performed tailored to the requirements of the connections. to be accom- modated and then the control is returned to Step B.

Step F. End of second stage. An expansion means the moving apart of cells so that spacing requirements

known at the time and the positional expression are satisfied. In order to allocate the main connections to a physical space in the channel, the main connections are ordered according to their length and then placed starting with the longest. By proceeding this way, the contours of a channel tend to become more irregular with respect to their width. These irregularities normally require less overall expansion since only some and not all of the cells adjacent to the channel in question have to be moved apart in order to accommodate the irregularities. The development of this process is shown in Fig. 3 as it proceeds towards the final layout.

Two nets are handled in a special way. They are the power supply (vdd) and ground (gnd) nets. Since they must be laid out in one and the same metal layer, a certain discipline has to be imposed. In order that there is a solution for these nets for the general case the router requires that each cell, after all concerning unary operators have been applied to it, must have at least one vdd pin on the south or east side and at least one gnd pin on the north or west side of its bounding box. During the first stage of the algorithm the main connections for the gnd net are assigned to channels in such a way that they converge to the north-west comer of the resulting cell’s bounding box and the main connections for the vdd net converge to the south-east corner. At the second stage the main connections of these special nets are always considered to be the shortest by the ordering

(n = 2) : C ! At thlo case a simple 2-bit multiplier block is used,

! whirh is implemented as a PLA.

inherit twobitmult from “Cdesignliblarith. mdl”

instance tbm : twobitmult

using tbm(r, b)

make multiplier : := tbm 1

end

Fig. 5 (continued).

116 H.K.E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment

procedure. This implies that they are always the outermost main connections of the channel. Thus, no secondary connection of those nets has to cross any main connection of another net.

3. Design language example

Our aim is to produce a structural description of an integrated circuit design written in a high level language, in which each part will be presented as a block and constructs will exist to provide the information necessary to compose these parts in a hierarchical manner. These constructs will include:

(a) Declaration of named points (pins) and structure of points available for external connection to a part.

(b) A means of associating such pins in groups (nets) implying electrical connection.

Fig. 6. Multiplier layout for n = 8.

H. K. E. Liesenberg, D.J. Kinnimenr / A hierarchical i.c. design environment 117

(c) Instantiation of parts previously defined as procedures. (d) Operators which allow the relative positioning of parts to be specified. Many of the usual high level language constructs will also exist allowing

selection, and recursion as well as hierarchy, and- a standard library of parts would be accessible as external procedures.

The main features of such a language have now been defined and in order to illustrate how it will interface to the autolayout algorithm described above it is necessary to give an example. Fig. 4 shows a diagram of a recursively defined n-bit multiplier whose components include two adders and four N/2 bit multi- pliers [9,10].

The multiplier is described by the text shown in Fig. 5 which contains specification, structure and relative placement.

Here primitive cells (inverter, shifter, PLA, multiplier, etc.) are produced by instancing blocks contained in the component library. The blocks may take parameters which affect its size (e.g., n-bit multiplier), topology (e.g., location of outputs relative to inputs) and/or performance (e.g., more silicon area to provide a faster result).

Declarations immediately below the heading describe the external pins needed in an n-bit multiplier, and at the bottom level the primitives in this case used are a 2 X 2 bit multiplier PLA, and two types of n-bit adders themselves produced from a number of single bit full adder PLAs. Nets are described by first defining functions of signal structures such as last half, remainder, etc. as selections of those structures, and then concatenating these selections together to provide the inputs to the appropriate instances. A connection is thus implied by selecting a signal and then using it as the actual parameter to an instance.

Relative placement is indicated in a similar way to the single example but with ‘/’ replacing e. Absolute pin positions and cell sizes for primitives are available from the library but since a bottom-up construction is performed by the layout system, the multiplier cell pin position and cell size must be calculated.

Fig. 6 shows the results of constructing this multiplier block with n = 8, and illustrates the need for different relative placements of the multiplier components at different levels in the hierarchy.

4. Conclusions

As the router was planned it was envisaged to be a fast tool where highly dense layouts were less important than ease of use. In time, and particularly if high volume production circuits are required, users may wish to have greater control on the final layout. Directives could probably be implemented which would allow a greater degree of control to the more experienced user without affecting too much the proposed objectives.

One example of a feature that could be implemented in form of a directive is what could be called the cell alignment feature. Let us suppose that two adjacent cells in a vertical channel have to be strongly interconnected on the sides facing

118 H. K. E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment

each other and that this could mainly be done by straight line connections. If now during an expansion process one cell is moved further than the other in the vertical direction, then straight line connections are not possible any longer and more space would be needed to lay out the interconnections. A directive saying that two adjacent cells should be treated by the expansion procedure as a unit (if one is dislocated, the other suffers the same dislocation) for a certain expansion could be useful for some regular structures.

In certain cases the standard solutions, particularly for the power supply and the ground nets, may not satisfy the user. Interactive capabilities would then be desirable for the users who are able to see more elegant solutions, and the router reduced to the role of verifying the integrity of the connections.

In its present form the router connects each net independently, which leads to a computational problem of some difficulty in routing a channel with many connections running through it. At high levels in the hierarchy, groups of connections are likely to run together as ‘busses’, all following parallel paths. Considerable savings can be made by routing a bus as a single unit, and this feature, together with the hierarchical nature of the router as a whole, allows the user to contemplate systems whose size would otherwise make autolayout an impracticable proposition.

The decision to design integrated circuits in a hierarchical way has led to the concepts of bounding boxes and pin tolerance to contacts which allow cells to be handled as black boxes at higher levels of the design hierarchy. These concepts and their implications had to be built into the router. Furthermore, the router has to accept as input a geometrical and structural top-down description of a cell. In order to always guarantee a solution certain restrictions are imposed on the power supply and the ground pins. Further use of the router may force a redefinition of these restrictions so that it adapts to new needs, but the concepts of hierarchy, minimum physical detail in specification, and ease of use whilst retaining overall control are unlikely to change.

Acknowledgment

The authors gratefully acknowledge their debt to the ideas which have come from many valuable discussions with colleagues in the VLSI group at the University of Newcastle upon Tyne, particularly Martin McLaughlan, Roy Campbell and Harry Whitfield.

References

[1] Dijkstra, E.W., A note to two problems in connexion with graphs, Numerische Muthematik 1 (1959) 269-271.

[2] Gray, J.P., Structured design and unstructured complementation or gate arrays revisited, Advanced Course on VLSI Architecture, University of Bristol, 1982.

H.K.E. Liesenberg, D.J. Kinniment / A hierarchical i.c. design environment 119

[3] Chesney, M., Design approach and associated tools, Advanced Course on VLSI Architecture, University of Bristol, 1982.

[4] Kinniment, D.J., VLSI and machine architecture, Aduanced Course on VLSI Architecture, University of Bristol, 1982.

[5] Mead, C. and L. Conway, Introduction lo VLSI Systems (Addison-Wesley, Reading, MA, 1980).

[6] Mole, G.F., I.A. Al-Shahib and D.J. Kinniment, A CAD verification system for ULA designs, Proc. IEE Con/. on Electronic Design Automation, University of Sussex, 1981.

[7] Preas, B.T. and W.M. vancleemput, Routing algorithms for hierarchical IC layout, Proc. 1979 Internal. Symp. on Circuits and Systems, Tokyo (1979) pp. 482-485.

[8] Trimberger. S., J.A. Rowson, CR. Lang and J.P. Gray, A structured design methodology and associated software tools, IEE Trans. Circuits and Systems CAS-28 (7) (1981).

[9] Yung, H.C. and C.R. Allen, Part I-VLSI implementation of an optimised hierarchical multiplier, Proc. IEE G. Circuits and Systems (1982) submitted.

[lo] Yung, H.C. and CR. Allen, Part II-Optimising analysis of a hierarchical multiplier algo- rithm, Proc. IEE G. Circuits and Systems (1982) submitted.