vlsi rec 7th sem vtu

P.A COLLEGE OF ENGINEERING (Affiliated to VTU , Recognized by AICTE ,NBA Accredited)

Near Mangalore University, mangalore-574153, Karnataka

LABORATORY CERTIFICATE

This is to certify that ............................................................ has satisfactorily completed the course of experiments in CAD for VLSI Laboratory practical prescribed by the Visveswaraih Technological University for VII sem. Of Electronics and Communication branch of Engineering in this College.

Register No: ................................. Signature of the Staff-in-charge

Signature of the H.O.D

Marks awarded in words

PART-ADIGITAL DESIGN

Part ASl. No.

Programs Page No.

Remarks

1 Timing verification with gate level simulation of an Inverter

2 Timing verification with gate level simulation of an Buffer

3 Timing verification with gate level simulation of an Transmission gate

4(a) Timing verification with gate level simulation of an AND gate

4(b) Timing verification with gate level simulation of an OR gate

4(c) Timing verification with gate level simulation of an NOR gate

4(d) Timing verification with gate level simulation of an NAND gate

4(e) Timing verification with gate level simulation of an XOR gate

4(f) Timing verification with gate level simulation of an XNOR gate

5(a) Timing verification with gate level simulation of an SR flipflop

5(b) Timing verification with gate level simulation of an MS flipflop

5(c) Timing verification with gate level simulation of an D flipflop

5(d) Timing verification with gate level simulation of an T flipflop

5(e) Timing verification with gate level simulation of an JK flipflop

6 Timing verification with gate level simulation of an Parallel Adder

7(a) Timing verification with gate level simulation of an Asynchronous Counter

7(b) Timing verification with gate level simulation of an synchronous Counter

8 Timing verification with gate level simulation of an Successive Approximation Register(SAR)

Part B

Sl No Program Page No.

Remarks

1 Design of an inverter using analog design flow

Experiment No. 1: An InverterSample Program (INVERTER)

Boot the system to Red Hat Linux Right click on the desktop Click on the open terminal tab To check whether the system is connected to server, the command used is

[root@local host ~]ping 192.168.80.1 {press enter}

Press ctrl+c to stop pinging To mount into the system:

mount –t nfs 192.168.80.1:/home/cadence /mnt/cadence {press inter}

To initialise your client, the command is :

/etc/init.d/nfs restart {press enter}

[root@local host ~]# will be displayed on the screen

Type [root@local host ~]# csh to go to C shell Then the # will be replaced by a $ symbol [root@local host ~]$ Type [root@local host ~]$ source cshrc If the above steps are done correctly a message will be displayed saying:

Welcome to cadence tool suite

To make a directory type mkdir ourlabs To go to the created directory type cd ourlabs [root@local host ourlabs]$ To see files within the directory type [root@local hostourlabs]$ ls {press enter}

Note 1: To move from the current directory to previous directory type cd . . {press enter}

Note 2: To move from the current directory to root directory typecd<SPACE> {press enter}

To create a directory for the inverter program type:

[root@local host ourlabs]$ mkdir invrtr {press enter}

The above path will change to :- [root@local host invrtr]$ If we need to check the path type : [root@local host invrtr]$ pwd {press enter} Steps to create a file in Verilog : [root@local host invrtr]$ vi invertr.v {avoid keywords} The above command will open a window where the module program can be written

The writing of the program can be done after activating the insert mode by pressing ‘ i ’ in the program window

Module Program:

Module inv(a,y);input a;output y;assign y= ~a;endmodule

To save and quit the module proram press ESC and type :wq To quit without saving press ESC and type :q! Test bench file is used for simulation To create a test bench file type [root@local host invrtr]$ vi invertr_test.v The above command will open window where the test bench program can be

written The writing of the program can be done after activating the insert mode by

pressing ‘ i ’ in the program window Test Bench Program:

moduleinv_test;reg a;wire y;invabc(a,y);initialbegin$monitor($time,"y=%d",y);a=1'b0;#10 a=1'b1;#10 a=1'b0;#10 $finish;endendmodule

To save and quit the module proram press ESC and type :wq To quit without saving press ESC and type :q! Compilation of the moduke and the test bench programs can be done using the

commands ncvlog<filename of the module/testbench program>.v -mess

ncvlog invertr.v -mess {press enter}ncvlog invertr_test.v -mess {press enter}

To elaborate the program to the libraries

ncelab<module name of test bench program> -mess

ncelab inv_test –mess {press enter}

To launch the simulation window the command is Nclaunch {press enter}

Simulation window:

In the simulation window set the directory as root Delete files from worklib Select invrtr(your directory) on the lower side of the window Click on invertr.v and click on VLOG icon on the nclaunch window Click on invertr_test.v and click on VLOG icon on the nclaunch window

Then within the worklib we can see two files inv inv_test Click on inv and select the launch icon on the top of the nclaunch window Click on inv_test and select the launch icon on the top of the nclaunch window Then click on the snapshots folder which will contain the bellow two files

Worklib.invertr.module Worklib.invertr_test.module

Click on the Worklib.invertr_test.module and select the Launch Simulator with current selection iconon the nclaunch window

After the simulation go back to the directory inverter [root@local host invrtr]$

Create directory rclabs using the command mkdir rclabs Open the directory rclabs using the command cd rclabs Go to the root directory of the computer Copy the contents of rclabs from the folder cadence digital labs to the newly

created rclabs folder in your directory. Copy the module program to the rtl folder in your directory

Enter the rclabs directorycd rclabs

Enter the rtl directorycd rtl

List the files within the directory and check whether the files have been copied properly, if not repeat the copying procedure again ls

Return to the rclabs directory usingcd .. Goto the work directory by cd work

Create a log file for the inverter file using the command :rc -gui -logfile intr.log {any name}

When the intr log file is executed, a new screen will open displaying rc:\> on the screen

The below given command is used to generate the template script from the compiler by entering:

rc:\>write_template -outfiletemplate.tcl rc:\>set_attrhdl_search_path {../rtl} / rc:\>set_attrlib_search_path {../library} / rc:\>set_attrscript_search_path {../tcl} / rc:\> include setup.g The reading of the libraries can be done by: rc:\>set_att library$LIBRARY

Reading and elaborating is done by the commands :

rc:\>read_hdl<filename of module program>.vrc:\>read_hdlinvertr.v

rc:\>elaborate Maximize the Cadence window and observe the circuit diagram

For Synthesis synthesize -to_mapped -eff medium -no_incr Synthesis succeeded

Program No.2 :A Buffer

Module Program

module buff(a,c,y);input a;output y;inout c;assign c=~a;assign y=~c;endmodule

Testbench Program

module buff_test;reg a;wire y;wire c;buff abc(a,c,y);initialbegin$monitor($time,"c=%d",c);$monitor($time,"y=%d",y);a=1'b0;#10 a=1'b1;#10 a=1'b0;#10 $finish;end endmodule

Program No.3 : Transmission Gate

Module Program

module trsgate(x,y,s);input x,s;output y;reg y;always@(x or s)begin if(s==1)y=x;else y=1'bz;endendmodule

Testbench Program

module trsgate_test;reg x,s;wire y;trsgate dum (x,y,s);initial beginx=1'b1;#2 s=1'b1;#2 x=1'b0;#2 s=1'b0;#2 x=1'b1;#2 $finish;endendmodule

Program No. 4(a) :And Gate

Module Program

module andgate(a,b,c);input a,b;output c;assign c=a&b;endmodule

Testbench Program

module andgate_test;reg a,b;wire c;andgate xyz(a,b,c);initialbegin$monitor($time,"c=%d",c);a=1'b0;b=1'b0;#10 a=1'b1;b=1'b0;#10 a=1'b0;b=1'b1;#10 a=1'b1;b=1'b1;#10 $finish;endendmodule

Program No. 4(b) :Or Gate

Module Program

module orgate(a,b,y); input a,b; output y; reg y; always@(a|b) begin y=a|b; endendmodule

Testbench Program

module orgate_test; reg a,b; wire y; orgate dum (a,b,y); initial begin a=1'b0; b=1'b0;#2 b=1'b1;#4 a=1'b1;#6 b=1'b0;endendmodule

Program No. 4(c) :Nor Gate

Module Program

module norgate(a,b,y); input a,b; output y;assign y=~(a|b);endmodule

Testbench Program

module norgate_test;reg a,b;wire y;norgate mod(a,b,y);initialbegin$monitor ($time,"y=%d",y);a=1'b0;b=1'b0;#10 a=1'b1;#10 b=1'b1;#10 a=1'b0;#10 $finish;endendmodule

Program No. 4(d) :Nand Gate

Module Program

module nandgate(a,b,c);input a,b;output c;assign c=~(a&b);endmodule

Testbench Program

module nandgate_test;reg a,b;wire c;nandgate xyz(a,b,c);initialbegin$monitor($time,"c=%d",c);a=1'b0;b=1'b0;#10 a=1'b1;b=1'b0;#10 a=1'b0;b=1'b1;#10 a=1'b1;b=1'b1;#10 $finish;endendmodule

Program No. 4(e) :Xor Gate

Module Program

module xorgate(a,b,y);

input a,b; output y; reg y;always@(a or b) begin y=(a^b); endendmodule

Testbench Program

module xorgate_test;reg a,b;wire y;xorgate mod (a,b,y);initialbegin

a=1'b0;b=1'b0;#2 a=1'b1;#4 b=1'b1;#6 a=1'b0;endendmodule

Program No. 4(f) :Xnor GateModule Program

module xnorgate(a,b,y);

input a,b; output y; reg y;always@(a or b) begin y=~(a^b); endendmodule

Testbench Program

module xnorgate_test;reg a,b;wire y;xnorgate mod (a,b,y);initialbegin

a=1'b0;b=1'b0;#2 a=1'b1;#4 b=1'b1;#6 a=1'b0;endendmodule

Program No. 5(a) :SR FlipflopModule Program

module srff(s,r,clk,q,qb);input s,r,clk;output q,qb;reg q,qb;reg [1:0]jk;always@(posedge(clk))beginjk={s,r};case(jk)2'b00: q=q;2'b01: q=0;2'b10: q=1;2'b11: q=1'bZ;default;endcaseqb=~q;endendmodule

Testbench Program

module srff_test;reg s,r,clk;wire q,qb;srff dum (s,r,clk,q,qb);initialclk=0;always#1 clk=~clk;initialbegins=1'b0;r=1'b1;#2 r=1'b0;#2 s=1'b1;#2 r=1'b1;#2 $finish;endendmodule

Program No. 5(b) :MS FlipflopModule Program

module msff(j,k,clk,q,qb);input j,k,clk;output q,qb;reg q,qb,tg;initialbeginq=1'b0;qb=1'b1;endalways@(clk)beginif(clk)beginif(j==1'b0 && k==1'b0) tg=tg;else if(j==1'b0 && k==1'b1) tg=1'b0;else if(j==1'b0 && k==1'b0) tg=1'b1;else if(j==1'b1 && k==1'b1) tg=~tg;endif(!clk)beginq=tg;qb=~tg;endendendmodule

Testbench Program

module msff_test;reg j,k,clk;wire q,qb;msff dum (j,k,clk,q,qb);initialclk=1'b0;always#100 clk=~clk;initialbeginj=1'b0; k=1'b1;#300 k=1'b0;#300 j=1'b1;#300 k=1'b1;#300 $finish;endendmodule

Program No. 5(c) :D FlipflopModule Program

module dflif(d,clk,q,qb);input clk,d;output q,qb;reg q,qb;always@(posedge(clk))begin if(d==1) q=1;else q=0;qb=~q;endendmodule

Testbench Program

module dflif_test;reg clk,d;wire q,qb;dflif dum (d,clk,q,qb);initial clk=0;always#100 clk=~clk;initialbegind=1'b0;#100 d=1;#200 d=0;#100 $finish;end endmodule

+

Program No. 5(d) :T FlipflopModule Program

module tff(t,clk,q,qb);input t,clk;output q,qb;reg q,qb;always@(posedge(clk))beginq=0;case(t)1'b0:q=q;1'b1:q=~q;default;endcaseqb=~q;endendmodule

Testbench Program

module tff_test;reg t,clk;wire q,qb;tff dum (t,clk,q,qb);initialclk=0;always#2 clk=~clk;initialbegint=0;#4 t=1;#6 $finish;endendmodule

Program No. 5(e) :JK FlipflopModule Program

module jkffgate(j,k,clk,q,qb);input j,k,clk;output q,qb;reg q,qb;reg [1:0]jk;always@(posedge(clk))beginjk={j,k};case(jk)2'b00: q=q;2'b01: q=0;2'b10: q=1;2'b11: q=qb;default;endcaseqb=~q;endendmodule

Testbench Program

module jkffgate_test;reg j,k,clk;wire q,qb;jkffgate dum (j,k,clk,q,qb);initialclk=0;always#1 clk=~clk;initialbeginj=1'b0;k=1'b0;#2 k=1'b1;#2 j=1'b1;#2 k=1'b0;#2 $finish;endendmodule

Program No.6 :Parellel AdderModule Program

module padd(cin,x,y,sum,cout);input cin;input [3:0]x,y;output [3:0]sum;output cout;fulladd g0(cin,x[0],y[0],sum[0],c0);fulladd g1(c0,x[1],y[1],sum[1],c1);fulladd g2(c1,x[2],y[2],sum[2],c2);fulladd g3(c2,x[3],y[3],sum[3],cout);endmodulemodule fulladd(cin,x,y,sum,cout);input cin,x,y;output sum,cout;assign sum=x^y^cin;assign cout=((x&y)||(x&cin)||(y&cin));endmodule

Testbench Program

module padd_test;reg [3:0]x,y;reg cin;wire [3:0]sum;wire cout;padd abc(cin,x,y,sum,cout);initial begin$monitor($time,"sum=%d",sum);x=4'b0000;y=4'b0000;cin=1'b0;#20 x=4'b1111;y=4'b1010;#40 x=4'b1011;y=4'b0110;#40 x=4'b1111;y=4'b1111;#50 $finish;endendmodule

Program No.7(a) : Asynchronous CounterModule Program

module acount(cnt,e,q);input cnt,e;output [3:0]q;wire q1,q2,q3,q4;tff aaa(e,cnt,q[0],q1);tff bbb(e,q1,q[1],q2);tff ccc(e,q2,q[2],q3);tff ddd(e,q3,q[3],q4);endmodulemodule tff(t,clk,q,qb);input t,clk;output q,qb;reg q,qb;initialbeginq=1'b0;qb=1'b1;endalways@(posedge clk)beginif(t==0)q=q;elseq=~q;qb=~q;endendmodule

Testbench Program

module asyncount_test;reg cnt,e;wire [3:0]q;acount zzz(cnt,e,q);initialbegincnt=0;e=1;endalways #100 cnt=~cnt;endmodule

Program No.7(b) :Synchronous CounterModule Program

module sync(cnt,e,q); module and1(a,b,c); input cnt,e; input a,b;output [3:0]q; output c;wire e1,e2,e3; assign c=a&b;tff aaa(e,cnt,q[0]); endmoduleand1 go(q[0],e,e1); tff bbb(e1,cnt,q[1]); module and2(d,e,f,g);and2 g1(q[1],q[0],e,e2); input d,e,f; tff ccc(e2,cnt,q[2]); output g;and3 g2(q[2],q[1],q[0],e,e3); assign g=d&e&f;tff ddd(e3,cnt,q[3]); endmoduleendmodule module tff(t,clk,q); module and3(p,q,r,s,t);input t,clk; input p,q,r,s;output q; output t;reg q; assign t=p&q&r&s;initial endmoduleq=1'b0; always@(posedge clk)beginif(t==0)q=q;elseq=~q;endendmodule

Testbench Program

module asyncount_test;reg cnt,e;wire [3:0]q;sync zzz(cnt,e,q);initialbegincnt=0;e=1;endalways #100 cnt=~cnt;endmodule

Program No.8 :SARModule Program

module sareg(l,clk,q);input l,clk;output [3:0]q;reg [3:0]q;integer j;initialbeginq=4'b1000;j=3;endalways@(clk)beginif(l) q[j]=1;else q[j]=0;j=j-1;q[j]=1;endendmodule

Testbench program

module sareg_test;reg l,clk;wire [3:0]q;sareg dum(l,clk,q);initialclk=1'b0;always#10 clk=~clk;initialbeginl=1'b0;#10 l=1'b1;#10 l=1'b0;#10 l=1'b1;#10 $finish;endendmodule

Credits:Faculty In Charge:

Dr. Jose Alex Mathew

Prof. Abdulla Gubbi

Mr. Mohd. Jakir

Typeset and Editing :

Digital Design

Mr. Sagar S Poojary [ 7th ec 2 ]

Mr. Tushar Shetty [ 7th ec 2 ]

Mr. Krishnaraj Mayya [ 7th ec 1 ]

Analog Design

Mr. Shabareesh K Bhut [ 7th ec 2 ]

Mr. Ragavendra K K [ 7th ec 2 ]

*Special thanks to our lab assistant Mr. Yaseen*