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Q8UPSAMPLER
DATASHEET
Allrightsreserved.NopartofthisworkcoveredbytheengineeredSAcopyrightmaybereproducedorcopiedinanyform or by anymeans (graphic, electronic ormechanical, including photocopying, recording, taping or informationretrievalsystems)withoutthewrittenpermissionofengineeredSA.Copyright©engineeredSAAvenuedesSports28,1400Yverdon-les-BainsSwitzerland+41215433966 DSP-Q8-DSinfo@engineered.ch/www.engineered.ch doc.v.100e/rev.Dec-16
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TableofcontentsTableofcontents...........................................................................................................................................................................................3I. AboutThisDatasheet.................................................................................................................................................................5II. CompanyInformation................................................................................................................................................................5III. Notice................................................................................................................................................................................................5IV. ProductWarningsandRestrictions.....................................................................................................................................5V. RepairandMaintenance...........................................................................................................................................................6VI. DocumentationReleaseNotice..............................................................................................................................................6
1 Introduction.........................................................................................................................................................................................71.1 Highlights........................................................................................................................................................................................71.2 FunctionalBlockDiagram........................................................................................................................................................71.3 SonicUpsampling........................................................................................................................................................................81.4 DSDtoPCMConversion............................................................................................................................................................81.5 DSF™Filtering...............................................................................................................................................................................8
2 CharacteristicsandSpecifications..............................................................................................................................................92.1 ElectrostaticDischargeWarning..........................................................................................................................................92.2 RecommendedOperatingConditions.................................................................................................................................92.3 AbsoluteMaximumRatings....................................................................................................................................................92.4 ElectricalSpecifications............................................................................................................................................................92.5 DigitalAudioSpecifications.................................................................................................................................................102.6 Pinassignments.........................................................................................................................................................................102.7 HousingDimensions................................................................................................................................................................112.8 Pindescriptions.........................................................................................................................................................................12
3 InterfacingandOperation...........................................................................................................................................................133.1 GeneralDescription.................................................................................................................................................................133.2 TypicalConnections................................................................................................................................................................143.3 InterfacingtoDigitalAudioReceivers.............................................................................................................................143.4 InterfacingQ8outputs............................................................................................................................................................153.5 ReferenceMasterClock..........................................................................................................................................................153.6 ResetandPowerOn................................................................................................................................................................163.7 AudioSerialInputPort(RX)................................................................................................................................................163.8 TX1AudioOutputPort...........................................................................................................................................................173.9 TX0AudioOutputPort...........................................................................................................................................................173.10 DataResolutionandDither..................................................................................................................................................183.11 IncomingSamplingRateandLocking..............................................................................................................................183.12 Muting............................................................................................................................................................................................193.13 PhaseInversion.........................................................................................................................................................................193.14 StereoDSDtoPCMConversion..........................................................................................................................................193.15 DataValidflag(DSP_MODE3).............................................................................................................................................193.16 SerialPortInterface(SPIPort)...........................................................................................................................................20
4 HardwareMode...............................................................................................................................................................................224.1 GeneralDescription.................................................................................................................................................................224.2 HardwareConfiguration........................................................................................................................................................22
5 SoftwareMode.................................................................................................................................................................................235.1 GeneralDescription.................................................................................................................................................................235.2 InputStatusRegister...............................................................................................................................................................235.3 TX0OutputControlRegister...............................................................................................................................................245.4 ProcessControlRegister.......................................................................................................................................................245.5 SoftwareRevisionRegister..................................................................................................................................................255.6 ProductIDRegister..................................................................................................................................................................25
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5.7 ProductSub-IDRegister........................................................................................................................................................256 Relatedproducts.............................................................................................................................................................................266.1 BackwardCompatibility........................................................................................................................................................266.2 Customapplications................................................................................................................................................................26
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Preface
I. AboutThisDatasheetThisdocumentprovidestheinformationneededtodesignandintegratetheQ8UpsamplerModuleintoyourproduct.Formore information,pleaserefertotheproductdescriptionavailable fromtheengineeredWebsiteat:www.engineered.ch
II. CompanyInformationengineeredSAAvenuedesSports281400Yverdon-les-BainsSwitzerland+41215343966info@engineered.ch/www.engineered.ch
III. NoticeengineeredSAprovidestheenclosedproduct(s)underthefollowingconditions:Theuserassumesallresponsibilityandliabilityforproperandsafehandlingofthegoods.Further,theuserindemnifiesengineeredfromallclaimsarisingfromthehandlingoruseofthegoods.Informationprovidedbyengineeredisbelievedtobeaccurateandreliable.However,noresponsibilityisassumedbyengineeredforitsuse.Pleasebeawarethattheproductsreceivedmaynotberegulatorycompliantoragencycertified.EXCEPTTOTHEEXTENTOFTHEINDEMNITYSETFORTHABOVE,NEITHERPARTYSHALLBELIABLETOTHEOTHERFOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. engineered currently deals with avariety of customers for products, and therefore our arrangement with the user is NOT EXCLUSIVE.engineered assumes NO LIABILITY FOR APPLICATIONS ASSISTANCE, CUSTOMER PRODUCT DESIGN, SOFTWAREPERFORMANCE,ORINFRINGEMENTOFPATENTSORSERVICESDESCRIBEDHEREIN.Pleasereadthedatasheetand,specifically,the“ProductWarningsandRestrictions”noticeinthedatasheetprior to handling the product. This notice contains important safety information. Persons handling theproduct must have electronics training and observe good laboratory practice standards. No license isgrantedunderanypatentrightorotherintellectualpropertyrightofengineeredcoveringorrelatingtoanymachine,process,orcombinationinwhichsuchengineeredproductsorservicesmightbeorareused.
IV. ProductWarningsandRestrictionsIt is important to operate this product within the specified input and output range described in thisdocument.Exceedingthespecifiedinputrangemaycauseunexpectedoperationand/orirreversibledamagetotheproduct.If you have questions regarding the input range, please contact engineered customer support prior toconnectingthepowersupply.Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperation and/or possible permanent damage to the product. Please consult the datasheet prior toconnecting any load. If you have doubts concerning the load specification, please contact engineeredcustomersupport.
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V. RepairandMaintenanceRoutinemaintenance is not required. This product is warranted to be free of any defect with respect toperformance,quality,reliabilityandworkmanshipforaperiodofSIX(6)monthsfromthedateofshipmentfromengineered.In the event your product proves to be defective in anyway during thiswarranty period,wewill gladlyrepairorreplacethispieceofequipmentwithaunitofequalorsuperiorperformancecharacteristics.Shouldyoufindthisproducthasfailedafteryourwarrantyperiodhasexpired,wewillrepairyourdefectivepieceofequipmentaslongassuitablereplacementcomponentsareavailable.You,theowner,willbearanylabourand/orcomponentcostsincurredintherepairorrefurbishmentofsaidequipment,beyondtheSIX(6)monthswarrantyperiod.Anyattempttorepairthisproductbyanyoneduringthisperiodotherthanbyengineeredoranyauthorized3rdpartywillvoidyourwarranty.engineered reserves the right to assess anymodifications or repairsmade by you and decide if they fallwithin warranty limitations, should you decide to return your product for repair. In no event shallengineered be liable for direct, indirect, special, incidental, or consequential damages (including loss andprofits)incurredbytheuseofthisproduct.Impliedwarrantiesareexpresslylimitedtothedurationofthiswarranty.
VI. DocumentationReleaseNoticeThisdocumentisunderrevisioncontrolandupdateswillonlybeissuedasareplacementdocumentwithanewversionnumber.Productspecificationsaresubjecttochangewithoutnotice.
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1 Introduction
1.1 HighlightsTheQ8Moduleisanultra-highperformance2-channelUpsamplerdesignedforhighend,proandconsumeraudioapplications.KeyfeaturesfortheQ8Moduleinclude:
• Superiorperformanceasynchronous24-bit/384kHzupsamplingbasedonanenhancedversionofthepatentedQ5technology.
• IntegrateswithDSS™synchronizationtechnologyforefficientjitterrejection.• 384kHzupsampleddigitaloutputfordriving2DAC'sindualmonomode.• Additionaldirectdownsampled1x/2x/4xFSoutputport.• DSDtoPCMconversion.• DoPdecoding.• Automaticinputsamplingfrequencysensing.• Supportssampleratesinputfrom44.1kHzto384kHzandwordlengthfrom16-to24-bit.• Inputformat:I2Sor2-channelDSD.• Standalonehardwareandconfigurablesoftwaremodesavailable.• ParametersavailablethroughSPIaccess.• CompatiblewithQ5Module.
1.2 FunctionalBlockDiagramTheQ8Moduleintegratesfourkeytechnologies:SonicUpsampling(enhancedversionofthepatentedQ5),DSS™SynchronizationandDSF™filteringtodeliverahighlyintegratedasynchronousupsampleranddigitalsynchronizerwithbestlow-levelsignal.ThemodulefeaturesasingleaudioinputportcapableofsupportingPCM data up to 24-bit from frequencies up to 384kHz or stereo DSD64 (2.8224MHz) and DSD128(5.6448MHz).Ineithercase,theDSDsignalorthedirectPCMinputareupsampledtoacommon8xFSPCMformat.
Figure1-1-functionalblockdiagram
PCM/DSD audio input
control interface
reclocking&
upsampling
direct down-
sampled output
digital output at
8xFS
Q8 Module
I2S / DSD
SPI+GPIOs
Low Jitter AudioMaster Clock
Left ch.
Right ch.
Digital Audio
Source
Micro controller
Digital transmitter
DAC& analog
filter
24.576MHz oscillator
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1.3 SonicUpsamplingTheQ8UpsamplerModuleincludesseveralproprietarytechnologies:adaptivetimefiltering,data-to-systemsynchronization,andaninnovativevirtualtime-domainmodel.Thesetechnologieseffectivelyreducenoiseartefactscausedbyimperfectdigitalsystemsandallowthedigitalsignaltocloserrepresentthetrueanalogsoundofthestudiomasteredaudiodata.Adaptivetimefilteringallowsthesystemtoadapttosmall fluctuations inthesystemsaudiomasterclock.Themasterclock is theheartofanydigitalaudiosystem,howeverasallcomponentsthatareconstructedfrom physical materials, they will at some point in time deviate from their ideal generalized behaviourcausing, in this case variation in frequency and system jitter in this important internal timing reference.Typically,thesevariationswillnotbecorrectedfor,howeverinQ8enableddevicesthesystemautomaticallyadaptstothesesmallfluctuationsresultinginperfect“glitch”freeanalogsoundevenafterendlesshoursofcontinuousplayback.Data-to-Systemsynchronizationallowsany incomingaudiostreamtoberesynchronizedandretimed toalocalhighqualityclock.Byusingastableclockreference,thenegativeeffectsofinter-componentjittercanbe minimized. When converting the digital audio to an analog signal through high performance D/Aconverters, this reduction in jitter has enormous benefits in the level of detail and clarity in thereconstructedanalogsound.Combingthisprocesswithavirtualtimedomainmodelthatusesanadvancedcubic interpolation algorithm to resample the incoming audio data, timing errors in this signal can becompensatedforatamazinglevelsofaccuracy.Theresultisatighterandmorefocusedbass,anincreasedstereoimaging,aswellasclarityandseparationforallmusicalinstrumentsandvoices.
1.4 DSDtoPCMConversionTheQ8ModulecanuseaDirectStreamDigital(DSD)audiostreamat2.8224MHzor3.072MHz(64x44.1kHzor48kHz),5.6448MHzor6.144MHz(128x44.1kHzor48kHz)asinputaudiosource.ADSDstreamisaone-bitdelta-sigmamodulateddigitalaudiosignalsampledinasequenceofveryhighfrequency.Thisformatisused to store audio on Super Audio Compact Disc (SACD) and is now popular on high-resolution musicavailable for download. Audio processing of the input DSD stream inside the Q8Module is done by firstconverting the DSD data to PCM format thanks to the DSF™ Filtering, then using standard PCM audioprocessing techniques. The audio channel configuration supported by the Q5Module is 2-channel stereoDSD.For seamless audio format integration, DoP (DSD over PCM) encoded input streams are automaticallydetected and decoded. Detection is based on the specific DoP marker code. Stereo DSD data are thenextractedfromthepseudoPCMdatastreamandsenttotheDSDtoPCMconverterunit.
1.5 DSF™FilteringDue to its veryhigh sampling rate (2.8224MHz, 3.072MHz, 5.6448MHzor 6.144MHz) andone-bit nature,DSDisincompatiblewithalreadyimplementedsignalprocessingfunctionstargetingstandardPCMdata.TheDirectStreamFiltering (DSF™Filtering)algorithmconvertsDSDstreams toPCMup to8xFSwith superbquality.TheQ8ModuleintegratesthisfeatureinordertosupplyveryhighaudioqualityfromaDSD64orDSD128audiostreamandthereforesignificantlyenhancesperformanceofanyaudioapplicationsusingthissingle-bitencoding.
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2 CharacteristicsandSpecifications
2.1 ElectrostaticDischargeWarningMany of the components in this product are subject to be damaged by electrostatic discharge (ESD).Customers are advised to observe proper ESD precautions when unpacking and handling the board,includingtheuseofagroundedwriststrapatanapprovedESDworkstation.Caution:FailuretoobserveESDhandlingproceduresmayresultindamagetothedevice.
2.2 RecommendedOperatingConditionsTable2-1indicatestherecommendedconditionsunderwhichtheproductshouldrunproperly.
Parameter RecommendConditionPowersupplyvoltage 3.30VDC
Inputsignalvoltage VIL(min/max):0.0V/0.5V VIH(min/max):2.4V/3.3V
Operatingfree-airtemperature TA(min/max):0°C/60°C
Table2-1-recommendedoperatingconditions
2.3 AbsoluteMaximumRatingsTheusershouldbeawareoftheabsolutemaximumoperatingconditionsfortheQ8Module.Stressbeyondmaximumratingsmaycausepermanentdamagetothedevice.Table2-2summarizesthecriticaldatapoints.
Parameter Min. Max.Powersupplyvoltage -0.30V 3.60V
Inputsignalvoltage -0.30V 3.60V
Inputcurrent(anypinsexceptssupplies) -10mA +10mA
Outputsignalloadimpedance 180Ω -
Operatingfree-airtemperature -20°C 60°C
Storagetemperature -20°C 85°C
Table2-2-absolutemaximumratings
2.4 ElectricalSpecificationsParameter Min. Typ. Max.
DCsupplyvoltage 3.10V 3.30V 3.60V
DCsupplycurrent 350mA 500mA
InputlogiclevelhighVIH 2.4V
InputlogiclevellowVIL 0.5V
Inputlogiccurrent -0.5mA 0.5mA
OutputlogiclevelhighVIH VDD-0.6V 3.10V VDD
OutputlogiclevellowVIL 0 0.2V 0.4V
Outputlogiccurrent -15mA 15mA
Table2-3-electricalspecifications
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2.5 DigitalAudioSpecificationsParameter Min. Typ. Max.
Masterclockinputfrequency 24.5760MHz
PCMinputresolution 16-bit 24-bit
PCMinputsamplerate 44.1kHz 384kHz
PCMinputformat I2S
DSDinputfrequency 2.8224MHz 6.144MHz
DSDinputformat 2-channel1-bitDSD(directstreamdigital)
TX0PCMoutputformat I2S
TX0PCMoutputclocking master
TX0PCMoutputsamplerate 1xFS(48kHz)/2xFS(96kHz)/4xFS(192kHz)
TX1PCMoutputformat mono-framedleft-justifiedmode/mono-framedright-justifiedmode
TX1PCMoutputclocking master
TX1PCMoutputsamplerate 384kHz
Dynamicrange 24-bit
THD+N -140dB -144dB -147dB
Table2-4–digitalaudiospecifications
2.6 Pinassignments
Figure2-1-pinassignments
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2.7 HousingDimensions
Figure2-2-housingdimensions
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2.8 PindescriptionsPin# Name Type Description1 VDD Power DigitalcoreandI/Opowersupply:+3.30V
2 VDD Power DigitalcoreandI/Opowersupply:+3.30V
3 RESET Input Reset–activelow,internalpull-upresistor4 SPI_CS Input Reset–activelow,internalpull-upresistor5 SPI_SCK Input ControlportSPIclock
6 SPI_MOSI Input ControlportSPIdatainput
7 SPI_MISO Output ControlportSPIdataoutput,open-collector,internalpull-upresistor
8 DGND Ground DigitalcoreandI/Oground
9 CLKIN Input Masterclockinput
10 NC Donotconnect Cutpin
11 DSP_MODE0 InputTX1outputportdataformatLow:mono-framedleftjustifiedoutputmodeHigh:mono-framedrightjustifiedoutputmode
12 DSP_MODE1 InputDSD/PCMinputformatLow:PCMorDoPinputstreamHigh:nativeDSDinputstream
13 DSP_MODE2 Input Unused–connecttoGND
14 DSP_MODE3 InputDataValidflag–activelowLow:incomingaudiodatastreamisvalidHigh:incomingaudiodatastreamisnotvalid,outputismuted
15 NC Donotconnect Reservedforfactoryuse
16 DGND Ground DigitalcoreandI/Oground
17 RX_WDCLK Input PCMserialaudioinputWordClockDonotconnectinDSDmode18 RX_BITCLK Input PCM/DSDserialaudioinputBitClock
19 RX_SDATA0 Input PCMserialaudioinputstereodataDSDserialaudioinputleftchanneldata20 RX_SDATA1 Input DSDserialaudioinputrightchanneldata
21 DNGD Ground DigitalcoreandI/Oground
22 TX1_FSYNC Input/Output SerialaudiooutputFrameSyncforTX1_SDATA0andTX1_SDATA1
23 TX1_BITCLK Input/Output SerialaudiooutputBitClockforTX1_SDATA0andTX1_SDATA1
24 TX1_SDATA0 Output SerialaudiooutputLeftUpsampledleftmonochannelPCMaudiodataserialoutput
25 TX1_SDATA1 Output SerialaudiooutputRightUpsampledrightmonochannelPCMaudiodataserialoutput26 DNGD Ground DigitalcoreandI/Oground
27 TX0_FSYNC Input/Output SerialaudiooutputframeSyncforTX0_SDATA0andTX0_SDATA1
28 TX0_BITCLK Input/Output SerialaudiooutputBitClockforTX0_SDATA0andTX0_SDATA1
29 TX0_SDATA0 Output SerialaudiooutputdataStereoDirectdown-sampledstereochannelPCMaudiodataserialoutputpin30 TX0_SDATA1 Output Serialaudiooutputdata-reserved
31 DGND Ground DigitalcoreandI/Oground
32 IRQ Output Controlportinterruptrequest–activelow
Table2-5–pindescriptions
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3 InterfacingandOperation
3.1 GeneralDescriptionThe Q8 Module is a 2-channel, asynchronous digital data stream upsampler with D/A conversion errorminimizationandmulti-DACdatadistribution.OperationatPCMinputsamplingfrequenciesfrom44.1kHzto384kHz,DSDat2.8224MHzor5.6448MHzandoutput at 384kHzare supported.Best-in-classdynamicrangeandTHD+Nareachievedbyemployingan innovativeupsamplingkernelwithbetter than147dBofimage rejection. A direct down-sampling option allows for dual digital output ports driven at differentsamplingfrequencies.TheaudioinputportsupportstheI2Sstandardandthe2-channelDSDaudiodataformatwhiletheoutputportisconfiguredonmono-framedaudiodataformat.Inputwordlengthsfrom16-to24-bitaresupported.Input ports are operated in Slavemode, deriving their word and bit clocks from external input devices.Output ports are operated in Master mode allowing the incoming data stream to be re-clocked andsynchronizedaroundasinglehighqualitymasterclock, referred toasDSSsynchronization. In theMastermodeoftheoutputports,theFSYNCandBITCLKclocksarederivedfromthesystemmasterclockCLKIN.TheQ8Moduleincludesafour-wireSPIport,whichisusedtoaccesson-chipcontrolandstatusregistersinSoftware mode. The SPI port facilitates interfacing to microprocessors or digital signal processors thatsupportsynchronousserialperipherals. InHardwaremode,dedicatedcontrol flagsareprovided forbasicfunctions.Thesepinscanbehard-wiredordrivenbylogicorhostcontrol.Inadditiontothenormalcontrolinterfaces,theQ8Moduleprovidesanartefact-freesoftmutefunctioninsoftwaremodeaswellasautomaticinputfrequencysensing.
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3.2 TypicalConnectionsTheQ8ModulecanbeoperatedinhardwaremodewherebytheSPIport(*)isnotneededtoconfigurethemodulebutrathertheFLAGpins.PleasenotethatsomefeaturesareaccessedonlybytheSPIportthereforehardwaremode offers reduced functionalities. Figure 3-1 illustrates typical connexionswith digital audioreceiver,ahostMC,DAC’sanddigitaltransmitter.
Figure3-1-typicalconnexions
3.3 InterfacingtoDigitalAudioReceiversAudio input and output ports are designed to interface to a variety of audio devices, including receiverscommonly used for AES/EBU and S/PDIF communications. Figure 3-2 illustrates the interface between aCirrus Logic WM8804 receiver and the Q8 input port whereby the Q8 Module works as Slave and thereceiverasMaster.
Figure3-2-interfacingwithadigitalreceiver
Q8 Module
digital audio
transmitter
dual D/A converter
FSYNCBITCLKSDATA0
FSYNCBITCLKSDATA0SDATA1
digital audio
receiver
WDCLKBITCLKSDATA0SDATA1DATA VALID
RX A
UDIO
PO
RT
LEFT
-CHA
NNEL
TX A
UDIO
PO
RTRI
GHT
-CHA
NNEL
TX A
UDIO
PO
RT
CONT
ROL
PORT
host processor
MODE0MODE1MODE2SPI_CS(*)SPI_SCK(*)SPI_MISO(*)SPI_MOSI(*)IRQ(*)RESET
low-jitterhigh quality
master clock
Q8 Module
RX_WDCLK
WM8804
LRCLKBCLKDOUT
GP0 (GEN_FLAG)
RX_BITCLKRX_SDATA0RX_SDATA1
DSP_MODE3
DSP_MODE1
33R33R33R
DATA VALID
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Careful impedance matching must be maintained between drivers, transmission lines and receivers tominimizesignalovershoot,undershootorringing.Figure3-2showssourcedamping-resistorterminationsof33Rasanexample.Properimpedancematchingandterminationdependsupondesignandlayout.In situationdescribed in Figure3-2 ,DSP_MODE1 is low forPCMandDoP input support.ADoP encodedstreamwillbeseenby thedigitalaudioreceiverasaPCMdata flow,but theQ8Modulewilldetect itandextract DSD data. DSP_MODE3 is used for muting the Q8 output when the receiver is unlocked ortransmittingnon-audiodata.
3.4 InterfacingQ8outputsTheQ8Moduleisdesignedspecificallytodrivehighperformance384kHzD/Aconverters.Thus,themoduleisabletodrivebothdual384kHzcompatibleDAC'sandanexternaltransmitteratthesametime.ConnectiontodualDAC's,configured inmonomode,andto thetransmitter isgiven inFigure3-3. In thatcase theQ5worksasClockMasterandtheDAC's/TransmitterasClockSlavedevices.
Figure3-3-interfacingtoD/Aconverters
3.5 ReferenceMasterClockTheQ8Modulerequiresa low-jittermasterclock foroperation.Thisclockmustbesuppliedat theCLKINinput(pin9)directlyfromanexternalcrystaloscillatororbyaclockbuffer.TheQ8Moduleisdesignedtoworkwithasinglefrequencyat24.5760MHz.Asaresult,alltheaudiooutputsamplingfrequencieswillbederivedfromamultipleof48kHz.Master clockdistributionmust be carefully designed tominimise jitter.Best result is usually achievedbyusingaclockfan-outbufferandpoint-to-pointconnexionstoeachdevicewithproperimpedancematching.
Q8 Module
33R33R33R33R
TX1_FSYNCTX1_BITCLKTX1_SDATA0TX1_SDATA1
TX0_FSYNCTX0_BITCLKTX0_SDATA0TX0_SDATA1
33R33R33R
384kHz DAC Left channel
WCLKBCLKLDATA
MCLK
384kHz DAC Right channel
WCLKBCLKRDATA
MCLK
Digital Transmitter
WCLKBCLKDATA
MCLK
24.576MHzoscillator
and fan-out buffer
CLKIN
Master ClockAnalog outputleft channel
Analog output right channel
Digital output
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3.6 ResetandPowerOnTheQ8ModulemayberesetusingtheRESETinput(pin3).Ithastobeheldlowforaminimumof500nstoguaranty a proper reset. TheRESEThas an internal pull-up resistor. Furthermore, the Q8 integrates aninternalpower-onresetmanagement,sotheuserdoesn’tneedtoforcearesetsequenceafterpowerupinordertoinitializethemodule.Oncethereset isreleased, there isa400msdelayforthemoduletobeoperational. Insoftwaremode, thehost MCU must observe this delay before attempting to write to the SPI port due to internal logicrequirements.
3.7 AudioSerialInputPort(RX)TheRXaudioinputportisafour-wiresynchronousserialinterfaceworkinginSlavemode.InPCMmode,theport uses three signals, namely RX_WDCLK (pin 17), RX_BITCLK (pin 18) and RX_SDATA0 (pin 19).RX_WDCLK provides the frame synchronization clock while RX_DATA0 and RX_BITCLK are used torespectively transfer the serial audio data and clock the serial data into the port. This latter supportssampling frequenciesupto384kHz.Theaudiodataword lengthmaybeupto24bitandtheaudiodata isalwaysbinarytwo’scomplementwiththeMSBfirst.InDSDmode,threesignalsoutoffourareused,RX_BITCLK(pin18),RX_SDATA0(pin19)andRX_SDATA1(pin 20) pins. RX_BITCLKprovides theDSD clock synchronization (2.8224MHz, 3.072MHz, 5.6448MHzor6.144MHz)whileRX_SDATA0andRX_SDATA1are respectively the left and right channeldata. Figure3-4illustratestheaudiodatastreamofeachmode.
Figure3-4-audioinputportdataformat
Insoftwaremode,theInputControlRegisterallowstoselecttheinputaudiodataformatmode.Twobitsareusedtochoosethemode,namelyFMT0andFMT1.TheconfigurationintheInputControlregisterisOR-edwiththeDSDInputpinDSP_MODE1.Inhardwaremode,itistheDSDInputpinDSP_MODE1thatallowstheinputaudiodataformatmodetobeconfigured.WhenDSDInputpinishigh,theDSDmodeisselectedasopposedtolowwherethePCMmodeisenabled.DoPdataandclockingisequivalenttoPCM,thereforeDSP_MODE1mustbelowforDoPstream.
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3.8 TX1AudioOutputPortTheTX1audiooutputportisafour-wiresynchronousserialinterfaceworkinginMastermode.TX1_SDATA0(pin 24) and TX1_SDATA1 (pin 25) pins are the PCM upsampled serial data output for left and rightchannels.TX1_BITCLK(pin23)outputoperatesatarateof32xFSYNC.TheWordClockTX1_FSYNC(pin22)isalsoconfiguredasoutputandissettooperateatarateof8xFS.
Figure3-5-MonoFramedDSPMode
The audio output ports are configured either in MonoFramed DSPMode or MonoFramed Right-JustifiedMode.Theaudiodatawordlengthissetto32-bit.TheaudiodataisalwaysBinaryTwo’sComplementwiththeMSBfirst.RefertoFigure3-5andFigure3-6fortheoutputdataformats.
Figure3-6-MonoFramedRight-JustifiedDSPMode
3.9 TX0AudioOutputPortTX0 audio output port is a three-wire synchronous serial interface working in I2S Master mode.TX0_SDATA0 (pin 29) output is the PCM down-sampled serial data output. The left/right word clockreferredtoasframesync,TX0_FSYNC(pin27)outputpincanbesettooperateatratesof1xFS,2xFSor4xFS.
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Theaudiodatawordlengthis32-bit.TheaudiodataisalwaysBinaryTwo’sComplementwiththeMSBfirst.RefertoFigure3-7.
Figure3-7-TX0Outputdataformat
3.10 DataResolutionandDitherWhenusingtheserialaudioinputportinI2Smode,allinputdataisprocessedas32-bitwide.Anyaudiodatawidth truncation(compared to theoriginalaudiodatasource),performedprior to theQ8Module, shouldhavebeendoneusinganappropriateditheringprocess.ThereisnoditheringmechanismontheinputsideoftheQ8Module,socaremustbetakentoensurethatnotruncationoccurs.Theaudiooutputportsaresetto32-bit.
3.11 IncomingSamplingRateandLockingWhentheQ8Moduleprocessestheincomingaudiodatastream,itcalculatestheratiobetweentheinputandoutputsampleratesandusesthisinformationtosetupvariousinternalparameters.InPCMinputmode,theQ8Moduleaccepts standardsampling frequenciesof32,44.1,48,88.4,96,176.4,192,352.8and384kHzwitha±2%deviationfromthenominalvalue.WhereasinDSDinputmode,theQ8Moduleacceptssamplingfrequenciesof2.8224,3.072,5.6448and6.144MHzwitha±2%deviationfromthenominalvalue.Ifanon-standardinputsamplingfrequencyisfoundorthestandardsamplingratedeviatesmorethan2%fromthenominalvalue,theQ8ModulewillNOTprocesstheincomingdataandwillbeastatusofunlocked.The Q8 Module can dynamically compensate for drift and fluctuations in the incoming input samplingfrequencywhere the processingwill track the incoming sample rate and automatically adjust the samplerateconversionprocessinordertomaintainthehighestlevelofaudioquality.InSoftwaremode, InputControlRegister functionsasstatusregisters,whichcontainsthe inputfrequencysamplingdetected.The INTREQpin reflects the lock stateof themodule. If there is a change in the inputsamplingratetheINTREQsignalgoeslowtoindicateanunlockstateuntiltheQ8Modulereacquiresavalidratio.Atthispoint,theINTREQwilltransitionhigh.
Q5 Interfacing and Operation
BITCLK Serial bit Clock 2.8224 MHz
Table 9 Serial input clocks in DSD mode
3.8 Audio Serial Ports - TX0 Output
The TX0 audio output port is a three-wire synchronous serial interface working in mastermode. TX0_SDATA1 (pin 29) output is the PCM downsampled serial data output. TheTX0_BITCLK (pin 28) output operates at a rate of 64xFSYNC. The left/right word clockreferred to as frame sync, TX0_FSYNC (pin 27) is also configured as output pin and it canbe set to operate at rates of 1xFS, 2xFS or 4xFS (see § 4.2.2).
The audio data word length may be up to 24bit. The audio data is always Binary Two’sComplement with the MSB first. Refer to Figure 15 TX0 output data formats for the outputdata formats.
FSYNC
BITCLK
MSB LSBSDATA
I2S Data Format 16 -24 bits
Right ChannelLeft Channel
MSB LSB
Figure 15 TX0 output data formats
CLKIN Frequency TX0 Output Frequency
1xFS 2xFS 4xFS
Unit
24.5760MHz 48 96 192 kHz
Table 10 TX0 output frequency sampling vs CLKIN frequency
Parameter Description Value
FSYNC Frame Sync Clock 48/96/192kHz
BITCLK Serial bit Clock 64xFSYNC
Table 11 TX0 output clocks
3.9 Audio Serial Ports – TX1 Output
The TX1 audio output port is a four-wire synchronous serial interface working in mastermode. The TX1_SDATA1 (pin 24) and TX1_SDATA2 (pin 25) pins are the PCM upsampledserial data output. The TX1_BITCLK (pin 23) output operates at a rate of 32xFSYNC. Theword clock TX1_FSYNC (pin 22) is also configured as output pin and it can be set tooperate at rates of 8xFS (see § 4.2.2).
The audio data word length may be up to 24bit. The audio data is always Binary Two’sComplement with the MSB first. Refer to Figure 16 for the output data formats.
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3.12 MutingTheTXx_SDATA0,TXx_SDATA1,TXx_BITCLKandTXx_FSYNCpinsareall low(hardmute)whenmodule iseitherinresetstateorunlocked(noaudiosourceorDataValidflaghigh).ThesepinsbecomevalidassoonastheQ8Modulegetslocked.Whenthemodule is locked,TXx_SDATA0,TXx_SDATA1pinscanbeset toallzerobyapplyingasoftmutethroughtheconfigurationofthe“Mute”bitintheSPIprocesscontrolregister.InthiscaseTXx_BITCLKandTXx_FSYNC are still active. Thus, in hardwaremode, only theData Valid flag pin can be usedwhereas insoftwaremode,therearetwowaystoputthemoduleinmute,whicharetheDataValidflagorthe“Mute”bitintheSPIregister.
3.13 PhaseInversionTheQ8Moduleincludesaphaseinversionfunctionwherebytheoutputdatacanbeinvertedcomparedwithaudioinputsignal.Bydefault,thisfunctionisdisabledandcanonlybeenableinsoftwaremode.Theselectedconfiguration can be changed through the LSB bit called PHI of the Process Control Register. All otherfeaturesofthemoduledon’taffectthisfunction.
3.14 StereoDSDtoPCMConversionTheQ8ModuleincludesastereoDSDtoPCMconverter.ThisgivesthepossibilityofconnectingaDSDinputstreamon theRX input port and using this stream asmain audio source. The selection of theDSD inputformat is done by setting DSP_MODE1 pin in hardware. In softwaremode, the FMT bits in Input controlregisterallowstoenabletheDSDinputformat.As described in chapter 3.7 “Audio Serial Input Port (RX)”, the RX audio input port is a four-wiresynchronous serial interface that is configured to operate in SlaveMode. Only three out of four lines areused.TheRX_SDATA0andRX_SDATA1linesaretheserialaudiodatainputsforDSDleftandrightchannelsrespectively.DSDdataformatis1bitstream,thereforenoframesynchisneeded.DoP(DSDoverPCM)isreceivedbytheinputportRXasaPCMstreamandaccordinglyDSP_MODE1mustbelow.DoPencodedinputstreamisautomaticallydetectedbythePCMinputunitaccordingtothespecificDoPmarkercode.StereoDSDdataarethenextractedfromthepseudoPCMdatastreamandsenttotheDSDtoPCMconverterunit.
3.15 DataValidflag(DSP_MODE3)The Q8 Module uses the Data Valid flag (DSP_MODE3) input pin to know whether it should attempt tosynchronizewiththeincomingaudiodatastream.IftheDataValidflagishigh,thenthemodulewillneverattempttolockandtheoutputswillbehardmuted.IftheDataValidflagislow,thenthemodulewillattempttofindtheinputsamplingfrequencyandprocesstheaudiodataaslongastheyarevalid.TheINTREQpincanbeusedtotrackthemodulestate(lock/unlock).
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3.16 SerialPortInterface(SPIPort)TheSPIportistheinterfaceusedtooperatetheQ8Moduleinsoftwaremode.ThisportallowsthesystemhostMCUtoaccessQ8Moduleinternalregistersforreadandwriteoperations.ThehostMCUisreferredastheMasterDeviceandtheQ8ModuleisreferredasSlaveDevice.The operation of the SPI port may be completely asynchronous with respect to the audio stream rates.However,itisrecommendedtokeeptheportpinsstaticifnooperationisrequired.The SPI port is a four-wires serial interface whereSPI_CS(active low) is the module chip select signal,SPI_SCKisthecontrolportbitclock(inputintothemodulefromtheMasterDevice),SPI_MOSIistheinputdatalinefromMasterDeviceandSPI_MISOistheoutputdatalinetotheMasterDevice.DataisclockedinontherisingedgeofSPI_SCKandclockedoutonthefallingedge.
Figure3-8-SPIprotocolforregisterread/writeoperations
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Table3-1andFigure3-8illustratetheoperationoftheSPIportaswellastheprotocolforregisterreadandwriteoperations.
ByteName MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSBHeaderByte 0 0 0 RW 0 A2 A1 A0
DataByte D7 D6 D6 D4 D3 D2 D1 D0
Table3-1-SPIbytedefinitionforregisterread/writeoperations
A2–A0 RegisteraddressselectionRW Read/Writecontrol 0: RegisterRead 1: RegisterWriteD0–D7 Registerdata
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4 HardwareMode
4.1 GeneralDescriptionTheQ8Modulecanwork inhardwaremodewhichallows thedevice tooperatewithoutahostsystemorserialcommunicationontheSPIport.Thedevice isconsidered inHardwaremodewhentheMD_CSpin isleftunconnectedorpulledupwitha resistor (10kΩ) toVDD. In thismode, themodule starts in adefaultconfiguration.However, the fourDSP_MODExpinsremainvalidandareused forsettingtheQ8Module inthecorrectoperationmode.
4.2 HardwareConfigurationTowork in hardwaremode, the SPI port can be left unconnected. DSP_MODEx pins are described herebelow.Pin# Name Type Description11 DSP_MODE0 Input TX1Outputportdataformat
12 DSP_MODE1 Input DSD/PCMinputformat
13 DSP_MODE2 Input Unused–shouldbeconnectedtoGND
14 DSP_MODE3 Input DataValidflag–activelow
Table4-1-DSP-MODExhardwarecontrolsummary
DSP_MODE0 TX1outputportdataformat 0: mono-framedleftjustifiedoutputmode 1: mono-framedrightjustifiedoutputmodeDSP_MODE1 DSD/PCMinputformat 0: PCMorDoPinputstream 1: nativeDSDinputstreamDSP_MODE2 Unused–shouldbetiedtoGNDDSP_MODE3 DataValidflag 0: incomingaudiodatastreamisvalid 1: incomingaudiodatastreamisnotvalid,outputismuted
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5 SoftwareMode
5.1 GeneralDescriptionTheQ8Modulesoftwaremoderequests thedevicetooperatewithahostsystemhavinganSPIport.ThismodeallowsthehostsystemtoconfigureorreadinformationfromtheQ8ModulebyaccessingitsinternalregistersthroughtheSPIport(seechapter3.16“SerialPortInterface(SPIPort)”forfurtherdetailsonSPIoperational port). The following chapters give details and bits definition of each register aswell as theirdefaultsettingafterreset.Q8ModuleRegistersOverviewAddr RegisterName Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit00x00 InputStatus SFMT0 x XFS3 XFS2 XFS1 XFS0 FMT1 FMT0
0x01 TX0OutputControl x x x x TX01 TX00 x x
0x02 ProcessControl x x x x x DATA MUTE PHI
0x03 Reservedforfactoryuse - - - - - - - -
0x04 Reservedforfactoryuse - - - - - - - -
0x05 Reservedforfactoryuse - - - - - - - -
0x06 SoftwareRevision REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
0x07 ProductID ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0x08 Reservedforfactoryuse - - - - - - - -
0x09 SubProductID SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0
Table5-1–registermap
5.2 InputStatusRegisterRegisteraddress:0x00
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSBBitname SFMT0 x XFS3 XFS2 XFS1 XFS0 FMT1 FMT0
Accesstype R R R R R R R R
Defaultvalue 0 0 0 0 0 0 0 0FMT1..0 InputFormat 00: I2S 01: reserved 10: reserved 11: DSDXFS3..0 InputSamplingFrequency 0000: Unlock 0001: 32kHz 0010: 44.1kHz 0011: 48kHz 0100: 88.2kHz 0101: 96kHz 0110: 176.4kHz
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0111: 192kHz 1000: 352.8kHz 1001: 384kHzSFMT0 InputSubFormat 0: PCM 1: DoP(PCMframecontainingencapsulatedDSDdata)
5.3 TX0OutputControlRegisterRegisteraddress:0x01
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSBBitname x x x x TX01 TX00 x x
Accesstype R/W R/W R/W R/W R/W R/W R/W R/W
Defaultvalue 0 0 0 0 0 1 0 0TX01..0 Directdown-sampledoutputfrequency 00: Reserved 01: 1xFS(48kHz) 10: 2xFS(96kHz) 11: 4xFS(192kHz)
5.4 ProcessControlRegisterRegisteraddress:0x02
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSBBitname x x x x x DATA MUTE PHI
Accesstype R/W R/W R/W R/W R/W R/W R/W R/W
Defaultvalue 0 0 0 0 0 0 0 0PHI PhaseInversion 0: PhaseinversionOFF 1: PhaseinversionONMUTE Audiooutputportsmute 0: MuteOFF 1: MuteONDATA DataInputMode 0: 352.8kHz/384kHzPCMinputstreamuseonesingledataline 1: 352.8kHz/384kHzPCMinputstreamusetwodatalines
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5.5 SoftwareRevisionRegisterRegisteraddress:0x06
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSBBitname REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
Accesstype R R R R R R R R
Defaultvalue - - - - - - - -REV7..4 MajorrevisionREV3..0 Minorrevision
5.6 ProductIDRegisterRegisteraddress:0x07
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSBBitname ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Accesstype R R R R R R R R
Defaultvalue 0 0 0 0 0 1 0 0ID7..0 ProductIDcode Permanentlysetto0x05forbackwardcompatibilitywithQ5Module
5.7 ProductSub-IDRegisterRegisteraddress:0x09
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSBBitname SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0
Accesstype R R R R R R R R
Defaultvalue 0 0 0 0 1 0 0 0SID7..0 ProductSUB-IDcode Permanentlysetto0x0AforQ8Module
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6 Relatedproducts
6.1 BackwardCompatibilityThe Q8 Module offers similar functionality as the previous Edel Q5 Upsampler Module and has beendesignedwithbackwardcompatibilityinmind.ThereforproductsusingtheEdelQ5willworkwiththeQ8withoutrequiringanyredesigneffort.CompatibilityconsiderationbetweentheEdelQ5andtheQ8Modulesaredetailedherebelow:
• Identicalhousingandpin-out• Identicalfunctionality• Similarelectricalspecifications• Hardwaremodecontrolisidentical• Softwaremodecontroloffersthesameregistersandaddsmoreoptions• TheQ8offersincreasedcalculationpowerandenhancedprocessingalgorithmsforbettersound
quality
6.2 CustomapplicationsThe Q8 Module is based on a modern digital platform which runs engineered’s software framework fordigital audio processing. This core system can be used for many custom applications where specificprocessingisrequired:
• Cross-over• Time/phasecorrection• Equalization• Compensationforloudspeakercharacteristics• Etc.
Please check ourweb site formore information and contact us for development of custom solutions thatmeetsyourproductrequirements.
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