tokyo electron corporate update
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CORP IR / 2019.07.31 2
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53
1. TEL Overview
2. TEL Initiatives for Medium-term Business Growth
3. Financial Model of Medium-term Management Plan and Growth Investment
4. FY2020 Business Environment and Financial Estimates
Appendix 1: Diversity of Semiconductor Technology and TEL’s Business Strategies
Appendix 2: Technical Challenges for Application and Effects of EUV Lithography Adoption
Appendix 3: Etch System
Appendix 4: Deposition System
Appendix 5: Cleaning System
Appendix 6: Financial Data
Contents
CORP IR / 2019.07.31 4
Striving for
new growthDistributor of other suppliers’ products
Established development/
manufacturing functionsGlobalization Production reform
TEL is Innovative and Flexible to Market Change
0
300
600
900
1,200
1,500
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20(E)
(Billion Yen)
(FY)
TEL consolidated net sales
Listed on TSE #2 in1980 and #1 in 1984 Strengthened corporate governanceEstablished first
manufacturing JV
(TEL-Thermco)Discontinued export business of
consumer productsBegan overseas direct operations
Semiconductor applications
Mainframe computer
Mobile phonePC
Consumer electronics, etc.
CORP IR / 2019.07.31 5
Financial Performance: Sales and Operating Margin
(Billion Yen)
4M DRAM oversupply • IT bubble crash
• Excessive logic foundry
investment
• Financial crisis in Asia
• 64M DRAM oversupply
• World financial crisis
• Memory oversupply
(FY)
• Effects of European debt crisis,
slowdown in emerging markets
• Weak demand for PC, mobile
723.8
906.0
668.7
497.2612.1613.1
663.9
799.7
1,130.7
1,278.2
1,100.0
16.7%
-4.4%
18.6%
-0.5%
14.6%
2.5%5.3%
14.4%17.6%
19.5%
24.9%24.3%
20.0%
-10%
0%
10%
20%
30%
40%
50%
-300
0
300
600
900
1,200
1,500
90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20(E)
TEL Net sales
Operating income
Operating margin
CORP IR / 2019.07.31 6
US$ 1,994B
US$ 475B
US$ 59B
The Market TEL Participates in
¥1,166.7B, 91%
¥111.2B, 9%
¥0.1B, 0%
¥1,278.2B
CY2018 World Market
Electronic System
Semiconductor
WFE* CAPEX
Source: Gartner, “Forecast: Semiconductor Wafer Fab Manufacturing Equipment
(Including Wafer-Level Packaging), Worldwide, 1Q19 Update” Bob Johnson, 9 May 2019
Charts/graphics created by Tokyo Electron based on Gartner research.
Electronic System=Electronic Equipment Production/Semiconductor=Semiconductor
Revenue (Excluding Solar)/WFE* CAPEX=Total Wafer Fab Equipment (including Wafer-
Level Packaging)
FY2019 TEL Sales(April 2018-March 2019)
FPD Production
Equipment
(FPD)
Semiconductor
Production
Equipment
(SPE)
Others
CORP IR / 2019.07.31 7
TEL Main Products World Market Share (CY2018)
Semiconductor Production Equipment
FPD Production Equipment (FY2019)
Source (FPD) : TEL survey
88%
30%38%
25%
Deposition System Cleaning SystemCoater/Developer Dry Etch System
47%
Wafer Prober*
27%40%
54%
ALD CVD Oxidation/Diffusion
29%
68%
FPD Coater/Developer FPD Etcher/Asher
Source
SPE (excluding Wafer Prober) : Gartner, “Market Share: Semiconductor Wafer Fab Equipment, Worldwide, 2018”, Bob Johnson,
Gaurav Gupta et al, 24 April 2019
Charts/graphics created by Tokyo Electron based on Gartner research.
Coater/Developer: Photoresist processing (Track), Dry Etch System: Dry etch, Deposition System: Tube CVD + Atomic layer
deposition tools + Oxidation/diffusion furnaces + Nontube LPCVD, ALD: Atomic layer deposition tools, CVD: Tube CVD + Nontube
LPCVD, Oxidation/Diffusion Furnaces : Oxidation/diffusion, Cleaning System: Single Wafer Processors + Wet stations +Batch Spray
processors + Other clean process
* SPE (Wafer Prober) : VLSI Research, April 2019
Charts/graphics created by Tokyo Electron based on VLSI Research
CORP IR / 2019.07.31 8
World Top 10 SPE Makers
CY2018 Revenue Ranking
14.01
12.81
10.91
10.87
4.24
2.57
2.22
1.49
1.48
1.40
Applied Materials
ASML
Tokyo Electron
Lam Research
KLA-Tencor
Advantest
Screen SemiconductorSolutions
Teradyne
KOKUSAI ELECTRIC
Hitachi High-Technologies
(Billions of US$)
SCREEN
Semiconductor Solutions
Source: VLSI Research, June 2019
CORP IR / 2019.07.31 9
Establish Environmental Medium-term Targets for 2030
9
Total CO2 emissions (vs 2018)Reduce per-wafer
CO2 emissions (vs 2013)
Equipment Facilities
Long-term goal (2050)
30%Reduce energy consumption at
each facility (per-unit basis)
(annual target, YoY)1%
As a leading corporation in environmental management, Tokyo Electron works actively to
conserve the global environment.
We strive to contribute to the development of a dream-inspiring society by proactively
promoting the reduction of environmental burden of both our facilities and products, and
at the same time, providing evolutionary manufacturing technologies that effectively
reduce the power consumption of electronic products.
20%
CORP IR / 2019.07.31 10
External assessments toward our activities
TEL ESG programs have received very positive reviews
TEL is included on several ESG-related indices
CORP IR / 2019.07.31 12
14/16nm 10nm 7nm 5nm
Logic
4X 6/7X 9X 12X
3D NAND
2Z 1X 1Y 1Z
DRAM
Rising Added-value in SPE
WFE investment (100k WSPM*, greenfield/TEL estimates)
~$7B~$8B
~$20B
* WSPM: Wafer starts per month
Expanding business opportunities for SPE manufacturers on arrival
of new applications and rising level of technological difficulty
CORP IR / 2019.07.31 13
Etch System Growth Scenario
Focus on processes with growing SAM and aim to
capture a high SAM share
HARC process
– Increase sales by growing 3D NAND and DRAM SAM
and capturing new PORs
Patterning process
– Expand SAM share by offering production cost
reductions
Interconnect/contact process
– Maintain high market share with growing SAM and by
differentiating technology
Gas chemical etch process
– Increase sales by creating new markets
0
500
1000
1500
2000
2500
3000
3500
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
CY'17 CY'18 CY'19 CY'20 CY'21 CY'22
SAM (in dollars) HARC Patterning
Interconnect/contact Gas chemical etch
Sales targets by process type within
TEL’s SAM for etch systems** TEL forecasts. SAM shown on a dollar basis and sales on a yen basis
Aim for 30-35% SAM share within 5 years
CORP IR / 2019.07.31 14
Expand business by choosing the most
appropriate method among batch, semi-batch
and single wafer, and providing high value-
added technologies
In deposition technologies, which are becoming
increasingly advanced, accelerate development
of new materials and new deposition method by
leveraging our strengths. Aim for further growth
– Deposition of new metal material to achieve lower
resistance
– New deposition methods to promote scaling, such
as anisotropic deposition and selective deposition
– Pre-treatment technology to realize better electric
characteristics
Deposition System Growth Scenario
Focus on high value-added deposition processes,
aim for 40%+ SAM share within 5 years
0
20000
40000
60000
80000
100000
120000
140000
160000
0.0
1.0
2.0
3.0
4.0
5.0
CY'17 CY'18 CY'19 CY'20 CY'21 CY'22
SAM (in dollars) DRAM NAND Logic/Foundry Others
Sales targets by application within
TEL’s SAM for deposition systems** TEL forecasts. SAM shown on a dollar basis and sales on a yen basis
Deposition System: Tube CVD + Atomic layer deposition tools + Oxidation/diffusion furnaces + Nontube LPCVD
CORP IR / 2019.07.31 15
Cleaning System Growth Scenario
Single wafer cleaning
– Grow sales with pattern collapse reduction
technology and by improving productivity
– Maintain a high market share for bevel wet etch
and expand applications through removal of new
materials
Batch cleaning
– Expand POR in 3D NAND critical processes
Scrubber cleaning
– SAM will grow as importance of back/bevel
processing increases due to introduction of EUV
Aim for 30% SAM share within 5 years
-10%
10%
30%
50%
70%
90%
110%
130%
150%
0.0
1.0
2.0
3.0
4.0
5.0
CY'17 CY'18 CY'19 CY'20 CY'21 CY'22
SAM (in dollars) Single wafer cleaning
Batch cleaning Scrubber
SAM share
25%
* TEL forecasts. SAM shown on a dollar basis and sales on a yen basis
Sales targets by system type within
TEL’s SAM for cleaning systems*
CORP IR / 2019.07.31 16
FPD Manufacturing Equipment Growth Scenario
Sales and operating margin(Billion yen)
Raise competitiveness of dry etch
system and coater/developer
Create inkjet market for large OLED
displays
Launch new products that reflect
evolution of displays
-10%
-5%
0%
5%
10%
15%
20%
25%
30%
35%
0
20
40
60
80
100
120
FY'15 FY'16 FY'17 FY'18 FY'19 FY'20 FY'21 FY'22 FY'23
Sales Operating margin
Aim for 30% operating margin within 5 years
CORP IR / 2019.07.31 17
115.0150.0
188.8
250.0
93.0
101.099.4
130.0
0
FY'17 FY'18 FY'19 FY'20
FS sales
Grow SAM through increase in
installed units
(installed base of 69,000 units)
Respond to new customer needs• 200mm renewal equipment
• Comprehensive contract services
Enhance business efficiency by
cooperating with Business Innovation
Project
Used equipment
and modification
Parts and services
Growth strategy key points
Field Solutions (FS) Sales Results and Growth Strategy
380.0B yen
208.0
251.0288.2
Leverage our strengths as an equipment manufacturer
to increase earnings in both the used equipment/modification
and parts/services segments
Target for
5 years hence
CORP IR / 2019.07.31 19
New Financial Model (within 5 Years)
Increase corporate value through innovative technologies and groundbreaking proactive
solutions, raise efficiency and secure even higher profitability and resistance to market shifts
FY2019
(Actual)
FY2020
(Estimates)
Within 5 years
(Plan)
$59B $47 – 50B $55 – 60B $60 – 65B $65 – 70B
Net sales 1,278.2 1,100.0 1,500.0 1,700.0 2,000.0
SPE 1,166.7 1,030.0 -- -- --
FPD 111.2 70.0 -- -- --
Gross profitGross profit margin
526.141.2%
441.040.1%
650.043.3%
740.043.5%
890.044.5%
SG&A expensesSG&A expenses to sales ratio
215.616.9%
221.020.1%
252.016.8%
264.015.5%
290.014.5%
Operating incomeOperating margin
310.524.3%
220.020.0%
398.026.5%
476.028.0%
>600.0>30.0%
ROE 30.1% -- >30%
WFE market
(Billion yen)
CORP IR / 2019.07.31 20
Raise gross profit margin of core SPE, FPD products
– Timely introduction of new products to an expanding market
– Lower cost ratio through product quality improvements
Gross Profit, SG&A Expenses (Sales ¥2,000.0B Model)
FY2019
(Actual)
FY2020
(Estimates)
Within 5 years
(Plan)
Growth rate
(FY’19-FY’23)
Gross profit
Gross profit margin
526.141.2%
441.040.1%
890.044.5%
+69.1%+3.3pts
(Billion yen)
Proactively invest in growth areas while planning appropriate SG&A and
R&D expenses
FY2019
(Actual)
FY2020
(Estimates)
Within 5 years
(Plan)
Growth rate
(FY’19-FY’23)
SG&A expenses
SG&A expenses to sales ratio
215.616.9%
221.020.1%
290.014.5%
+34.5%-2.4pts
(Billion yen)
CORP IR / 2019.07.31 21
R&D Expenses, Capex Plan
39.5
21.7
12.7 13.1 13.3
20.6
45.649.7
56.0
40.0-50.0
24.1 26.6 24.820.8 19.2 17.8
20.624.3
33.0 35.0-37.0
0
20
40
60
FY’12 FY’13 FY’14 FY’15 FY’16 FY’17 FY’18 FY’19 FY’20 (E)
81.573.2 78.6
71.3 76.283.8
97.1
113.9 120.0
0
50
100
150
FY'12 FY'13 FY'14 FY'15 FY'16 FY'17 FY'18 FY'19 FY'20 (E)
R&D expenses
Capex Depreciation
400.0B yen3 year total
(Billion Yen)
(Billion Yen)
Conduct proactive investment towards further growth
Enhancing development and production structures in growth areas
CORP IR / 2019.07.31 22
FY2020 Business Environment and Financial Estimates(FY2020: April 1, 2019-March 31, 2020)
CORP IR / 2019.07.31 23
FY2019 (April 2018 – March 2019) Highlights
Net sales +13% YoY driven by higher competitiveness in the growing SPE*1
market and expanded share in FPD*2
New record highs for gross profit, operating income and net income attributable to owners of parent
Net Sales and Gross Profit Margin
613.1 663.9799.7
1,130.7
39.6% 40.2% 40.3%42.0% 41.2%
0
400
800
1,200
FY'15 FY'16 FY'17 FY'18 FY'19
Net sales (¥B)
Gross profit margin
88.1116.7
155.6
281.1310.5
14.4%
17.6%19.5%
24.9%
24.3%
0.0%
5.0%
10.0%
15.0%
20.0%
25.0%
30.0%
0
50
100
150
200
250
300
FY'15 FY'16 FY'17 FY'18 FY'19
Operating income (¥B)
Operating margin
Operating Income and Operating Margin
Net Income Attributable to
Owners of Parent and ROE
71.8 77.8
115.2
204.3
248.211.8% 13.0%
19.1%
29.0%
30.1%
0
50
100
150
200
250
FY'15 FY'16 FY'17 FY'18 FY'19
Net income attributable toowners of parent (¥B)
ROE
*1 SPE: Semiconductor production equipment *2 FPD: Flat panel display production equipment
1,278.2
CORP IR / 2019.07.31 24
► WFE*1 capex
We expect CY2019 investment to decrease 15-20% YoY.
Despite solid investment for logic/foundry, we expect a temporary
adjustment in memory investment on a softening in demand and macro-
economic effects. Inventory adjustments are proceeding, and we expect a
recovery in memory investment in CY2020
►FPD production equipment capex for TFT array process*2
In 2019, we expect capex for OLED panels in mobile applications to be soft,
and investment in large panels is undergoing a temporary adjustment.
Full-year capex is forecast to decrease 30% YoY, but a recovery is expected
from H2
Business Environment (Outlook as of July 2019)
*1 WFE (Wafer fab equipment): The semiconductor production process is divided into front-end production, in which circuits are formed on wafers and inspected, and back-end production, in
which wafers are cut into chips, assembled and inspected again. Wafer fab equipment refers to the production equipment used in front-end production and in wafer-level packaging production.
*2 TFT array process: The processes of manufacturing the substrates with the electric circuit functions that drive displays
CORP IR / 2019.07.31 25
Logic/Foundry: Forecasting market growth of approx. 35% YoY
– Market environment: Increased capex on generation change. 10nm and beyond generation
to comprise 50%
– Opportunities: Business expansion in more complex patterning processes
Non-volatile memory: Approx. 60% decrease YoY
– Market environment: Making adjustments in investment for increasing production capacity
due to improved yield, but inventories are gradually declining. 9X/12X generations to
comprise over 80% of capex
– Opportunities: Differentiation through high value-added etch and clean
DRAM: Approx. 40% decrease YoY
– Market environment: 1Y/1Znm generations to comprise approx. 60% of capex
– Opportunities: Combined patterning in latest generation
CY’19 WFE Market and Business Opportunities by Application
Despite a decrease in memory investment in CY2019,
recovery is expected in CY2020
CORP IR / 2019.07.31 26SPE: Semiconductor production equipment, FPD: Flat panel display production equipment
FY2019
(Actual)
FY2020 (Estimates)
H1 H2 Full yearFull year
YoY change
Net sales 1,278.2 490.0 610.0 1,100.0 -13.9%
SPE 1,166.7 450.0 580.0 1,030.0 -11.7%
FPD 111.2 40.0 30.0 70.0 -37.1%
Gross profitGross profit margin
526.141.2%
192.039.2%
249.040.8%
441.040.1%
-85.1-1.1pts
SG&A expenses 215.6 107.0 114.0 221.0 +5.3
Operating incomeOperating margin
310.524.3%
85.017.3%
135.022.1%
220.020.0%
-90.5-4.3pts
Income before income taxes 321.5 85.0 135.0 220.0 -101.5
Net income attributable to
owners of parent248.2 63.0 101.0 164.0 -84.2
Net income per share (Yen) 1,513.58 388.83 - 1,015.21 -498.37
FY2020 Financial Estimates (no change from Apr. 26, 2019 announcement)
Market undergoing correction but continuing investmenttowards a recovery next year
(Billion yen)
CORP IR / 2019.07.31 27
53%
60%
20% 22%
8% 12%
42%
34% 20%
20%
30%
32%27%
20%
504.3
384.3
319.0
444.0
0
100
200
300
400
500
FY'19 H1(Actual)
FY'19 H2(Actual)
FY'20 H1(Estimates)
FY'20 H2(Estimates)
FY2020 SPE Division New Equipment Sales Forecast
51%
33%
26%
15%
22%26%
27%130.6
188.4
0
100
200
FY'20 Q1(Actual)
FY'20 Q2(Estimates)
Q1 results were as planned; have already shipped over half of the Q2 sales target
Expect substantial increase in sales for logic/foundry
Sales by application
(Billion yen)
(Billion yen)
Logic foundry
Logic & others
DRAM
Non-volatile memory
Logic foundry +
Logic & others
Percentages on the graphs show the composition ratio of new equipment sales. Field Solutions sales are not included.
Figures for FY2020 H2 are rough estimates.
CORP IR / 2019.07.31 28
FY2020 Dividend Forecast (as of Apr. 26, 2019 financial estimates announcement)
(Yen)Dividend per share
Dividend payout ratio: 50%
Annual DPS of not less than 150 yen
We will flexibly consider share buybacks
TEL shareholder return policy
We will review our dividend policy if the company does not generate
net income for two consecutive fiscal years
Expect to announce dividend revision from ongoing share buybacks
when Q2 results are announced
0
300
600
900
FY'15 FY'16 FY'17 FY'18 FY'19 FY'20 (E)
143 yen
237 yen
Year-end
309 yen
624 yen
352 yen
758 yen
502 yen
Interim
193 yen
CORP IR / 2019.07.31 29
Share Repurchase Plan
• Type of shares to be acquired: Shares of common stock
• Total number of shares to be acquired: Up to 14 million shares
(Equivalent to 8.5% of outstanding shares excluding treasury stock)
• Total cost of acquisition: Up to 150 billion yen
• Period of acquisition: From May 28, 2019 to December 31, 2019
Plan to implement share repurchase of up to 150B yen
We will continue to manage our balance sheet flexibly
while considering our ability to generate cash, necessary
cash on hand and growth investment capital
CORP IR / 2019.07.31 30
Appendix 1: Diversity of Semiconductor Technology
and TEL’s Business Strategies
CORP IR / 2019.07.31 31
180130 110 90
6545
3222
14
107
5
1
10
100
1000
1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020
Wavelength
Technology node
ArF
EUV
i-ArF
Scaling
KrF
Performance Enhancement through Scaling, Material
Development and 3D Structures
i-line
High AR of DRAM
3D NAND
Planar FET
FinFET
Nanowire FET
3D Architecture
[nm]
Architecture, design, process are also being actively investigated
Planar NAND
Planar FET
3D NAND large stack
CORP IR / 2019.07.31 32
Semiconductor Technology Roadmap
Future device systemsfor HPC/AI/IoT
Logic sub
Logic BEOLeMemory
HBM
Logic sub
Logic BEOL
Interposer
3D NAND
High AR TSV
High density RDL
RF/Analog
Capacitor for stable power supply
Low-k
Face-to-Face bonding
High dense TSV
Low energy
consumption
High productivity
SPE tool
Power device
for IoT
RF analog
for IoT
Demand for ultra-low power consumption technology
>2 TiersScalingMRAMReRAM
AI chip (Analog memory)
New architecture Higher-k capacitor Scaling (WL/BL)
DRAM
>2 TiersWL metal>150 layers
NAND
Logic
Ad-packageEUV doubleEUV singleAd-SAQP
Patterning
GAA Tr.*Contact metalBEOL structure Systemize technology by integrating chips - DRAM tower with via- Analog/NAND/Logic by stacking- Built-in AI (Analog memory) - Moore’s Law by package scaling
TEL forecasts
underarrayCMOS
* Gate-all-around transistor
CORP IR / 2019.07.31 33
Market Heading Towards Diversification
PC/Mobile systems
Moore’s LawImproved performance through
transistor integration
CustomizationMulti-functionality
Hyper-massPursuit of ultra-efficient productivity
Applications increase, production technology diversifies too
OS
CPU + Memory AI system
Communicationsystems
Healthcaresystems
Roboticsystems
Mobility systems
CORP IR / 2019.07.31 34
Maximize Utilization of TEL’s Comprehensive Strengths
Market-
ingCoater/
Developer Etch Deposition Cleaning Test
Sales
R&D Manu-
facturing
FS
Strong next generation
product development
Process integration High quality
Robust supply chain
Largest installed
base in industry:
69,000 units
Advanced FS
Broad product coverage
Advanced data
collection and
analysis abilities
Customer trust
CORP IR / 2019.07.31 35
Continually Pursuing the Best Products and Best Service
Front-loading
Advanced
field solutions
Business development leveraging industry’s largest installed
base of 69,000 units
TELeMetrics™ remote maintenance
Predictive maintenance with machine learning
Vision: A truly global company generating high added value and profits in the semiconductor and
FPD industries through innovative technologies and groundbreaking proactive solutions that
integrate diverse technologies
Share roadmap for next several generations with customers
Promote early engagement
Realize maximum yield of customer devices and equipment
availability from early stage of customers’ mass production and
reduce burden on the environment
Further increase investment in human resources/R&D by raising
operational efficiency and driving higher per-employee productivity
CORP IR / 2019.07.31 36
Appendix 2: Technical Challenges for Application
and Effects of EUV Lithography Adoption
CORP IR / 2019.07.31 37
DRAM Process Challenges at a Glance
Scaling increasingly difficult due to capacitor pitch
limitation
– Multi-patterning at Capacitor, WL, BL, STI levels
To scale capacitor EOT, high-k (ZrO2/Al2O/ZrO2)
dielectrics have been introduced with metal (MIM)
CMOS (periphery) portion moving to HKMG* &
FinFETs to reduce area
Capacitors will change from cylinders (dielectric
on outside and in center) to pillars (dielectric on
outside only) with thinner high-k for space saving
– Aspect ratio increases to >50:1 @D16 node
and continues to ~80:1
All aspects of high aspect ratio structure difficult to
fabricate (etch, film deposition, cleaning, …)
STI
Capacitor
Interconnects
Contact
Bitline
Buried gate
Conventional 6F2
cell structure
DRAM faces scaling, materials and integration challenges
* HKMG: High-k metal gate
CORP IR / 2019.07.31 38
NAND Process Challenges at a Glance Scaling is no longer limited by lithography. Rather, it is
limited by the number of ONON or OPOP device
layers one can stack for higher capacity
The high aspect ratio of the device structure is proving
to be more challenging for every new generation
CMOS (periphery) portion moving under memory to
reduce area creates a difficult thermal budget problem
Contact
Channel
Staircase
Word line isolation (Slit)
Gate
Photo image: TECHINSIGHTS
Etch and deposition of the multi-layering
progressively difficult as AR increases
2016 - 2017 2018 - 20192020 -
2021
2022 –
2023
# of 3D tiers 4X 6X 9X 12X 25X 51X
Hole CD (nm) 65 - 100 65 - 100 65 - 100 65 - 100 65 - 100 65 - 100
Holes between slits 4 4 4 - 8 8 8 8
Vertical pitch (nm) 50 - 70 40 - 60 40 - 60 40 - 50 40 - 50 40 - 50
Bitline CD (nm) 20 20 20 - 40 ~40 ~40 ~40
TEL forecasts
CORP IR / 2019.07.31 39
1
12
33 masks
Too close
Closer
Too far
1 mask
Cut
Three exposures: (Litho + Etch) x 3 Lower yield
Increased yield
Placement errors reduced
Cross section of
a logic structure
EUV
introduction
Conventional
exposure
Exposure using
EUV
11
11
Line
Space
Self-aligned multiple patterning (SAMP)
- high etch and dep usage
LELELE = (Litho-Etch)3
- limited etch and dep usage
Step 1: Line/Space
Step 2: Cut
One exposure: (Litho + Etch) x 1
Each exposure process
creates placement errors
Logic: Overcoming Technological Hurdles (Placement Errors)
with EUV
CORP IR / 2019.07.31 40
(Litho-etch)n Patterning for Logic MOL Contact/Cut Module
• PMD dep
• Hard mask1 dep
• Hard mask2 dep
• Lithography1
• Contact HM2 etch1 short etch time
• Lithography2
• Contact HM2 etch2 short etch time
• Lithography3
• Contact HM2 etch3 short etch time
• Contact HM1 etch short etch time
• Contact PMD etch long etch time
• Post etch clean
• Barrier metal Ti/TiN dep
• Contact plug W dep
• Contact plug W CMP
Lithography1 Lithography2 Lithgraphy3
Contact PMD etch
Contact HM2
etch1
Contact HM2
etch2
Contact HM2
etch3
Contact HM1 etch Contact plug W CMP
Thicker layer
Higher etch selectivity
(Litho-etch)3 patterning EUV lithography
Contact HM2
etch
(Litho-etch)n patterning
or
CORP IR / 2019.07.31 41
Self-aligned Multiple Patterning for Line/Space
Mandrel2 etch Sidewall1 dep Sidewall etch back1
Hard mask3 etch Mandrel1 etch Sidewall2 dep Sidewall etch back2
Hard mask1Hard mask2
Mandrel1Hard mask3Hard mask4Mandrel2Hard mask5
𝑝
• Had mask1 dep
• Hard mask2 dep
• Mandrel1 dep
• Hard mask3 dep
• Hard mask4 dep
• Mandrel2 dep
• Hard mask5 dep
• Lithography
• Hard mask5 etch
• Mandrel2 etch
• Sidewall1 dep
• Sidewall1 etch back
• Mandrel2 pull
• Hard mask4 etch
• Hard mask3 etch
• Mandrel1 etch
• Sidewall2 dep
• Sidewall2 etch back
1
2𝑝
SADP
SADP: Self-aligned double patterning
SAQP: Self-aligned quadruple patterning
1
4𝑝
SAQP
Lithography
Deposition
Etch
CORP IR / 2019.07.31 42
EUV adoption will solve sophisticated technological hurdles our customers
face (i.e. placement errors), bringing about quite positive effects on
semiconductor and SPE industries
– Advance miniaturization
– Accelerate customers’ investment in next generation technologies by enhancing the yield
Further miniaturization led by EUV will create more differentiation of our
products and business opportunities
– Increase our coater/developer market share even further
– Expand demand for etch, deposition and cleaning equipment
– Differentiate our product through advancing self-aligned patterning technology
– Expand business with process integration, leveraging our robust product lineup
Effects of EUV Lithography Adoption
CORP IR / 2019.07.31 44
HARC process
– SAM will increase due to advancement of 3D NAND
and DRAM scaling
Patterning process
– Multi-patterning will continue to be used, even after the
adoption of EUV for mass production, and SAM will
remain at high levels
Interconnect/contact process
– SAM will grow due to adoption of copper dual
damascene interconnects for DRAM and increasing
number of logic interconnects layers
Critical conductor process
– Stable investment will continue despite low SAM ratio
Gas chemical etch process
– Growth trend for SAM due to introduction of 3D
structures in devices
Etch System SAM Outlook
10.8
12.1
10.1
13.3
15.5 15.8
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
CY'17 CY'18 CY'19 CY'20 CY'21 CY'22
HARC Patterning Interconnect/contact
Critical conductor Gas chemical etch Others
*TEL forecasts
($B)
Etch system SAM by process type*
CORP IR / 2019.07.31 45
HARC process– 3D NAND (multi-level contact, word line isolation), DRAM (capacitor):
Continue to differentiate through process performance and productivity
– 3D NAND (channel): Launch new systems that can
differentiate by providing both precise process controllability
and even higher productivity
Patterning process– DRAM: Reduce customer production costs by combining
etch steps
– Logic: Differentiate through integration of etch and deposition
technologies
Interconnect/contact process– Apply knowledge cultivated in logic to DRAM
Gas chemical etch process
– Create a new market through plasma assist technology
Etch System Strategy
Word line
isolation (slit)Channel
Multi-level
contact
Capacitor
Interconnects
Isotropic etch
Nanosheet image:
Courtesy of IBM
Source: N. Loubet, et al., Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET
CORP IR / 2019.07.31 47
Deposition System SAM Outlook
Deposition system SAM by application*
4.5
5.0
3.9
5.2
5.86.1
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
CY'17 CY'18 CY'19 CY'20 CY'21 CY'22
NAND DRAM Logic/Foundry
NAND
– Investment for 3D NAND scaling will continue.
Particularly, demand for high quality dielectric film,
mainly with ALD, is increasing for high aspect ratio
step
DRAM
– Scaling will continue. Investment is expected in new
structures and materials to improve capacitor
performance
Logic/Foundry
– SAM ratio will decrease, but stable investment
expected. Continued demand for technological
innovation to suppress resistance increase in thin
wire
($B) * TEL forecasts
CORP IR / 2019.07.31 48
Dia: 20nm, AR = 50:1
To
pB
ott
om
Deposition Business Strategy
• Lower temperatures
• High-k dielectric film
• Capacitor electrode
DRAM 3D NAND• Channel silicon film
• Charge trap film
• Block high-k dielectric film
• Buried oxide film
• Buried silicon film
TELINDY PLUSTM Super Large Batch
100/125 150/175
NT333TM
N2
N2
Si precursor
Oxidation
Modification
Triase+™ EX-II ProTM TiN
S/C >95%
Gap-fill SiO2 Dep
Provide high value-added technology by leveraging our
advantage of having batch, semi-batch and single wafer
technologies
Vertical Furnace Semi-batch SystemSingle-wafer System
Equipmentstability
Improved productivity/coverage
Highertempera-
ture
Continuousthin film/
film qualityimprovement
AR ≃ 16:1
CORP IR / 2019.07.31 50
3.0
3.4
2.9
3.63.8
4.0
0.0
1.0
2.0
3.0
4.0
5.0
CY'17 CY'18 CY'19 CY'20 CY'21 CY'22
Single wafer cleaning Batch cleaning Scrubber cleaning
No significant changes to SAM ratios for
cleaning systems
Single wafer cleaning
– Will continue to be the largest market
– Technological innovation aimed at reducing
defects and improving etch/drying performance
will continue
Batch cleaning
– Demand will continue in the market for wet etch
for 3D NAND critical processes
Scrubber cleaning
– The importance of physical back/bevel cleaning
is increasing in pre-lithography process and
other areas
Cleaning System SAM Outlook
($B)
Cleaning system SAM
by system type*
* TEL forecasts
CORP IR / 2019.07.31 51
Single wafer cleaning
– Bevel wet etch• Expect annual market growth rate of around 10%
• Contribute to improving customers’ yields.
Maintain a high market share by differentiating
through performance in precisely removing film from
the outer part of the wafer
– Prevent pattern collapseExpand market share by TEL original technology to
reduce collapse of high aspect ratio pattern
– Metal etchLaunched new dedicated SPM chambers for controlling
selectivity for metal in order to solve reduced yield
issues caused by dry etch damage and residue
Single Wafer Cleaning Strategy
Conventional drying
technologyNew drying technology
Pattern collapses occur No collapse
Metal etch process
Without bevel wet etch With bevel wet etch
W W W WTiN TiN
CORP IR / 2019.07.31 52
Batch and Scrubber Cleaning Strategy SiN etch process
Wafer back and defocus diagram
Wet
etch
Selectivity to SiO2
Uniformity Batch cleaning
– SiN etch and W etch processes for 3D NANDFocus on processes that require long durations
and advanced process technology. Differentiate by
realizing high uniformity, high selectivity and high
productivity in wet etch
Scrubber cleaning
– Pre-lithography processProvide high-value solutions such as reducing
particles brought in by wafers, contributing to the
improvement of exposure tool availability which
have grown increasingly important due to the
introduction of EUV
539
787
1 10
500
1,000
Nitride Oxide
Before
After
Total focus spot count (>50nm)
Small particles
Embedded particles Surface particles
CORP IR / 2019.07.31 54
Financial Summary
FY2018 FY2019YoY
Change
(Reference)
FY2019 estimates
announced on
Oct. 31, 2018
Net sales 1,130.7 1,278.2 +13.0% 1,280.0SPE 1,055.2 1,166.7 +10.6% 1,169.8
FPD 75.0 111.2 +48.2% 110.0
Gross profitGross profit margin
475.042.0%
526.141.2%
+10.8%-0.8pts
528.041.3%
SG&A expenses 193.8 215.6 +11.2% 219.0Operating incomeOperating margin
281.124.9%
310.524.3%
+10.5%-0.6pts
309.024.1%
Income before income taxes 275.2 321.5 +16.8% 315.0Net income attributable to
owners of parent204.3 248.2 +21.5% 237.0
EPS (Yen) 1,245.48 1,513.58 +21.5% 1,445.13
R&D expenses 97.1 113.9 +17.4% 116.0
Capital expenditures 45.6 49.7 +9.1% 51.0
Depreciation and amortization 20.6 24.3 +18.0% 26.0
(Billion yen)
1. In principle, export sales of Tokyo Electron’s mainstay semiconductor and FPD production equipment are denominated in yen. While some settlements are denominated
in dollars, exchange risk is hedged as forward exchange contracts are made individually at the time of booking.
2. Profit ratios are calculated using full amounts, before rounding.
SPE: Semiconductor production equipment, FPD: Flat panel display production equipment
CORP IR / 2019.07.31 55
93 91
7 9
0%
50%
100%
FY'18 FY'19
1,055.2
1,166.7
314.6 326.7
29.8%28.0%
0%
10%
20%
30%
40%
50%
60%
0
400
800
1,200
1,600
FY'18 FY'19
Segment Information
75.0
111.2
13.2
24.2
17.7%
21.8%
0%
10%
20%
30%
40%
50%
60%
0
40
80
120
160
FY'18 FY'19
SPE
FPD
SPE(Semiconductor Production Equipment)
FPD(Flat Panel Display Production Equipment)
(Billion Yen) (Billion Yen)
Composition of Net Sales
Sales
Segment income
Segment profit margin
Sales
Segment income
Segment profit margin
1. Segment income is based on income before income taxes.
2. R&D expenses such as fundamental research and element research are not included in above reportable segments.
3. Composition of net sales figures is based on the sales to customers.
CORP IR / 2019.07.31 56
(Billion Yen)
In FY2019 in memory, steady investment for
increasing production capacity and cutting-
edge technologies accompanied strong
demand for servers
In logic/foundry, investment continued for
the 14nm and subsequent generations
SPE Division: New Equipment Sales by Application
24%25% 21%
31%11% 10%
28%
40% 38%
17%
24%31%
550.3
814.6
888.7
0
400
800
1,200
FY'17 FY'18 FY'19
DRAM
Non-volatile memory
Logic foundry
Logic & others (MPU, AP, Others)
CORP IR / 2019.07.31 57
Sales grew in FY2019 in coater/developer
and etch systems
SPE Division: New Equipment Sales by Product
2% 1% 1%6% 6% 7%11%
10% 9%22%
23% 20%
34%
40% 40%25%
20%23%
550.3
814.6
888.7
0
400
800
1,200
FY'17 FY'18 FY'19
Coater/Developer
Etch system
Deposition system
Cleaning system
Wafer prober
Others
(Billion Yen)
CORP IR / 2019.07.31 58
115.0
150.0
188.8
93.0
101.0
99.4
208.0
251.0
288.2
0
100
200
300
FY'17 FY'18 FY'19
FY2019 sales were ¥288.2 billion,
+15% YoY. Parts sales especially grew
due to an increase in installed base and
comprehensive service contracts
Field Solutions Sales
Used equipment and modification
Parts and services
(Billion Yen)
* FY2017 sales figures have been rounded.
CORP IR / 2019.07.31 59
Financial Summary
FY2019 FY2020
Q1 Q2 Q3 Q4 Q1vs. Q4
FY2019
Net sales 295.5 395.4 268.1 319.0 216.4 -32.2%
SPE 280.4 358.0 239.5 288.7 198.1 -31.4%
FPD 15.1 37.3 28.5 30.1 18.2 -39.6%
Gross profitGross profit margin
122.441.4%
161.640.9%
109.740.9%
132.241.5%
89.841.5%
-32.1%+0.0pts
SG&A expenses 50.0 58.6 51.0 55.8 47.3 -15.3%
Operating incomeOperating margin
72.424.5%
103.026.0%
58.721.9%
76.424.0%
42.519.7%
-44.3%-4.3pts
Income before income taxes 75.2 105.8 60.5 79.8 44.5 -44.2%
Net income attributable to
owners of parent55.7 79.5 48.8 64.1 31.8 -50.2%
R&D expenses 26.1 31.2 26.5 30.0 25.6 -14.6%
Capital expenditures 9.6 13.2 11.8 14.9 7.6 -49.0%
Depreciation and amortization 5.0 5.6 6.2 7.3 6.0 -17.1%
1. In principle, export sales of Tokyo Electron’s mainstay semiconductor and FPD production equipment are denominated in yen. While some settlements are denominated
in dollars, exchange risk is hedged as forward exchange contracts are made individually at the time of booking.
2. Profit ratios are calculated using full amounts, before rounding.
(Billion Yen)
SPE: Semiconductor production equipment, FPD: Flat panel display production equipment
CORP IR / 2019.07.31 60
280.4
358.0
239.5
288.7
198.1
78.3
105.8
60.7
81.7
46.4
27.9%29.6%
25.4%
28.3%
23.5%
0%
10%
20%
30%
40%
50%
0
80
160
240
320
400
Q1FY'19
Q2 Q3 Q4 Q1FY'20
Segment Information
15.1
37.3
28.5 30.1
18.2
2.4
9.5
5.8 6.4
3.5
16.2%
25.5%
20.5% 21.2%19.2%
0%
10%
20%
30%
40%
50%
0
8
16
24
32
40
Q1FY'19
Q2 Q3 Q4 Q1FY'20
95 91 89 91 92
5 9 11 9 8
0%
50%
100%
Q1FY'19
Q2 Q3 Q4 Q1FY'20
SPE(Semiconductor production equipment)
FPD(Flat panel display production equipment)
Composition of Net Sales
(Billion Yen) (Billion Yen)
Sales
Segment income
Segment profit margin
Sales
Segment income
Segment profit margin
SPE
FPD
1. Segment income is based on income before income taxes.
2. R&D expenses such as fundamental research and element research, etc. and other general and administrative expenses are not included in the above reportable segments.
3. Composition of net sales figures is based on the sales to customers.
CORP IR / 2019.07.31 61
SPE Division: Sales by Region
221.9
265.7241.4
326.0
280.4
358.0
239.5
288.7
198.1
0
100
200
300
400
2017… 2017… 2017… 2018… 2018… 2018… 2018… 2019… 2019…
(Billion Yen)
Q1
FY’18
Q2 Q3 Q4 Q1
FY’19
Q2 Q3 Q4 Q1
FY’20
Japan 26.7 38.4 35.1 45.1 51.1 58.0 54.0 42.7 32.5
North America 24.0 32.0 29.1 33.9 28.4 45.9 22.7 34.7 28.5
Europe 25.3 26.9 19.6 25.0 17.7 31.3 18.6 25.3 20.2
South Korea 68.3 101.7 79.4 122.3 88.9 86.5 60.9 68.9 36.9
Taiwan 45.8 36.6 42.1 44.3 26.3 48.0 29.3 59.1 48.3
China 26.7 23.0 22.6 31.8 54.9 71.3 38.0 42.5 27.0
S. E. Asia, Others 4.6 6.7 13.2 23.4 12.7 16.8 15.6 15.2 4.4
CORP IR / 2019.07.31 62
SPE Division: New Equipment Sales by Application
29%
20%
30%
21%
25%
23%
27%
25%
38%
17%
22%
23%
18%
31%
32%
19%
12%
31%
32%
25%
16%
24%
34%
26%
22%
27%
27%
24%
17%
40%
16%
27%
DRAM
Non-volatile memory
Logic foundry
Logic & others
(MPU, AP, Others)
(Billion Yen)
Percentages on the graph show the composition ratio of new equipment sales. Field Solutions sales are not included.
25%
23%
27%
25%
38%
17%
22%
23%
18%
31%
32%
19%
12%
31%
32%
25%
16%
24%
34%
26%
22%
27%
27%
24%
17%
40%
16%
27%
25%
35%
8%
32%
27%32%
26% 19% 17%23%
18%26% 33%
16%8%
12% 10%4%
11%
9%
15%26%
40%35%
41%
43%
49%
36%
45%
24%
15%
17%
25%21%
28%
30%
30%
28%
35%
26%
169.7
204.3
181.7
258.8
219.7
284.5
169.8
214.5
130.6
0
50
100
150
200
250
300
Q1FY'18
Q2 Q3 Q4 Q1FY'19
Q2 Q3 Q4 Q1FY'20
CORP IR / 2019.07.31 63
Field Solutions Sales
54.4
64.462.1
70.0
63.2
76.1 72.5 76.369.6
0
20
40
60
80
Q1
FY’18
Q2 Q3 Q4 Q1
FY’19
Q2 Q3 Q4 Q1
FY’20
SPE Sales 52.2 61.4 59.7 67.2 60.6 73.4 69.6 74.2 67.4
FPD Sales 2.2 2.9 2.4 2.8 2.5 2.7 2.8 2.1 2.1
(Billion Yen)
CORP IR / 2019.07.31 64
119.1 115.4 109.5 115.6 117.217.2 17.1 9.9 9.0 8.8
131.2 139.9 142.2 150.0 151.9
28.7 42.7 55.489.0 53.0
381.6 344.0 368.2354.2 381.0
151.3 155.3 144.7146.9
96.3
355.5 423.7 341.1392.6
340.8
1,185.0 1,238.51,171.4
1,257.6
1,149.3
Q1FY'19
Q2 Q3 Q4 Q1FY'20
Balance Sheet
772.3849.5 821.9
888.1819.3
412.7388.9
349.5
369.5
330.0
1,185.01,238.5
1,171.41,257.6
1,149.3
Q1FY'19
Q2 Q3 Q4 Q1FY'20
Assets Liabilities & Net Assets
(Billion Yen) (Billion Yen)
* Cash and cash equivalents: Cash and deposits + Short-term investments, etc. (Securities in B/S).
Liabilities
Net assets
Other current assets
Tangible assets
Intangible assets
Cash & cash
equivalents*
Inventories
Trade notes, accounts
receivables
Investment & other assets
CORP IR / 2019.07.31 65
Turnover days = inventory or accounts receivable at the end of each quarter / last 12 months sales x 365
Inventory Turnover and Accounts Receivable Turnover
216.4
57 54 54 52 46 43 40 42
29
110 107
117 111
117
96 102 101
116
0
40
80
120
160
0
100
200
300
400
Q1FY'18
Q2 Q3 Q4 Q1FY'19
Q2 Q3 Q4 Q1FY'20
(Billion Yen)
Net sales
Accounts receivable turnover
Inventory turnover
(Days)
CORP IR / 2019.07.31 66
Cash Flow
59.4
-8.5
-99.9
50.9
-120
-90
-60
-30
0
30
60
90
120
Q1
FY’18
Q2 Q3 Q4 Q1
FY’19
Q2 Q3 Q4 Q1
FY’20Cash flow from operating activities 24.4 43.4 30.4 88.1 51.4 84.0 -11.0 65.0 59.4
Cash flow from investing activities*1 -9.3 -9.4 -15.2 -12.8 -12.1 -12.2 -1.1 -14.4 -8.5
Cash flow from financing activities -36.8 -0.0 -45.7 -0.0 -56.9 -5.0 -67.8 -0.0 -99.9
Free cash flow*2 15.1 34.0 15.1 75.3 39.3 71.7 -12.1 50.5 50.9
Cash on hand*3 294.6 329.9 301.2 373.8 355.5 423.7 341.1 392.6 340.8
*1 Cash flow from investing activities excludes changes in deposits with periods to maturity of over 3 months.
*2 Free cash flow = cash flow from operating activities + cash flow from investing activities excluding changes in deposits with periods to maturity of over 3 months.
*3 Cash on hand includes the total of cash + deposits with periods to maturity of over 3 months.
(Billion Yen)
Share repurchase
-43.2
-56.7
CORP IR / 2019.07.31 67
Consolidated 10-year Financial Summary
* From FY2019, the Company adopts “Partial Amendments to Accounting Standard for Tax Effect Accounting” (ASBJ Statement No. 28, revision on
February 16, 2018). “Total assets” and "equity ratio" for FY2018 have been restated in the table in accordance with the revised accounting standard.
(Millions of Yen) FY2010 FY2011 FY2012 FY2013 FY2014 FY2015 FY2016 FY2017 FY2018 FY2019
Net Sales 418,636 668,722 633,091 497,299 612,170 613,124 663,948 799,719 1,130,728 1,278,240
Semiconductor production
equipment262,391 511,331 477,873 392,026 478,841 576,242 613,032 749,893 1,055,234 1,166,781
FPD production equipment 71,361 66,721 69,888 20,160 28,317 32,709 44,687 49,387 75,068 111,261
PV production equipment 3,805 3,617
Computer network 84,473 90,216 84,867 84,664 100,726
Electronic components
Other 410 453 461 448 479 555 6,228 438 425 197
Gross profit 108,316 234,758 211,444 158,754 201,892 242,773 267,209 322,291 475,032 526,183
Gross profit margin 25.9% 35.1% 33.4% 31.9% 33.0% 39.6% 40.2% 40.3% 42.0% 41.2%
SG&A expenses 110,496 136,887 151,001 146,206 169,687 154,660 150,420 166,594 193,860 215,612
Operating income -2,180 97,870 60,443 12,548 32,204 88,113 116,788 155,697 281,172 310,571
Operating margin -0.5% 14.6% 9.5% 2.5% 5.3% 14.4% 17.6% 19.5% 24.9% 24.3%
Ordinary income 2,558 101,919 64,046 16,696 35,487 92,949 119,399 157,549 280,737 321,662
-7,767 99,579 60,602 17,766 -11,756 86,827 106,466 149,116 275,242 321,508
-9,033 71,924 36,725 6,076 -19,408 71,888 77,891 115,208 204,371 248,228
Depreciation and amortization 20,001 17,707 24,197 26,630 24,888 20,878 19,257 17,872 20,619 24,323
Capital expenditures 14,918 39,140 39,541 21,773 12,799 13,183 13,341 20,697 45,603 49,754
R&D expenses 54,074 70,568 81,506 73,248 78,663 71,349 76,286 83,800 97,103 113,980
Interest-bearing debt 5,105 7,996 4,402 3,756 13,531 ― ― ― ― ―
Equity 511,818 572,741 586,789 593,032 578,091 639,483 562,369 643,094 767,146 880,748
Total assets 696,351 809,205 783,610 775,527 828,591 876,153 793,367 957,447 1,202,796 1,257,627
Debt-to-equity ratio 1.0% 1.4% 0.8% 0.6% 2.3% ― ― ― ― ―
Equity ratio 73.5% 70.8% 74.9% 76.5% 69.8% 73.0% 70.9% 67.2% 63.8% 70.0%
ROE -1.8% 13.3% 6.3% 1.0% -3.3% 11.8% 13.0% 19.1% 29.0% 30.1%
48,284 83,238 29,712 84,266 44,449 71,806 69,398 136,948 186,582 189,572
9,613 -35,881 -8,352 -141,769 -19,599 155,737 -150,013 -28,893 -11,833 -84,033
-287 -5,236 -27,334 -10,625 -186 -18,213 -138,600 -39,380 -82,549 -129,761
-50.47 401.73 205.04 33.91 -108.31 401.08 461.10 702.26 1,245.48 1,513.58
12 114 80 51 50 143 237 352 624 758
10,068 10,343 10,684 12,201 12,304 10,844 10,629 11,241 11,946 12,742
Net income per share
Cash dividends per share
Number of employees
Income before income taxes
Net income attributable to owners of
parent
Cash flow from operating activities
Cash flow from investing activities
Cash flow from financing activities
CORP IR / 2019.07.31 68
Disclaimer regarding forward-looking statement
Forecast of TEL’s performance and future prospects and other sort of information published are made based on information available
at the time of publication. Actual performance and results may differ significantly from the forecast described here due to changes in
various external and internal factors, including the economic situation, semiconductor/FPD market conditions, intensification of sales
competition, safety and product quality management, and intellectual property-related risks.
Processing of numbers
For the amount listed, because fractions are rounded down, there may be the cases where the total for certain account titles does not
correspond to the sum of the respective figures for account titles. Percentages are calculated using full amounts, before rounding.
Exchange risk
In principle, export sales of Tokyo Electron’s mainstay semiconductor and FPD panel production equipment are denominated in yen.
While some settlements are denominated in dollars, exchange risk is hedged as forward exchange contracts are made individually at
the time of booking. Accordingly, the effect of exchange rates on profits is negligible.
Disclaimer regarding Gartner data (Page 6, 7)
All statements in this presentation attributable to Gartner represent Tokyo Electron’s interpretation of data, research opinion or
viewpoints published as part of a syndicated subscription service by Gartner, Inc., and have not been reviewed by Gartner. Each
Gartner publication speaks as of its original publication date (and not as of the date of this presentation). The opinions expressed in
Gartner publications are not representations of fact, and are subject to change without notice.
FPD: Flat panel display
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