the lc-3 – chapter 5

The LC-3 – Chapter 5COMP 2620

Dr. James Money COMP 2620

1

The LC-3

So far, we’ve discussed the basic parts of a computer: memory, processing unit, control unit, I/O devices

We also looked at the six phases of the instruction cycle: FETCH, DECODE, EVALUATE ADDRESS, OPERAND FETCH, EXECUTE, and STORE RESULT

The LC-3

We now want to introduce a “real” computer, the LC-3

We are going to introduce the instruction set architecture (ISA) of the LC-3

We have looked at some of it before We will examine it now in a comprehensive

way

The LC-3

Recall the ISA is the interface between software commands and what the hard carries out

We will discuss the features of the LC-3 and now to write programs in LC-3’s own language – LC-3’s machine language

The ISA: Overview

The ISA specifies all the information about the computer the software has to be aware of

It tells you what commands you can issue Also used when you translate from a high

level language to machine language The ISA also specifies the memory

organization, registers, and instruction set

Memory Organization

The LC-3 memory has an address space of 216 locations and the addressability of 16 bits

Not all 65536 locations are used for memory We will discuss it further in Chapter 8 We refer to 16 bits as one word since the LC-

3 works 16 bit units We also say it is word-addressable

Registers

The LC-3 provides high speed temporary storage

This is because memory requires more than one machine cycle to access memory

The most common types of temporary storage is the general purpose register set

Each register in the set is called a general purpose register (GPR)

Registers

Registers have the same properties as memory for storing information

The number of bits available in each register is one word

That is, on the LC-3, they are 16 bits

Registers

Each register must be uniquely identifiable The LC-3 has 8 GPRs, each identified by a 3

bit register number They are referred to as R0, R1, R2,…,R7 Consider a snapshot of LC-3’s register set,

called a register file with values 1,3,5,6,-2,-4,-6,-8 stores in R0-R7 respectively

Registers

Register 0 (R0) 0000000000000001

Register 1 (R1) 0000000000000011

Register 2 (R2) 0000000000000101

Register 3 (R3) 0000000000000111

Register 4 (R4) 111111111111111110

Register 5 (R5) 111111111111111100

Register 6 (R6) 111111111111111010

Register 7 (R7) 111111111111111000

Registers

Recall the ADD instruction:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1

ADD R2 R0 R1

Registers

Register 0 (R0) 0000000000000001

Register 1 (R1) 0000000000000011

Register 2 (R2) 0000000000000100

Register 3 (R3) 0000000000000111

Register 4 (R4) 111111111111111110

Register 5 (R5) 111111111111111100

Register 6 (R6) 111111111111111010

Register 7 (R7) 111111111111111000

Instruction Set

An instruction is made of two parts:– Opcode – what the instruction does– Operands- what the instructions acts upon

The ISA is defined by the set of opcodes, data types, and addressing modes

The addressing modes determine where the operands are located

The ADD is an example of a register mode addressing mode

Opcodes

The number of opcodes vary considerably between different architectures

Some have a lot of opcodes, which other contain relatively few

For example, the HP Precision Architecture (HP-PA) has an instruction that combines multiply with add: (AxB)+C

Opcodes

The Intel x86 ISA has MMX instructions because they extend the ISA to help with multimedia

The decision on what instructions include are hotly debated usually at design time

Opcodes

The LC-3 has 15 instructions, each with a unique opcode

The opcode is specified in bits [15:12] of the instruction

Since there are 4 bits used, there are 16 possible opcodes

Code 1101 has been left unspecified for now

Opcodes

There are three different types of opcodes:– Operates – process information– Data movement – moves information between

registers and memory or input/output devices– Control – change sequence of execution

Opcodes

Data Types

A data type is a representation of information so the ISA has opcodes that operate on that representation

If the ISA has an opcode that operates on info represented by a data type, then we say the ISA supports the data type

The only support data type on the LC-3 is two’s complement integers

Addressing Modes

An addressing mode is a way of specifying where an operand is located

There are three places for operands:– Memory– Registers– Part of the instruction

Addressing Modes

If the operand is part of the instruction, we refer to it as a literal or immediate operand

The term literal comes from the fact the bits of the instruction literally form the operand

The term immediate comes from the fact we have the operand immediately – we do not look for it elsewhere

Addressing Modes

The LC-3 has 5 addressing modes:– Immediate– Register– Three memory addressing modes:

PC-relative Indirect Base+Offset

Condition Codes

All ISAs allow execution to change based on the result of a previous instruction

The LC-3 has three single bit that are set (1) or cleared (0) each time one of the GPRs are written to

Condition Codes

The three bit registers are– N – negative– Z – zero– P – positive

These correspond to whether the written result was positive, negative, or zero

Only one of them are set at any given time

Condition Codes

These three single registers are referred to as condition codes

They are called this since they are used by control instructions to influence sequence of execution