the dialog chip in the front-end electronics of the lhcb muon detector
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The DIALOG chip in the front-end electronics of the LHCb Muon
Detector
Outline• DIALOG in the LHCb experiment
• DIALOG features and internal scheme
* Programmable Delay and Digital Shaping: ADC-DLL
* Threshold DACs and Line Drivers for ASD chip
* Front-End Rate (and Noise) Monitors
• DIALOG layout organizationC. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
S. Cadeddu1, C. Deplano1,2, A. Lai1
1 INFN Cagliari Italy; 2 Università di Cagliari Italy
LHCb experiment LHCb: an experiment for precise
measurements of CP violation and B mesons rare decays
LHC Bunch Crossing frequency ~ 40 MHz (25 ns)
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
Muon Detector
25 ns
TIME DISTRIBUTION Each channel of the Muon Chambers can have a different delay Different BX
Time distribution not center inside the BX
Reasons
Particle time of flight
Different cables length
Time distribution width ~ 25 ns
EFFICIENCY
LOSS
BX ID
45 46 47 48 49 50 51 52 53 54 55
25 ns
INTERACTION
DETECTION
25 ns
25 ns
LHCb experiment
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
Muon Detector
MUON CHAMBER (MWPC/GEM)
F/E board
8 PCH
8 PCHASDASD
8 LCH
DIALOG
8 PCH
8 PCH
F/E board
DIALOG CUSTOM IC
DELAY AND WIDTH ADJUSTMENT
LOGICAL CHANNEL GENERATION
THRESHOLDS FOR ASD CHIPS
ASD: CARIOCA CHIP
ANALOG SHAPER DISCRIMINATOR
ON
DE
TE
CT
OR
E
LE
CT
RO
NIC
SI2C MASTER
LOW VOLTAGE
CONTROLS
CALIBRATION PULSES
SERVICE board(on
crates)
SYNCHRONIZATION
TIME (PHASE) MEASUREMENT
DATA FORMATTING
DATA TO MUON TRIGGER
OFF DETECTOR ELECTRONICS
10m cabling (LVDS)
DATA TO DAQ
RECONSTRUCTION
Counting Room
4000 ASD
8000 DIALOG
BX ID
45 46 47 48 49 50 51 52 53 54 55
25 ns
INTERACTION
DETECTION
SYNC ICNSS N33-
14
DIALOG features DIALOG (Diagnostic time Adjustment and
LOGics)
Programmable input signals time adjustment (31 steps of ~ 1.6 ns)
External selection or automatic calibration by DLL (settable period ~ 57 ns [17 MHz]÷ 21 ns [48 MHz])
Programmable output signals width adjustment (8 steps of ~ 3 ns each)
Mask on every input channel
Logical Channel generation
OR2; OR4; OR8;
AND2; OR2(2AND2); OR4(4AND2)
Sixteen 24 bits rate counters
18 different threshold signals for ASD
Internal Pattern generation
2 ASD pulse generation signals with programmable time adjustment
I2C interface (93 registers) to configure all DIALOG tools
Triple-voted and auto-corrected register for better SEU immunity (both configuration and state machines)
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
IBM 0.25 μm radiation tolerant technology
16 LVDS input channels
8 LVDS output channels
DIALOG Internal Scheme
16 LVDSinput Prog.
Delayer
Prog.Dig.
Shaper
MASK
LogicalChannel
Generation
8 LVDSoutput
I2CInterface
SCL
SDA
DIALOGConfiguration
registers
CAlibDLL&
ADC DLL
Address
16 x 24 bitsRate
counters
Tst Signal
Pls0
Pls1
ASD pulse generation
& Delay
ThrDAC 1
ThrDAC 16
Threshold1
Threshold16
Calibration CLK
Pulse
Start/Stop
… ThrDAC 1
ThrDAC 2
Threshold1
Threshold2
CARIOCAASDQ
Internal pattern
MU
X
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
Programmable Delay and ShapingProgrammable input signals
time adjustment (31 steps of ~ 1.6ns @ 40MHz)
External selection or automatic calibration by ADC-DLL
Typical max delay ~ 50 ns
Max possible delay ~ 120 ns (@ 18 MHz)
DNL (peak to peak) < ± 0.25 LSBProgrammable output signals Digital Shaping (8 steps of ~ 3.2ns each @ 40MHz)
Typical shaping ~ 25 ns
Important to adjust the variable time width of signals (time over threshold) to the constant width of one BX cycle
DNL (peak to peak) < ± 0.2 LSBBoth uses the same VCDL
External selection or automatic calibration (ADC-DLL)
pulse from CARIOCA
25 ns
50 ns
PCH15
PCH9
PCH1
DIALOG outputs delayed by 25ns one with respect to the otherTime Re-aligned and shaped
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
Calibration DLL
Vctrl (after locking) ADCRef Clock
Code in
8 VCDL (matched to calibration DLL)
VCDL 1
VCDL 2
VCDL 3
VCDL 8
Vctrl
SAR andcontrols
REG
DAC
Controls
Code
From I2C
Comparator
Vout
Reference Clock is input only during specific calibration (initialization) runs Locking time is < 500 ns and Conversion time is ~ 2 μs Locking range ~ 57 ns [17 MHz]÷ 21 ns [48 MHz] Temperature Effect: 1 ns for 20 °C (50 ps/°C)
DIALOG ADC-DLL
DIALOG Thresholds Setting Tools 2 ASD threshold setting blocks
consisting of :
8 DAC + buffer for CARIOCA
DAC: resolution 8 bit, range (625 m ÷1.2) V
Linear output driver (Rin CARIOCA ~ 24 kΩ) good linearity and uniformity for RLoad > 6.8 kΩ
DNL (peak to peak) < ± 0.5 LSB
1 DAC + buffer for ASDQ
DAC: resolution 8 bit, range (0 ÷625 m) V
Linear output driver (Rin ASDQ ~ 1 kΩ)
good linearity and uniformity for RLoad > 1 kΩ
DNL (peak to peak) < ± 0.5 LSB
1 voltage divider + 2 buffers to give the correct voltage range to DAC
Linear output driver (Rin ~ 1 kΩ)
DAC
Buffer CARIOCA
Buffer ASDQ
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
DIALOG Thresholds Setting Tools
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0 50 100 150 200 250 300
DIALOG code
DNL
0
5
10
15
20
25
30
35
-1 -0.5 0 0.5 1
DNL
coun
ts
Channels profile
LSBcalculated
ncalculated
nmeasured
V
VV
DNL
600
700
800
900
1000
1100
1200
0 50 100 150 200 250
DIALOG code
AD
C c
on
vert
ion
(m
V)
625 mV
1230 mV
Max spread is 24 mV
64 threshold channels
CARIOCA thresholds scan: 16 x 4 chip = 64 channelsGood Linearity and UniformityDNL profile C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
DIALOG front-end Rate Monitors 2 Scaler blocks (one for each ASD chip) consisting of:
a 24 bits rate counter with triple-voted (TV) registers (1 channel out of 8 at a time)
seven 24 bits rate counters (one for each channel 1 ÷ 7) for test mode
Read and reset by I2C interface
24 bit counter TV
24 bit counter
24 bit counter
24 bit counter
24 bit counter 24 bit counter
24 bit counter
24 bit counter
Mux
I2C selector
PCH 2
PCH 4
PCH 6
PCH 8
PCH 10
PCH 12
PCH 14
PCH 0
PCH 2
PCH 4
PCH 6
PCH 8
PCH 10
PCH 12
PCH 14
I2
C
Mux out TV out
out 14
out 2
out 4
out 6
out 8
out 10out 12
Scaler Block for PCH EVEN
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
DIALOG layout and pinout
gnd
gnd
9 ASD threshold
9 ASD threshold
gn
d
vdd
vdd
vdd
vdd
gnd
gnd
gn
d
vdd
vdd
vdd
vdd
vdd
gn
dg
nd gn
d
gnd
vdd
8 LVDS Physical Channel
LVDS ASDQ pulse
8 LVDS logical channel
CARIOCA pulse
CARIOCA pulse
8 LVDS Physical Channel
LVDS ASDQ pulse
LVDS I2C in
LVDS I2C out
Reset
Address113 pin
width 3875 m
length 4900 m
core
Scale
rs
Scale
rs
thre
shol
ds
thre
shol
ds
DLL ADC
DLL ADC
Pu
lse +
Dela
y L
ines
Pu
lse +
Dela
y L
ines
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
Power consumption ~ 50 mA at bias voltage 2.5 V
Radiation Test OK:
* 250 MeV proton at PSI W/R I2C registers
* Cs 137 (γ ~ 661 keV ) 1 Mrad (equivalent dose for 10 year of LHCb)
Conclusion
DIALOG 1.0 was completely tested under operating conditions (detector MWPC + front-end board CARDIAC)DIALOG 1.0 is fully working and is under production at IBM
C. Deplano - INFN Cagliari Italy– IEEE Rome 19/10/04
DIALOG TB BOARD
CARDIAC FRONT-END BOARD
MWPC FULLY EQUIPPED
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