scott williams

Scott WilliamsOBJECTIVE:Seeking a challenging and rewarding contracts in ASIC/FPGA Design & VerificationEXPERIENCE SUMMARY: Overall experience of over 10 years in ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in SystemC and verified the TCP RTL implementation Designed and Verified ZBT SRAM and Flash interface for LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and Synthesised the same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of a Smart Card ASIC Participated in the development of a VHDL SimulatorSKILL SET: Languages :VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators :NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers :Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers:Denali Pure View Foundry Tools :Samsung s Foundry tools Cubicware Protocols :TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISAEDUCATION:M.S. Electrical and Electronics EngineeringPROFESSTIONAL EXPERIENCE: Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the same. Verified the RTL implementation of TCP/IP Stack. A detailed test plan was created and SystemC models of the functional blocks were written to test the whole of TCP/IP Implementation. Designed and verified the LEXRA RISC Processor Interface with the functional blocks and verified the same. Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor. Integrated all functional RTL modules and created a system level top. Perl scripts where written to manage the files and test cases. Created the Vera testbench environment for the whole chip.SPI-4 Core: Modified the SPI-4 soft core both on the Sink and Source data paths. Synthesized the modified RTL code on Synplifypro and implement the netlist on Xilinx Implementation tools targeting to Xilinx virtex II series. Verified the RTL and post layout netlist for functionality and timing.Ingress FPGA for line card: Designed and implemented the Network Processor interface on the Ingress traffic flow towards the Switch fabric. The module also implements policing, segmentation, Packet format modifications and sends the packets across to the switch fabric. Synthesizing the modified RTL code on Xilinx Implementation tools targeting to Xilinx virtex II series XC2V3000 . Gate count of the complete Ingress FPGA 1,800,000 gates. Modified the Accelar Simulation Environment Nortel functional simulation environment used for Verification used the same to verify the modified RTL code and synthesized gate level netlist. The job involved understanding the Accelar simulation environment and modifying the same in accordance with the new requirement. Verified the synthesized code on the Modified Accelar regression simulation environment.Trojan ASIC - USB Smart Card Solution: Synthesized the DesignWare 8051 of Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Designed testbench to test the DesignWare 8051 functionality. Mapped to whole design to XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post-layout simulations were done on MODELSIM simulation environment. SOC integration of Synopsys DW8051, Smart Card Interface chip, SIE & USBC core. Project managed the whole simulation work of the USB-Smart Card. Enhanced already present Smart Card Device Model. Responsible for testing & debugging of the functionality of the design.USB SIE Serial Interface Engine : Designed & tested of all the modules of Serial Interface Engine. Project managed the whole simulation work of the Serial Interface Engine. Integrated the SIE with the USBC and Mapped the whole design to XILINX FPGA - 4000XL series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment. Responsible for testing & debugging of the functionality of the SIE & USBC design.Ultimate - VHDL simulator conforming to IEEE VHDL specification : Took part in the kernel development of the simulator. Design and implemented an intermediate format for the simulator. Wrote extensive test cases to test the various constructs and expressions of VHDL according to SPEC defined by IEEE.References Furnished Upon Request.Up