sap 1
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Simple As Possible -1 (SAP-1)
Computer Architecture 20
04
SAP-1 Characteristics
• Hardwire Architecture• 2 8-bit general registers• 1 8-bit output registers• 4-bit ALU (additional, subtraction)• 4-bit instructions and 4-bits operands
– (cccc oooo)• cccc = OP CODE• oooo = OPERAND
• 16x8 address ROM for mixed program and data• 12 control signals
SAP-1Architecture Program Counter
(PC)4
8
(Memory Address Register)
MAR4
16x8 PROM
Instruction Register (IR)
8
4
8
Aregister
Arithmetic Logic UnitALU
Bregister
8
8
8Outputregister
Control UnitCON
Binary DisplayD
8
8
44 8
12
CpEpLmEr LiEiLaEa SuEuLbLo
Cp
CLKCLREp
CLRCLK
CLK
CLK
CLK
CLK
CLK
CLR
Lm
Er
Li
Ei
La
Ea
Su
Eu
Lb
8
8
Lo
Program Counter
Program Counter(PC)
4
Cp
CLKCLREp
D0
D1
D2D3
D0
D1D2
D3
Q0
Q1Q2
Q3
UCLK
DCLK
OECE
LOADRESET
MIN
MAXCNT UP RCO
U1
COUNT ER_4
CLK
Cp
CLR
Ep
D[0
..3
] • OUTPUT: 0000-1111 (0-F)
• CLK: Clock cycle
• CLR: reset output to 0000
• Cp: (PC) (PC)+1
• Ep: output (PC)
MAR
• INPUT: 8 bits (cccc oooo)
• OUTPUT: 4 bits (cccc)
• CLK: Clock cycle
• Lm:
– (MAR) input
– output HiByte(MAR)
(Memory Address Register)
MAR8
4
CLK
Lm
D0D1
D2
D3D2D3
D0D1
RESET
DL
Q0Q1
Q2Q3
QU
QL
LOAD
HOLD
UP
CLK
DU
OE
U2
SHIFT REG_4
CLK
Lm
D[0
..3
]
Q[0
..3
]
ROM (R)
D0D1
D2
D3D4
D5D6
D7
A0A1
A2
A3
A0A1
A2A3
A4
A5A6
A7A8
A9
A10A11
CS
W R
RD
D0D1
D2D3
D4
D5D6
D7
U3
MEMORY_12_8
FILE=PROM.BIN,ASCHEX
Vcc
Er
D[0
..7
]
A[0
..3
]
16x8 PROM 8
4
Er
• INPUT: 4 bits (cccc)
• OUTPUT: 8 bits (dddd dddd)
• Er:
– R input
– output (R)
B,O Register (tri-state)
X[0..7]
Y[0..7]
LiEi
CLR
CLK
D2D3
D4D5
D6
D7
D0
D1
RESET
DLQ0
Q1
Q2Q3
Q4Q5
Q6
Q7QU
QL
LOAD
HOLDUP
CLK
DU
OE
D[0..7] Q[0..7]
U51
SHIFT REG_8_BUS
Bregister
8 CLK
Lb
8
• INPUT: 8 bits (dddd dddd)
• OUTPUT: 8 bits (dddd dddd)
• CLK: Clock cycle
• Lx: Load data in
– (A) input
• Ex: Enable data out
– output (A)
I Register• INPUT: 8 bits
• OUTPUT1: 8 bits – For ALU, direct output
• OUTPUT2: 8 bits– For BUS, control by Ea
• CLK: Clock cycle
• La: Load data in
– (A) input
• Ea: Enable data out
– output2 (A)
Instruction Register (IR)
4
8
4
CLRCLK
Li
Ei
Aregister
8
8
8
CLK
La
Ea
• INPUT: 8 bits (cccc dddd)
• OUTPUT1: 4 bits (cccc)– For instruction decoder, direct output
• OUTPUT2: 4 bits (dddd)– For BUS, control by Ei
• CLK: Clock cycle
• Li: Load data in
– (IR) input
• Ei: Enable data out
– output2 (IR)
ALU
Arithmetic Logic UnitALU
8
Su
Eu
8
8
Binary Display
Binary DisplayD
8
• INPUT1: 8 bits (aaaa aaaa)• INPUT2: 8 bits (bbbb bbbb)• OUTPUT: 8 bits (dddd dddd)• Su: Load data in
– 0 – additional• (ALU)input1+input2
– 1 – subtraction• (ALU)input1-input2
• Eu: Enable data out– output (ALU)
• INPUT: 8 bits (aaaa aaaa)
Control Unit (CON)• COMPONENTS
– Ring Counter• T0 – T5
– Instruction Decoder• 6 op-code signals
– Control Matrix• 12 control signals
I7I6I5I4
ID
INSTRUCTION DECODER
LDAADDSUBOUTHLT
I7I6I5I4
CM
CONTROL MATRIX
RC
RING COUNTER
LDAADDSUBOUT
LoLbEuSu
EaLaEiLi
ErLmEpCp
T[0..5]
T[0..5]
CLKCLR
LoLbEuSu
EaLaEiLi
ErLmEpCp
HLT
CLKCLR
I[4..
7]
CLOCK• Press START to begin
– Generate CLK– Generate CLR
• HLT Signal– Reset system to Initial state
CLKCLR
CLOCK
CLOCK GENERATOR
CLKCLR
CLK1
CLR1 HLT
Vcc CLOCK(CLK1)
START2
START1
START
U101
AND
CLK
START1
HLT
CLR
CLR1
CLK1
CLK
Q!Q
RESET
JKSET
U19
JKFF
CLK
Q!Q
RESET
JKSET
U20
JKFF
START2
OPCODE• LDA (0000 oooo)
– 0000 1001 = LDA (R9)• (A) (R9)
• ADD (1111 oooo)– 0001 1010 = ADD (RA)
• (B) (RA)• (A) (A)+(B)
• SUB (0010 oooo)– 0010 1100 = SUB (RC)
• (B) (RC)• (A) (A) – (B)
• OUT (1100 xxxx)– 1100 xxxx = OUT
• (D) <- (A)• HLT (1111 xxxx)
– 1111 xxxx = HLT
PROGRAM/DATA MEMORY
R0 - 0000 1001 (LDA R9)R1 - 0001 1010 (ADD RA)R2 - 0001 1011 (ADD RB)R3 - 0001 1100 (ADD RC)R4 - 0010 1101 (SUB RD)R5 - 1110 xxxx (ADD RA)R6 - 1111 xxxx (ADD RA)R7 - xxxx xxxxR8 - xxxx xxxxR9 - 0001 0000 (16)RA - 0001 0100 (20)RB - 0001 1000 (24)RC - 0001 1100 (28)RD - 0010 0000 (32)RE - xxxx xxxxRF - xxxx xxxx
Ring Counter
CLK
T0 T1 T2 T3 T4 T5
T0
T1
T2
T3
T4
T5
RC
RING COUNTER
T[0..5]
CLKCLR
CLKCLR
Machine Cycle
• Fetch Cycle (T0-T2)• Execute Cycle (T3-T5)
CLK
T0 T1 T2 T3 T4 T5
Fetch Cycle Execute Cycle
Machine Cycle
Fetch Cycle
– T0• EpLm CON• (MAR) (PC)
– T1• ErLi CON• (IR) (RMAR)
– T2• Cp CON• (PC) (PC)+1
Execute Cycle
• LDA– T3
• LmEi CON• (MAR) (oooo)
– T4• ErLa CON• (A) (Roooo)
– T5• No op
• ADD– T3
• LmEi CON• (MAR) (oooo)
– T4• ErLb CON• (B) (Roooo)
– T5• LaEu CON• (ALU) (A)+(B)• (A) (ALU)
Execute Cycle
• SUB– T3
• LmEi CON• (MAR) (oooo)
– T4• ErLb CON• (B) (Roooo)
– T5• LaSuEu CON• (ALU) (A)+(B)• (A) (ALU)
• OUT– T3
• EaLo CON• (O) (A)
– T4• No Op
– T5• No Op
• HLT– T3
• HLT signal
CONTROL UNIT (CON)
CLOCK CONTROL
Instruction decoder Control Matrix
Ring Counter
4
612
HLT
CLK
CLR
4
Instruction
CON
Instruction Decoder
U4NOT
U5NOT
U6NOT
U7NOT
U8
AND_4
U9
AND_4
U10
AND_4
U11
AND_4
U12
AND_4
LDA
ADD
SUB
OUT
HLT
I7 I6 I5 I4
CONTROL MATRIXT
5
T1
T4
T3
T0
T2
T[0..5]
U23AND
U24AND
U26AND
U27AND
U29AND
U30AND
U31AND
U33AND
U34AND
U36AND
U37AND
LDAADDSUBOUT
U40OR_4 U41
OR_4
U42OR_3
U43OR_3
U44OR
U45OR
Cp
Ep
Lm E
r
Li
Ei
La
Ea
Su
Eu
Lb
Ld
Operation samplePROGRAM/DATA MEMORY
R0 - 0000 1001 (LDA R9)R1 - 0001 1010 (ADD RA)R2 - 0001 1011 (ADD RB)R3 - 0001 1100 (ADD RC)R4 - 0010 1101 (SUB RD)R5 - 1110 xxxx (ADD RA)R6 - 1111 xxxx (ADD RA)R7 - xxxx xxxxR8 - xxxx xxxxR9 - 0001 0000 (16)RA - 0001 0100 (20)RB - 0001 1000 (24)RC - 0001 1100 (28)RD - 0010 0000 (32)RE - xxxx xxxxRF - xxxx xxxx
Press start button(PC) 0000 Start
LDA R9(MAR) (PC) fetch TO (MAR)= 0000R(MAR) 0000 1001 (R) = (R0)IR 0000 1001 fetch T1 (PC) (PC)+1 fetch T2 (PC) = 0001(MAR) IR(low) exec T3 (MAR)= 1001(A) R(MAR) exec T4 (A) = (R9)NOOP exec T5
ADD RA(MAR) (PC) fetch TO (MAR)= 0001R(MAR) 0001 1010 (R)= (R1)IR 0001 1010 fetch T1(PC) (PC)+1 fetch T2 (PC) = 0010(MAR) IR(low) exec T3 (MAR)= 1010(B) R(MAR) exec T4 (B)= (RA)(A) (A)+(B) exec T5 (A)= 16+20
ADD RB...
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