low power

Low Power Illinois Scan Architectures

Guide:Prof. Virendra Singh

Presented by:Binod KumarM.Tech,EE

Outline

The problem of Power Dissipation in testing

Introduction to illinois scan architecture

Low power illinois scan architecture-1( Chandra et al.)

Low power illinois scan architecture-2(Ling et al.)

Some proposals for further improvement

The problem of Power Dissipation in testing

Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss.

Power consumption during testing of scan circuit is an important issue to address for todays very complex circuits when chips are being designed with small feature size and higher frequency.

Excessive average power results into burn out of chip.

Excessive peak power results into power droop problem which can falsely classify a good chip as a faulty chip.

Introduction to illinois scan architecture

Ref-Prof.J.Patel's slides,illinois Scan slides 6 per page.

Illinois Scan with multiple pins

The scan chains which are compatible are grouped together in one group.

Two Test Modes of Illinois Scan

Beyond Illinois Scan

Illinois Scan has achieved phenomenal success in reducing Test data volume,Pin overhead & Test application time.It does not cater to the need of low power because because like basic scan, all the scan flops and the CUT are subjected to continuous switching activity during shift and capture cycles.Some architectures have been presented for achieving low power along with reduced test data volume,pin overhead & test application time.

Low power illinois scan architecture-1

Ref--Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction Anshuman Chandra, Felix Ng, Rohit Kapur, In Pro. DATE, IEEE, 2008. 462-467

Procedure for one scan-in & scan-out cycle

Set LPWR sel = 1

Scan-in data into the Reference chain and the shared chains for (n-1)b shifts while scanning out values from all the chains.

Set LPWR sel = 0

Scan-in data in the scan blocks of the shared chains from the previous scan block in the Reference chain for the last b shifts. For the first scan block, scan in data into Reference chain and shared chains from the SI.

Set the primary input values and the scan enable

Apply the capture clock to capture the response of the CUT

Response Captured in scan flops

In this scheme,scan block is of size 'b' and number of scan blocks per chain is 'n', thus the shift cycle length is equal to 'nb' .

State of scan chains after '(n-1)b' shifts

State of scan chains after scan in shift for 'nb' shifts

Discussion

While the reference chain is updated, in this configuration the shared chains receive constant data from the pseudo scan input that is connected to the ground and the first n-1 scan blocks in the shared chains are filled with value 0.

The additional multiplexers added to the design increase the load on the last flop of each scan block of shared chains.

Low power illinois scan architecture-2

It is an extension of the previous scheme with the added feature of scan cell reordering.

It divides scan chains into several scan chain segments first and then putting the similar scan cells in adjacent positions to reduce dynamic power dissipation during test data shift in operation.

Ref--A low power broadcast scan scheme,Zhang Ling, Yan Bowu and Li Tonghan,Journal of Chemical and Pharmaceutical Research, 2014, 6(7):2158-2162

Identifying which Scan cell columns to be grouped together?

COMPARATIVE STUDY OF 3 IMPLEMENTATIONS OF ILLINOIS SCAN

Original Implementation of Illinois scan

COMPARATIVE STUDY OF 3 IMPLEMENTATIONS OF ILLINOIS SCAN

Implementation using low power illinois scan architecture-1

COMPARATIVE STUDY OF 3 IMPLEMENTATIONS OF ILLINOIS SCAN

Implementation using scan cell reordering of low power illinois scan architecture-1

Discussion

Compared with conventional broadcast scan this scheme enormously reduces scan-in shift power.

The low power scan with scan cell reordering may result in a slight longer routing length. However, this technique only makes modification for the adjacent two segments, so the routing length would not be very long.

Some proposals for further improvement

In the first architecture,experiment can be carried out for a different value of number of scan blocks per chain(n) and scan block size(b).

Also in this architecture, instead of supplying all 0's as pseudo scan input,all 1's may be applied as pseudo scan input.

Some proposals for further improvement

In the second architecture instead of reordering over adjacent blocks, reordering can be done over the entire row (single scan chain).

There is no theoretical basis for this proposed reordering.A systematic formulation based on graph theory may help achieve higher efficiency.

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