pre silicon to post silicon overview - computer action...

Pre Silicon to Post Silicon Overview

Adam Norman

Intel Corp.

PCCG

What is Pre-Silicon?

It is the design Phase of a platform, which is done before silicon/packages/boards have been fabricated.

• It can take many years of pre-silicon work to create a CPU.

Typically, the design work is done with simulation.

• Optimization of design

• Tradeoffs ( power, area, cost, features, risk …)

• Robustness studies…

2

What is the relationship between Pre and Post ?? Questions to class before we learn more

about Pre-Silicon methods

• What can you simulate?

• How accurate is the simulations?

• How many simulations should I run?

• What do you trust more? Simulation or Measurement?

3

Simulation Domains

4

Pre Layout SimsSilicon and/or boards parameterized

Post Layout SimsSilicon and/or Boards Extracted

ActiveTransistors

Circuits/Devices

Feedback

PassivePower Deliver Network (PDN)

Transmission Lines

Physical (PCB, Sockets, Conn.)

Vias

Discrete components R,L,C

Active vs Passive Simulation

Active, generally has non-linear and/or time varying elements.

• Transient simulation is usually performed

– SPICE is most common simulator

Passive is generally Linear Time-invariant (LTI)

• 3D structures usually simulated with Full-wave solvers : Can you name some 3D solvers?

– Output is Frequency Domain (S-parameters)

• 2D structures, can use simpler/faster solvers

– Many output formats, RLGC, tabular W-element, S-param….

• Combining the Active + Passive elements

– Transient simulation is needed

– Commonly used tool is HSPICE5

Pre Silicon Disciplines

Circuit (I/O) Design

• Focus on Active portion (circuits)

– Transmitter and Receivers

– Understanding PVT impact on Jitter

Signal Integrity

• Focus on Board + Circuit

Power Integrity

• Focus on PDN + Circuit6

Signal Integrity Terminology

7

MB_L1

Ron

DIMM

Conn.

PKG_L1

DIMM_L1 DIMM_L2

DRAM1 DRAM2

.

DRAM1 DRAM2

Victim

Aggressor

Topology

Deck

3D structures (or Vertical Structures)

Transmission Lines

Transmitter Circuit (Tx)

Drive Strength (Ron)

Receiver Circuit (Rx)

IBIS Model

Termination/ODT

Loads

Victim

Aggressors

Coupling

Reference Plane

Silicon Package Motherboard

Post Layout Extraction

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How do you use the Simulations?

Class Exercise

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Goal specific methodologies

PathFinding

• Comparative analysis

HVM …. Class Exercise [ List Variables]

• Heart of Signal Integrity at Intel

Validation

• Post Layout?

• Transistor Models10

Variation Sources Manufacturing variation (HVM)

• Tolerances

• Design Variable

• CLASS EXERCISE : LIST 20 parameters

Time Varying (temporal)

• Temperature

• Voltage

• Noise11

What do you measure in Simulations?

Simulation has the luxury of “infinite” observability.

• How does this compare to Post-Silicon Measurements?

King of metrics is the eye-diagram.

• Time Domain metric

Many other waveform and Frequency Domain based metrics• Setup/Hold timing

• Ringback Level

• Non-monotonicities

• Slewrate

12

How do you get an eye diagram?

2 Typical approaches

• Pattern simulation (aka empirical)

• Peak Distortion Analysis (aka analytic)

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Eye Diagram

CLASS DEMO

14

Setup

Hold

Voltage Margin

Strobe/CLK

Peak DistortionFinding Worst Case Eye

15

16

cursorprecursor postcursors

Sample Pulse Response

EACH DOT SEPERATED EXACTLY BY 1 UI

UI = BIT WIDTH

17

cursorprecursor postcursors

ISI+ ISI-

Sample Pulse Response

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LTI property: Superposition

Tx symbol

…000010000000…

In Out

Pulse response

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LTI property: Superposition of symbols

Tx symbol

…000010011100…

In Out

Response to pattern 100111

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LTI property: Superposition of coupled symbols

Tx symbol

…000010000000…

In

Out

FEXT Pulse response

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LTI property: Superposition of coupled symbols

Tx symbol

…000011111100…

In

Out

FEXT response

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LTI property: Superposition of coupled symbols

Out

Tx symbol

…000011111100…

FEXT response

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LTI property: Superposition of coupled symbols

Out

Tx symbol

…000010011100…

Insertion loss response

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LTI property: Superposition of coupled symbols

Out

Tx symbol

…000010011100…

Tx symbol

…000011111100…

FEXT response

Insertion loss response

Composite response

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Peak Distortion Analysis

Must apply to Linear time-invariant system

• Superposition applies

– Interference of symbols on same wire

– Interference of symbols on different coupled channels

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Worst-case 0

-5 -4 -3 -2 -1 0 1 2

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1 1 0 1 0 0 1

Worst-case 0

+= ISIVWC0

-5 -4 -3 -2 -1 0 1 2

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Worst-case 1

-5 -4 -3 -2 -1 0 1 2

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Worst-case 1

0 0 1 0 1 1 0

-+= ISIcursorVWC1

-5 -4 -3 -2 -1 0 1 2

Is peak distortion realistic?

CLASS Exercise:

• 10 Aggressors

– 10 bit deep of channel memory

BER Analysis is Statistical Eye

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Driver/Receiver (Silicon)

Topology and Signaling

Definition

IBIS/Linear

Deck Creation

Transistor

HVM Variable Definition

Sampling Plan

(DOE, MC, FOCUS, GA)

SPECS

Run Simulations

Stackup/RLC

Connectors/Vias

Package/SktTool: Text Editor

Tool: Spreadsheet

Tools: JMP, Excel, .JSL

Tools: Hspice,Lynx

S-Param Syn.

Waveform Analysis

PDA, BER

Tools: SigSim, Simba

Data AnalysisDOE/RSM

Error Analysis

Tools: JMP

Matlab

Very Frequent Loop

Less Frequent Loop

DOE has reduced need

~3x to 4x Repeat

Tied to Silicon Revs

~3x to 4x Repeat

Only for “new” busses

Itera

tion P

ath

s

Tool: IBIS Center

PRE-Silicon

Flow

Analysis Techniques Time Domain Analysis and Frequency

Domain Analysis

Design of Experiments (DOE)/Neural Net Modeling

• Build a model of the metric

Worst Case analysis

Monte Carlo

Sweeps

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DOE/NN Flow

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This is what we want to predict !1,000,000 Units

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This is the goal for Pre-Silicon and Post-Silicon predictions.

Intel has been evolving tools/methods towards this predictive goal.

Such that, we can optimize cost and performance while still meeting

Reliability (“DPM” or customer Fails) and Yield ( Factory Rejects) targets.

Notes:

1. Customer determines

the fail. Not the spec.

2. With perfect prediction

we would have 0 Factory

Rejects and XX Customer

Fails.

- How do get there?

How do we get there?

Starting from a perfect prediction.

35

Custo

mer

Fa

ils

Notes:

1. Infinite number of

assumptions are completely

known, including customer

fail definition. Nothing

uncontrolled

2. This could be pre-silicon or

Post-Silicon

- What happens in reality?

This is the goal for Pre-Silicon and Post-Silicon predictions.

If we could perfectly predict customer margin, then we could optimize

such that we meet reliability targets with no yield loss.

Build 1million systems

- predict all variation sources

Pre-Silicon Predictions

36C

usto

me

r F

ails

Perfect PredictionC

usto

me

r F

ails

?Predicting Heavy tails

Correlation?

Notes:

Numerous factors for deviation from perfect

1. Pre-Silicon assumptions

- Stimulus, # of aggressors

- Driver Models, Jitter

- Eye Mask

2. Missing variables and noise

3. Imperfect Simulator

Goal for the evolution of Pre-Silicon Tools and methods is to

Tractably close this gap

Post-Silicon Predictions

37C

usto

me

r F

ails

Perfect Prediction

Cu

sto

me

r F

ails

?

Predicting Light tails

Correlation?

Notes:

Numerous factors for deviation from perfect

1. Post-Silicon assumptions

- Stimulus

- Sampling Scheme

2. Missing variables and noise

3. Uncontrolled variables

4. Measurement error

Goal for the evolution of Post-Silicon Tools and methods is to

Tractably close this gap

Correlation Paths – What matters?

38

Cu

sto

me

r F

ails

Cu

sto

me

r F

ails

Cu

sto

me

r F

ails

Perfect Prediction ( reality)

PreSilicon Prediction

PostSilicon Prediction

Notes:

1. Good engineering is necessary to properly

Assess risk. By understanding limitations

And assumptions in both predictive domains

the best risk decision can be made

Although Pre to Post Silicon Correlation is most commonly targeted,

Don’t forget about the bigger goal. “Don’t confuse the map with the terrain”

Corr

ela

tion?

How did we evolve to this picture?

39

Cu

sto

me

r F

ails

Cu

sto

me

r F

ails

PreSilicon Prediction

PostSilicon Prediction

The evolution of both methods is valuable to study.

And, of course, new methods/techniques are always being added.

PreSilicon Evolution

Post Silicon Evolution

Physics:: Lossless … Lossy …Crosstalk …SIPI

Methods:: MC … DOE …PDA …BER … DPM

DFx:: Voltage Margin…Timing Margin…BER

Methods:: MC … DOE …GA …BER … DPM

PreSilicon Simulation Evolution

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Year 2000 2001 2002 2003 2006 2008 2009

Physics

[Modeling]

Physics_A Physics_A Physics_B Physics_B Physics_C Physics_D Physics_E

Stimulus Pattern

Suite

+WC

Pattern

(PDA)

+BER + (Tx/Rx

Jitter)

Sampling MC+Grid +DOE +NN

Guard

band

GB_A GB_B(statistical

eye mask)

GB_C GB_D GB_E GB_F GB_G

Risk/Goal Find WC Find WC Find WC Find WC Find WC “+DPM” “DPM”

Takeaways:

1. Guardband must always be consistent

with the assumptions.

- “KIT” of information.

2. All facets of PreSilicon method evolve

3. Simulator capability and need dictate

the “physics” modeling.

4, Note that methods/techniques are rarely

thrown away. Efficiency and

Summary

Pre-Silicon simulations are a valuable part of the design process.

Excellent means for understanding and optimizing under HVM variation

Are they perfect? No

Should you still do validation? Yes41