power integrity is more than decoupling capacitors… the ... · xilinx kcu105 –vcc1v2 pdn power...
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Power integrity is more than decoupling capacitors…The Power Integrity EcosystemKeysight HSD Seminar
Mastering SI & PI Design
Page
© Keysight
Technologies 2017 2
Signal
Integrity
Power
Integrity
SI and PI
Eco-System
Page
What Does the Power Distribution Network Look Like?
© Keysight
Technologies 2017 3
The “Real World” PDN Network
Device
Detail
Supply Noise Ground Noise
Package
Pkg
Device
Page
Is Target Impedance Really this Simple?
© Keysight
Technologies 2017 4
Current
RippleAllowedVoltageSupplyPowerZ
)_()__( Target
Example:
3.3 V
VRM
4 A 2 A
I
VZ
Target
mA
VZ 5.82
2
%)5()3.3(V)Target(3.3
“Target Impedance is the goal that designers should hit!!!”
3.3 V Power Plane
Target Impedance Calculation
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L-C Series Resonance Problem with Capacitors
© Keysight
Technologies 2017 5
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L/C Parallel Resonance Problem in the PDN Design
© Keysight
Technologies 2017 6
Page
Power Delivery Target Impedance
© Keysight
Technologies 2017 7
Flat Z at lower frequencies reduces
the package/ DUT anti-resonance
at higher frequencies!
VRM
Impedance
Decoupling
Sink
Interconnect
IMP
ED
AN
CE
(O
HM
S)
FREQUENCY (Hz)
Page
Forced and Natural Response – Time Domain
© Keysight
Technologies 2017 8
DroopKick
Current Load
Power Rail
Natural Forced
Page
Spectral Content of the Sink
© Keysight
Technologies 2017 9
Digital Switching Spectral Content
• Edge speeds determine the di/dt
maximum for Ldi/dt ripple voltage.
• I(t) waveform determines the
spectral content, digital patterns
have a wide bandwidth (peaks
are at odd harmonics of clock
rate)
PRBS
SINE
Page
Z is below target, but not flat….. Is this a problem?
© Keysight
Technologies 2017 10
Z Target
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How to Design for Power Integrity: Finding Power Delivery Noise Problems
© Keysight
Technologies 2017 11
Steve Sandler – Picotest
Author of Power Integrity
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Start at the Voltage Regulator Module to Design for Flat PDN
12
No DeCaps vs. With DeCaps
DeCap1 DeCap2 𝐶 =
𝐿𝑠𝑙𝑜𝑝𝑒𝑍𝑑𝑒𝑠𝑖𝑟𝑒𝑑2
𝐿𝑠𝑙𝑜𝑝𝑒
𝑍𝑑𝑒𝑠𝑖𝑟𝑒𝑑2
Minimizes the quantity of capacitors to reach target Z
Page
How to get a flat VRM Impedance
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1-Port Reflect vs 2-Port Shunt Through
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Separating PCB Mounting L from CESL
20
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Manufacturer’s Demo PCB – Not Flat, Hard to Measure
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Page
VRM Characterization Board for Flat Z Design
22
Page
Measured Models
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How to Videohttp://tinyurl.com/vrm-video
https://www.picotest.com/DesignCon-2017.html
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State Space Hybrid Model – LM20143Switching Transients & Small Signal Impedance
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www.keysight.com/find/eesof-sipi-resources
Page
Modern Day PCB’s Have Increasing Data Speed and Complexity
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– Xilinx KCU105 FPGA Kit
FMC : 2Gbps ~ 10 Gbps
SFP: 8Gbps 16Gbps w 64b/66n
encoding, QSFP 25 Gbps+
HDMI : 2.0 = 6Gbps 3.1 =10Gbps
USB3.0: 5Gbps 3.1 =10 Gbps
PCI-E : 3.0 = 8 Gbps 4.0 = 16Gbps
DDR4: 3.2Gbps
9.27 x 5 inch, 16 layers PCB
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Modern Applications with Multiple PDNs
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Xilinx Kintex VCU105 Board: Power Planes
15 Major Power Distribution
Networks (PDN)
16 Layer PCB
Page
VRM: U4
1.2 V
Sink : U63
1.1479 V
Vdrop= 53 mV
Sink : U62
1.14745 V
Vdrop= 52 mV
Sink : U61
1.14747 V
Vdrop= 52 mV
Sink : U60
1.14755 V
Vdrop= 52 mV
PIPro – DC IR Drop
27
Xilinx KCU105 – VCC1V2 PDN
Power Dissipation
and Current Density
visualization
Voltage and current reported per Via, Sink, VRM
and more!
Page 28
EM Simulations for Multi-Port PDN PCB Models
No Capacitors
With Capacitors
ADS PIPro and SIPro
Z
Z
frequency
frequency
64 Port PDN PCB EM Circuit
Model
(S-parameter Behavioral
Model)
Page
PIPro – AC PDN Impedance Analysis
30
Voltage, current and Power Loss Density Plots
+ Full scripting support for setup, simulation and post-processing
Easy setup:Filter, drag and Drop
Components
Component Model assignment:
• Lumped
• SnP
• Murata
• Samsung
• TDK
• Create custom parts from
Schematic models
Page
PIPro – AC PDN Impedance Analysis
31
– Decoupling Capacitor Selection in PIPro
Voltage, current and Power Loss Density PlotsAnalyze effect of decap
model changes without any
need to re-simulate
Original PDN
Impedance
New Model
Selected
Page
PIPro – AC PDN Impedance Analysis
32
– Decoupling capacitor tuning from schematic
Values Tuning
De
ca
ps
On
e G
rou
p o
f D
eca
ps
PCB Model
VRM Choke
VRM
Memory-1
Controller
Memory-2
Memory-3
Memory-4
Completely
flexible PDN
optimization
strategy
Top-level Model
From PIPro
Page
SI and PI Co-EM Simulation
33
Power and Signal Nets
in the same EM
simulation
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Vendor Specific IBIS Models to Improve Accuracy
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– Xilinx Kintex FPGA and Micron DDR4 IBIS models
Kintex IBIS Micron IBIS
Page
Simultaneous Switching Noise (SSN)
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– Shows SSN noise voltage at VCCO pin, which
is similar to the measured data
• Both eye width and height are reduced by
SSO noise, as expected.
• 387.5p 375p, 510mV 474mV respectively
VCCO Pin Noise Voltage By SSON
No PDN – Ideal VCCO With SSON
Page
SSO Noise Measured Example
36
– Simultaneous Switching Output Noise (SSON)
CLK
SSO Noise
DQ
DQs
VCCO
Page
SI with PI, PI with SI, and SI PI Co-Simulation
37
SI PISI and PI
EEsof ADS SIPro and PIPro Integrated EM Simulation
IR Drop , AC Impedance
Loss, Delay, Crosstalk
S-Parameters
EM Behavioral Model
S-Parameters
Page
Want More Resources?
www.keysight.com/find/eesof-tutorials-signal-integrity
www.keysight.com/find/eesof-ads-sipi-resources
Signal Integrity & Power Integrity Resources
Try it for free for 30 days with absolutely no
obligation.www.keysight.com/find/hsdswtrials
ADS Bundle Used for Power Integrity Analysis:
• W2222BP Power Integrity Bundle: ADS Core, TransConv, Harmonic Balance,
Layout, PIPro
Page
Thank You!
39
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