november, 2005 iecon 2005 1 optimized design of a back-to-back npc converter to be used as interface...
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1November, 2005 IECON 2005
Optimized design of a back-to-back NPC
converter to be used as interface of
renewable energies
Emilio J. Bueno1), Santiago Cobreces2), Francisco J. Rodríguez3), Álvaro Hernández4), Felipe Espinosa5), Raúl Mateos6),
Juan C. García7), Félix López8)
1,2,3,4,5,6,7) Department of Electronics, Alcalá University 8) SEDECAL CONTROL
28871 Alcalá de Henares (Madrid) SPAIN 28110 Algete (Madrid) SPAIN
emilio@depeca.uah.es FLopez@sedecal.com
2November, 2005 IECON 2005
Contents Contents
1. Introduction.
2. Power Electronics System.
3. Control Electronics System.
4. Practical results.
5. Summary.
3November, 2005 IECON 2005
Disturbances …
Problems to solve in the connection of VSCs to the Problems to solve in the connection of VSCs to the grid (1/2)grid (1/2)
Distribution line
Motor VSC1 VSC23*L13*L2
3*Co
CDC
P
N
Line impedance
ge
from the converter towards the grid:PWM commutations. Can be reduced using a LCL-filter and a mutilevel converter.Temporal drifts of the filter components. Inductances saturation.
from the grid towards the converter:Unknown line impedance (weak grid).Line voltage harmonics.Permanent unbalanced line voltages. Temporal unbalanced line voltages (dips).
5November, 2005 IECON 2005
““CONDOR” project (1/2) CONDOR” project (1/2)
CONDOR: “Double converter based on multilevel inverters designed for recovering energy and minimizing electromagnetic emissions”.
Financed by the Spanish Science and Technology Ministry (DPI2002-04555-C04).Duration: December, 2002 – December, 2005.Researching groups: University of Alcalá (Coordinator), University of Carlos III, University
of Valencia and Institute for Electrical Technology of Valencia.Collaborating companies: SEDECAL CONTROL.
N
nAC
Motor
VSC1 VSC2
Sa2
Sa1
Sa2
Sa1
Sb2
Sb1
Sb2
Sb1
Sc2
Sc1
Sc2
Sa2
Sa1
Sa2
Sa1
Sb2
Sb1
Sb2
Sb1
Sc2
Sc1
Sc2
Sc1
3*L13*L2
3*Co
CDC2
NP
P
CDC1
Da2
Da1
Db2
Db1
Dc2
Dc1
Da2
Da1
Db2
Db1
Dc2
Dc1
ea
eb
ec
PCC
Sc1
6November, 2005 IECON 2005
““CONDOR” project (2/2)CONDOR” project (2/2)
AC motor
VSC1 VSC23*L13*L2
3*Co
CDC2NP
P
N
CDC1
ea
eb
ec
PCC
n
Auxiliar breaker
Mainbreaker
Auxiliar rectifier
Power Electronics System
ADCsMeasurements of
grid filter variables
ADCsMeasurements of DC-bus
variables
ADCsMeasurements of motor
variables
PWM VSC 1 PWM VSC 2FPGA SPARTAN 2E
DSP TMS6713VSC 1 Control VSC 2 Control
Communication cardInterface card between the Coprocessor Module – Power Electronics System
Coprocessor Module
References
Control Electronics System
References
7November, 2005 IECON 2005
ObjectivesObjectives
This work presents the construction of the Power Electronics System, the converter
limitations to compensate unbalanced dips, and the designs of grid filter components and
DC-bus capacitors.
In this work the grid filter is the LCL and the analytical equations for the components are
obtained to verify the ICE 61000-3-4 standard.
As for the DC-bus capacitors, the analytical equations for the ripples in uDC due to iDC and
iNP are obtained. From these equations, the DC-bus capacitors are calculated.
With respect to the Control Electronics System, the chosen structure and the task
distribution between the system processors are presented.
8November, 2005 IECON 2005
Contents Contents
1. Introduction.
2. Power Electronics System.
3. Control Electronics System.
4. Practical results.
5. Summary.
9November, 2005 IECON 2005
Power electronics specifications and assemblyPower electronics specifications and assembly
Specifications of the utility grid and the converter
10November, 2005 IECON 2005
Converter limitations to compensate unbalanced dipsConverter limitations to compensate unbalanced dips
The maximum peak phase current to compensate the unbalanced voltage dips and with zero phase jump can be calculated approximately as:
dqndqp
g
ee
Si
0
max 3
2ˆ
The system must be oversized to compensate voltage dips to nominal power. The elements that limit this current are mainly the grid filter inductances and the IGBT’s.
i (A)
NBA (Weber·turn)
0.124891
249.6382
-0.124891
-249.6382
L1
0.053172
212.688
-0.053172
-212.688
L2
II
I
II
II
I
II
NBA (Weber·turn)
i (A)
If the excess energy is not stored or dissipated the DC-bus voltage increases. The elements that determine the DC-bus voltage limitations are the IGBTs (maximum direct collector emitter voltage) and the DC-bus capacitors (nominal voltage).
11November, 2005 IECON 2005
Grid filter designGrid filter design
Filter limitations Resonance frequency. 210 0
SWbase
Inductance. The total value of the inductances should not be bigger than 10% of Lbase.
Capacitor. i1 in function of Co is: 22
2
2
1
2
21 gobase eCiiii
0 20 40 60 80 100140
150
160
170
180
190
200
210
% de Cbase
Current (
A)
0 2 4 6 8 10144.2
144.4
144.6
144.8
145
145.2
% de Cbase
Current (
A) I
1nI2n
I1nI2n
The design expressions are
Co is the 5% of Cbase.
21 2LL
nbaseo
base
baseobaseo IC
U
CCL
34
2
222223332006.0334
3
334
3
Chosen values are
L1=0.5mH/175Arms.
L2=0.25mH/150Arms.
Co=100μF/400Vrms.
12November, 2005 IECON 2005
Calculation of the DC-bus capacitorsCalculation of the DC-bus capacitors
uDC
vN = uDC/2 + vN
vP = uDC/2 + vP
iNPR
CP= 2CDC
iP
iN
CN= 2CDC
iNPI NP
Simplified diagram of a back-to-back converter based on two NPC’s
Ripple due to iDC
DCDC
SWSW
DC
DCiDC
iNiP Cu
STT
C
iuvv DC
DCDC 422
1
2
0 10 20 30 40 50 60 70 80 90 1000
100
200
300
400
500
600
700
800
900
1000
uD
C (
V)
mf
Main ripple due to iNP
Main ripple due to iDC DC
baseNP
P
baseNP
i
NPiNiP C
Ti
C
Tivvv
NPNPNP
ˆ
12
1ˆ
6
1
2
Ripple due to iNP
13November, 2005 IECON 2005
Contents Contents
1. Introduction.
2. Power Electronics System.
3. Control Electronics System.
4. Practical results.
5. Summary.
14November, 2005 IECON 2005
Control electronics system (1/3)Control electronics system (1/3)
AC motor
VSC1
3*L1 3*L2
3*Co
CDC2 NP
P
N
PCC
CDC1
uDC meas.
NP Voltage Balancing Controller
uDC
controller
)(kuDC
)(kuDC
Current controller
)(kid
)(kiq
)(* ku
Grid current meas.
Grid voltages meas. SPLL
tititi cgbgag ,, tetete cPCCbPCCaPCC ,,
)(kig
kek g
),(1
Control of VSC connected to the grid Control of VSC connected to the AC machine
iDC1 iDC2 Distribution line
High level controller
References from the grid managing
PWM generator
)(* ku
12 pulses
Machine measurements
tr
Current controller
Machine controller
)(ki
)(kr)(kd
kki r),( kr
tititi cba ,,
Turbine controller
kPw
PWM generator
12 pulses
15November, 2005 IECON 2005
Control electronics system (2/3)Control electronics system (2/3)
Control Electronics System
ADCsMeasurements of grid filter variables
ADCsMeasurements of DC-
bus variables
ADCsMeasurements of motor variables
PWM VSC 1 PWM VSC 2FPGA SPARTAN 2E
DSP TMS6713VSC 1 Control VSC 2 Control
Communication cardInterface card between the Coprocessor Module – Power
Electronics System Coprocessor Module
References References
16November, 2005 IECON 2005
Control electronics system (2/2)Control electronics system (2/2)
17November, 2005 IECON 2005
Contents Contents
1. Introduction.
2. Power Electronics System.
3. Control Electronics System.
4. Practical results.
5. Summary.
18November, 2005 IECON 2005
““CONDOR” project (2/2) CONDOR” project (2/2)
19November, 2005 IECON 2005
Some converter waveformsSome converter waveforms
VSC1 working as non controlled rectifier and VCS2 driving to induction machine
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05-10
-5
0
5
10
i A(A
)
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
-500
0
500
time(s)
v AB(V
)
0 0.01 0.02 0.03 0.04 0.05-1
-0.5
0
0.5
1
time(s)
uDCp
(V)
uDCn
(V)
0 0.0050.010.0150.020.0250.030.0350.040.0450.05-4
-2
0
2Time trace of udcp
time in sec
udcp
0 100 200 300 400 500 600 700
0.050.1
0.150.2
0.25
frequency in Hz
Harm
onic
Am
plit
ude
Discrete transform of udcp
Ripple due to iNPRipple due to iDC
20November, 2005 IECON 2005
Controller programmingController programming
Areas Code Size
Count Incl. Total
Incl. Max.
Incl. Min.
Inc. Aver.
main() 184 1 441572 0 0 441572
init_system() 328 1 413848 0 0 413848
c_int(5) 472 55 397135 7310 7112 7220
acquisition_data() 1324 55 121487 2230 2196 2208
reference_PWM() 780 55 40578 754 607 737
spll_pi() 720 55 42517 778 772 773
dsc() 1440 55 50961 983 924 926
currentcontroller() 3648 55 107030 2005 1845 1946
dcbuscontroller() 548 55 13864 256 252 252
c_int(4) 220 1 13937 0 0 13937
system_protection() 144 1 7005 7005 7005 7005
Data acquisition
Startmain() and init_system()
t(k)=k·TS=k·200μsNo
Output controllerreference_PWM()
PI SPLLspll_pi()
DSCdsc()
Current controllercurrentcontroller()
DC_bus controllerdcbuscontroller()
Any fault?
System protectionsystem_protection()
Stop
Any hardware fault?
Yes → c_int(4)
Yes
Yes → c_int(5)
No
+
+
acquisition_data()
c_int(5) Control algorithm
TMS320C6713 DSP is operating at 225MHz.Cycle clock is 4.44ns.Sampling time is 200μsThe execution average time of the Control
algorithm is 32μs.
22November, 2005 IECON 2005
Contents Contents
1. Introduction.
2. Power Electronics System.
3. Control Electronics System.
4. Practical results.
5. Summary.
23November, 2005 IECON 2005
SummarySummary
A back-to-back NPC three-level converter of 100KVA has been designed, validated by
simulation and tested in a real converter.
In the “Power Electronics System”:
(1) the converter limitations to compensate voltage dips have been analysed;
(2) a method for designing the grid filter components has been proposed; and
(3) the factors that determine the DC-bus capacitor values have been analysed.
With respect to the “Control Electronics System”, the chosen structure and the task
distribution between the two processors have been presented.
24November, 2005 IECON 2005
Thank you for your attention!!!
Emilio J. Bueno1), Santiago Cobreces2), Francisco J. Rodríguez3), Álvaro Hernández4), Felipe Espinosa5), Raúl Mateos6),
Juan C. García7), Félix López8)
1,2,3,4,5,6,7) Department of Electronics, Alcalá University 8) SEDECAL CONTROL
28871 Alcalá de Henares (Madrid) SPAIN 28110 Algete (Madrid) SPAIN
emilio@depeca.uah.es FLopez@sedecal.com
Acknowledgment:
This work has been financed by the Spanish administration (CICYT: DPI2002-04555-C04-04).
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