nov. 10, 2005ucsc us atlas upgrade meeting -- ely, garcia-sciveres1 dc to dc power converion r. ely...
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Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 1
DC to DC Power ConverionR. Ely and M. Garcia-Sciveres
Atlas Upgrade WorkshopSanta Cruz, November 2005
• Series Scheme• Charge Pumps• Plans
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 2
Higher voltage power distribution is a MUST
Efficiency ratio: serial over parallel powering
01234567
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
13.5
14.5
15.5
x = IR/V
[1+
x]/[
1 +
x/n
]
n = 2
n = 5
n = 8
n= 10
SCT SLHC
(from Marc Weber’s Genova workshop talk)
Read: voltage delivery at n times operating voltage
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 3
Two Options
•Serial Power
•Work started with Pixels. Demonstrated with present modules by Bonn group
•Picked up for SCT modules by Marc Weber at RAL
•Will be incorporated into stave prototypes
•DC-DC converters
•Proposed by LBNL
•Initial simulations shown at Genova (details later)
•No prototype yet due to lack of IC designer availability
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 4
First of all:
Serial powering applies to modules, that is groups of chips on one hybrid connected to one sensor. Within hybrid, chips are
powered in parallel !
one current source for a chain of modules; voltage defined by set of regulators
“ground levels” of any pair of modules vary
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 5
RAL work (Mark Weber) 4 SCT modules, serial powering PCBs, DAQ support cards
SCT module 1
DAQ support card
Serial powering PCB
M4
M3
M2
DAQ support card
Serial powering PCB
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 6
Schematics of serial powering PCB
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 7
Photograph of serial powering PCB
Shunt regulator
AC LVDS data
Analog regulator
AC LVDS Clock and command
SC
T m
odul
e
DA
Q s
uppo
rt
card
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 8
Noise performance: indep. vs. serial poweringLet’s look at noise occupancy (NO) first
Module 662 powered independently
Noise performance remains excellent !
Module 662 powered in series with 3 others
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 9
trimDAC range 0PP PP PP SP4 SP4 SP4
2.04E-06 2.15E-06 2.23E-06 1.78E-06 1.86E-06 2.33E-064.18E-06 3.88E-06 3.86E-06 3.60E-06 3.45E-06 4.11E-061.85E-05 1.82E-05 1.74E-05 1.03E-05 8.94E-06 9.62E-063.90E-05 3.96E-05 3.73E-05 1.50E-05 1.32E-05 1.55E-051.91E-05 1.82E-05 1.77E-05 1.07E-05 9.19E-06 9.94E-065.00E-05 4.78E-05 4.58E-05 3.19E-05 2.74E-05 2.96E-052.99E-05 2.90E-05 2.83E-05 3.87E-05 3.23E-05 3.42E-052.33E-05 2.25E-05 2.23E-05 3.27E-05 2.82E-05 2.94E-05
628
662
681
755
Noise performance: independent powering vs. serial powering
Noise performance remains excellent
Independently powered Powered in series
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 10
Noise performance: independent powering vs. serial powering
Noise performance remains excellent
Independently powered | Powered in series
Noise for IP (1-3) and SP (4-6)
1.00E-006
1.00E-005
1.00E-004
1 2 3 4 5 6
run nr.
no
ise
occ
up
ancy
662 top 662 btm 681 top 681 btm 755 top 755 btm 628 top 628 btm
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 11
Serial SCT plans from Genova
More studies on SCT module set-up (1-3 months)
o more noise tests e.g. introducing noise sources/ oscillationso closer look into AC-LVDS coupling
Built and study a more realistic system(½ -2 years)
o Dense packaging; o Grounding and shielding issueso Miniaturized regulator circuitry;o Modified readout chipo Redundancy features
If promising, develop SLHC prototype (> 2 years)
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 12
DC-DC Converter options
• Switched Capacitor array– not common in industry except for divide by 2– Seems natural choice for us- fewer worries (see below).
• Inductor Buck converter – typical in industry– We would have to worry about magnetic field, EMI from
fringe fields, and would have to make our own air-core toroidal inductors.
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 13
Divide by 4 Stack
• Phase 1
1
+-
1
2
2
+-
1
2
2
+-
1
2
2
+- Load
Vd
Vd
+ -+ - + -+-
Load
+-
+-
+-
+-
Load
• Phase 2
4 capacitors – 13 switches
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 14
DC Converter - DC4x5
C2
1
C1
2
VS C0
C3
2
1
11
1
2
2
2
Z
DC converter with 4 caps and an ideal conversion ratio of 5
10 switches
Phase 1 Phase 2
VS
C3 C1
C2 C0C1C3
C2
V
V
2V
3V
5V
C0
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 15
DC Converter – Div by 4 Ladder
C4
Z
C2
C1
2
2
1
1
2
1
1
2
C0
C3
C5
VS
C5
C3
C1
C4
C2
C0
VS
C5
C3
C1
C4
C2
C0
Phase 1
Phase 2
6 Capacitors
8 Switches
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 16
Comparison of CircuitsNormalize to Divide by 5
• Stack5 caps 16 switches– Uniform charge on caps– Large voltage swings on switches
• DC4x5 4 caps 10 switches– 2 caps have potential of 3Vo– Lower voltage swings on switches
• Ladder 10 caps 12 switches– Larger potential differences on caps– Voltage swings on switches ~ Vo
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 17
CMOS Transistor Switches
• Austria Microsystems H35 Process– Feature size 0.35μ– 3 gate oxides– Vds up to 50 vts– Bulk isolation – Gate oxide breakdown vt > 8vts
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 18
AMS H35 Transistors
Device Name
Min. L
(μ)
Max.
Vgs(vt)
Max
Vds(vt)
On Res.
L = min
W= 50m
Cg (pf)
NMOSI 0.5 3.6 3.6 0.06 125
NMOS50T
0.5 3.6 50 0.54 364
PMOS50T
1.0 3.6 50 0.73 369
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 19
Figures of Merit(for divide by n)
• Voltage efficiency - εv = n*Vout / Vin
– Vout is a function of the load = Vin / n for no load
• Current efficiency - εI = Iout / n*Iin
– Charge is lost charging the gate capacitance of the switches
• Power efficiency - εp = εv * εI
• Ripple - less than Iout*period/C
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 20
Figures of Merit for Divide by n Stack Supplying Io
(all switches have ‘on’ resistance R, all switched capacitors have value C and Co >>C)
• Low frequency limit – RC << 1/f
• Hi frequency limit - RC >> 1/f
- clearly we want IoR << Vs/4 (for Vs = 10v, R < 2.5Ώ
nfCoI
nsVV
0
nelfornRoI
nsV
n
nnnRoI
nsVV
arg4
)2
)12)(1(1(2
0
nfConI
nsVV
0(For ladder)
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 21
Divide by 5 Stack
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 22
Drain-Gate-Source Waveforms of Switches
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 23
V eff and I eff vs period
0
0.2
0.4
0.6
0.8
1
1.2
0 0.2 0.4 0.6 0.8 1
period (us)
effi
cien
cy
V effI eff
Efficiency versus Frequency
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 24
Efficiency vs Transistor WidthEfficiency vs transistor width
0
0.2
0.4
0.6
0.8
1
1.2
0 10 20 30 40
width (mm)
eff
icie
ncy V eff 8mhz
V eff 5mhz
Veff 2.5mhz
Ieff 8mhz
Ieff 5mhz
Ieff 2.5mhz
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 25
Power Efficiency
Power Efficiency vs transistor width
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0 5 10 15 20 25 30 35
width (mm)
eff
icie
ncy
Peff 8mz
Peff 5mhz
Peff 2.5 mhz
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 26
Buck Converter
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 27
DC Conversion Conclusions
• At an operating freqency of 5mhz(Co = 4.7uf, C1 = 0.2uf– Voltage efficiency ~.84– Current efficiency ~.92– Ripple = 1.2%– Output impedance = 0.25 ohms (25mv / 100ma)
• Clock generator will reduce efficiency by 10%
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 28
Other topics not related to power
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 29
Test of Indium Bumped “2E” Assembly
Mask used for scans
2E = 2 columns per pixel. Only a small region of the sensor is properly bonded to the readout chip. The rest of the pixels are disconnected. The bonded region is shown here. X-axis is column number and Y-axis is row. Only the bonded channels were probed in what follows. Disconnected channels were masked off.
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 30
Noise vs. Voltage
This is the most probable single channel noise for select connected pixels. Determined from s-curve fits in charge injection scans after tuning thresholds to 4000e.
Looks like
Depletion voltage at ~23 V
Low voltage values not reliable due to bad S-curve
fits
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 31
Representive S-curves at varying voltages
Above depletioon voltage (~25 V)
12 V
3.5 V
0.5 V
6.5 V
2.0 V
Corrected bias voltage
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 32
Short strip module geometry
For a given hybrid technology, only way to reduce ratio (hybrid_mass)/(silicon mass) is to increase IC input density
hybrid
sensor
IC
Sensor is twice the strip length,
With bond pads in the middle.
stave
Hybrid can neck down here to save mass
Nov. 10, 2005 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres 33
Nanowire carpet hybrid pixel proposal
• Submitted to LBNL molecular foundry
• Too recent to know where this will go
• Eliminates bump bonding AND sensor wafer patterning.
• Intent is to produce very cheap hybrid pixel modules.
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