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TECHNICAL DOCUMENT 3195 April 2005
Nanosecond Thermal Processing for Self-Aligned Silicon-on-Insulator
Technology
A. D. Ramirez B. W. Offord
J. D. Popp S. D. Russell
J. F. Rowland
Approved for public release; distribution is unlimited.
SSC San Diego
TECHNICAL DOCUMENT 3195 April 2005
Nanosecond Thermal Processing for Self-Aligned Silicon-on-Insulator
Technology
A. D. Ramirez B. W. Offord
J. D. Popp S. D. Russell
J. F. Rowland
Approved for public release; distribution is unlimited.
SSC San Diego
San Diego, CA 92152-5001
SSC SAN DIEGO San Diego, California 92152-5001
T. V. Flynn, CAPT, USN Commanding Officer
R. F. SmithExecutive Director
ADMINISTRATIVE INFORMATION The work described in this report was performed for the Office of Naval Research Internal Applied
Research (IAR) Program by the Electromagnetics & Advanced Technology Division (Code 285) of SPAWAR Systems Center San Diego (SSC San Diego).
Released under authority of S. D. Russell, Head Electromagnetics & Advanced Technology Division
This is a work of the United States Government and therefore is not copyrighted. This work may be copied and disseminated without restriction. Many SSC San Diego public release documents are available in electronic format at http://www.spawar.navy.mil/sti/publications/pubs/index.html
SB
1
Am
eric
an P
hysi
cal S
ocie
ty22
–26
Mar
ch 2
004,
Mon
trea
l, Q
uebe
c, C
anad
a
Aya
x D
. Ram
irez,
Bru
ce W
. Offo
rd, J
erem
y D
. Pop
p,
Step
hen
D. R
usse
ll, J
ason
F. R
owla
nd
Spac
e an
d N
aval
War
fare
Sys
tem
s C
ente
r Sa
n D
iego
, CA
Nan
osec
ond
Ther
mal
Pro
cess
ing
for S
elf-A
ligne
d Si
licon
-on-
Insu
lato
r Tec
hnol
ogy
2
Abs
trac
tFu
ture
rada
r and
com
mun
icat
ions
sys
tem
s w
ill h
ave
the
need
to u
se C
MO
S
inte
grat
ed c
ircui
ts to
pro
vide
incr
ease
d an
alog
and
dig
ital f
unct
ions
. C
onve
ntio
nal C
MO
S te
chno
logy
has
bee
n lo
cked
into
des
igni
ng p
roce
sses
ar
ound
pol
ysili
con
gate
mat
eria
l bec
ause
of t
he n
eed
for s
elf-a
lignm
ent.
Low
-res
ista
nce
met
al g
ates
are
sup
erio
r for
hig
h-sp
eed
devi
ces.
How
ever
, th
eir l
ow m
eltin
g po
int p
reve
nted
thei
r use
in a
sel
f-alig
ned
stru
ctur
e th
at
expe
rienc
es h
igh-
tem
pera
ture
pro
cess
ing
(>70
0 o C
). S
ilico
n-on
-Insu
lato
r (S
OI)
tech
nolo
gy, n
on-re
fract
ory
met
al g
ates
, and
nan
osec
ond
lase
r pr
oces
sing
wer
e us
ed to
fabr
icat
e a
self-
alig
ned
stru
ctur
e.
Thes
e te
chni
ques
will
allo
w fu
rther
sca
ling
of C
MO
S d
evic
es a
nd e
nabl
e m
ixed
-mod
e de
vice
s to
be
inte
grat
ed o
n th
e sa
me
subs
trate
. Th
e la
ser i
s us
ed to
rapi
dly,
on
the
orde
r of n
anos
econ
ds, m
elt a
nd re
dist
ribut
e th
e im
plan
ted
dopa
nts
for t
he s
ourc
e an
d dr
ain
with
min
imal
late
ral d
iffus
ion,
whi
ch lo
wer
s pa
rasi
tic g
ate
to d
rain
and
sou
rce
over
lap
capa
cita
nce.
Gat
e re
sist
ance
can
be
low
ered
by
at le
ast a
n or
der o
f mag
nitu
de a
nd o
ptim
al
thre
shol
d co
ntro
l of p
MO
S a
nd n
MO
S d
evic
es c
an b
e ac
hiev
ed b
y us
ing
an
alum
inum
met
al g
ate
inst
ead
of a
pol
ysilic
on g
ate.
Thi
s pr
oces
s al
low
s hi
gh-
perfo
rman
ce, l
ow-p
ower
dig
ital t
echn
olog
y to
be
inte
grat
ed w
ith h
igh
F max
, lo
w-n
oise
RF
devi
ces.
3
Bac
kgro
und
Ther
e is
a n
eed
for d
eepl
y sc
aled
CM
OS
inte
grat
ed c
ircui
ts (I
Cs)
to
prov
ide
mix
ed-m
ode
oper
atio
n (a
nalo
g an
d di
gita
l). A
s IC
dev
ice
dim
ensi
ons
decr
ease
into
the
deep
-sub
mic
ron
rang
e, ti
ghte
r con
trol o
n do
pant
redi
strib
utio
n du
ring
the
IC p
roce
ss h
as b
ecom
e m
ore
rele
vant
. M
inor
var
iatio
ns in
the
dopa
nt d
istri
butio
n co
uld
lead
to la
rge
diffe
renc
es
in th
e el
ectri
cal p
rope
rties
of j
unct
ion
devi
ces.
The
need
for s
elf-a
lignm
ent h
as d
icta
ted
the
use
of p
olys
ilico
n ga
tes
whe
n de
sign
ing
CM
OS
dev
ices
. B
ecau
se th
e C
MO
S p
roce
ss re
quire
s a
high
-tem
pera
ture
pro
cess
to a
nnea
l the
sou
rce
and
drai
n im
plan
ts a
fter
the
gate
def
initi
on (w
hich
lead
s to
sel
f-alig
nmen
t), m
etal
gat
es w
ere
disc
arde
d. I
n ge
nera
l, lo
w-r
esis
tivity
met
al g
ates
are
sup
erio
r for
hig
h-sp
eed
devi
ces
as w
ell a
s hi
ghFm
ax a
nd lo
w-n
oise
pro
perti
es; h
owev
er,
thei
r low
mel
ting
poin
t was
wha
t led
tech
nolo
gy to
use
poly
silic
on.
4
Lase
r Ann
ealin
g an
d D
opan
t Act
ivat
ion
Silic
on
Impl
ante
d
Dop
ants
λ=
308
nmXe
Cl E
xcim
er L
aser
Act
ivat
ion
of D
opan
ts
Dur
ing
Mel
t Reg
ime,
R
emov
al o
f Dam
age
Cau
sed
by Im
plan
tatio
n, a
nd
Form
atio
n of
Sha
llow
Ju
nctio
ns.
APP
RO
AC
H
•Sel
f-Alig
ned
Met
al G
ate
•Sili
con-
on-In
sula
tor (
SOI)
Tech
nolo
gy
•Nan
osec
ond
Ther
mal
Pro
cess
ing
with
Exc
imer
Las
er
5
Phys
ical
Str
uctu
re o
f a P
oly
Gat
e (S
OI)
MO
SFET
Si S
ubs
trat
e
Bu
ried
Oxi
de
(BO
X)
N+
Gat
e
N+
Sou
rce
P B
ody
N+
Dra
in
Met
al
Inte
rcon
nect
Poly
gat
eSi
licon
Bur
ied
Oxi
de
Con
vent
iona
l Pol
y G
ate
Tech
nolo
gy
6
BO
X
Usi
ng A
l as t
he m
ater
ial f
or th
e m
etal
gat
e cr
eate
s a d
evic
e th
at h
as a
t lea
st a
n or
der
of m
agni
tude
low
er g
ate
resi
stan
ce
than
a si
licid
e po
lyga
te.
Met
al G
ate
Tech
nolo
gy
Al
Silic
on
TiN
Gat
e O
xide
3800
Å
70 Å
0.25
-mic
ron
Gat
e Le
ngth
Phys
ical
Str
uctu
re o
f a M
etal
Gat
e (S
OI)
MO
SFET
7
Bur
ied
Oxi
deSi
licon
Gat
e O
xide
Met
al G
ate
0.05
µm
Impl
ant S
ito
set
volta
ge th
resh
old
of M
OSF
ET, g
row
ga
te o
xide
,de
posi
t, et
ch
alum
inum
gat
eMET
AL
GA
TE (S
OI)
MO
SFET
: TH
E PR
OC
ESS
Bur
ied
Oxi
deSi
licon
Gat
e O
xide
Met
al G
ate
Cha
nnel
0.05
µm
Impl
ant a
rsen
ic
ions
to c
reat
e so
urce
/dra
in o
f tr
ansi
stor
8
0.05
µm
Bur
ied
Oxi
deSilic
onG
ate
Oxi
de
Met
al G
ate
Expo
se w
afer
to L
aser
en
ergy
to a
ctiv
ate
impl
ante
d ar
seni
c
Lase
r Lig
ht R
efle
cted
by
Met
al G
ate
MET
AL
GA
TE (S
OI)
MO
SFET
: TH
E PR
OC
ESS
Bur
ied
Oxi
deN
+ So
urce
SOU
RC
Eco
ntac
t
P ty
pe S
ilico
n
DR
AIN
cont
act
Gat
e O
xide
Cha
nnel
0.05
µm
N+
Dra
in
Dep
osit
oxid
e, p
atte
rn,
etch
con
tact
s an
d m
etal
in
terc
onne
ct, e
nd
prod
uct
Met
al G
ate
9
Expe
rimen
tal R
esul
ts
Exci
mer
Las
erO
ptic
s &
Pro
cess
ing
Cha
mbe
r
FIG
. 1 P
rimar
y C
ompo
nent
s of
the
Exci
mer
Las
er P
roce
ssin
g Sy
stem
SOI W
afer
s C
hara
cter
istic
sM
ater
ial
Ion
Impl
ante
d w
ith A
s at
a d
ose
of
5 x
1015
/cm
2@
30 K
eVO
rient
atio
n<0
01>
SIM
S A
naly
sis
Per
form
ed to
det
erm
ine
carri
er c
once
ntra
tion
SiT
hick
ness
700
ÅS
RP
Ana
lysi
s pe
rform
ed to
det
erm
ine
perc
ent a
ctiv
atio
nS
iO2
Thic
knes
sO
n a
3800
Å-la
yer o
f SiO
2
Lase
rE
xcim
er, 3
08 n
mP
ulse
Ene
rgie
sU
p to
425
mJ
Flue
nce
Ran
ged
from
300
to 4
00 m
J/cm
2
Pul
se R
ep. R
ate
1 H
z
Pre
ssur
e30
0 m
torr
(pro
cess
ing
cham
ber)
6-in
SO
I Waf
er
10
Lase
r Ann
ealin
g an
d D
opan
t Act
ivat
ion:
SIM
S R
esul
ts
Red
istri
butio
n of
dop
ants
, 35
0 m
J/cm
2
Fig.
2 U
ntre
ated
and
Tre
ated
Sam
ples
(350
mJ/
cm2 )
11
shal
low
Junc
tions
60 n
m70
nm
350
mj/c
m2
300
mj/c
m2
Fig.
3 T
reat
ed S
ampl
es (3
00 a
nd 3
50 m
J/cm
2 )
Lase
r Ann
ealin
g an
d D
opan
t Act
ivat
ion:
SR
P R
esul
ts
12
Fig.
5 R
uthe
rfor
d B
acks
catte
ring
Spec
trom
etry
(RB
S)A
naly
sis
of L
aser
-Tre
ated
Sam
ple
RB
S A
naly
sis
13
EFFE
CTS
OF
LASE
R U
V LI
GH
T O
N
MET
AL
LIN
ES
Lase
r exp
erim
ents
wer
e co
nduc
ted
to d
eter
min
e th
e ef
fect
s of
ultr
avio
let
(UV
) lig
ht o
n th
e m
etal
line
s. F
igur
e 6
show
s tw
o Sc
anni
ng E
lect
ron
Mic
rosc
opy
(SE
M) p
ictu
res
of m
etal
sam
ples
afte
r exp
osur
e to
five
pul
ses
(at r
epet
ition
rate
of 1
Hz)
with
flue
nces
of u
p to
500
mJ/
cm2 .
No
dam
age
to m
etal
line
s w
as o
bser
ved.
Fig.
6 L
aser
-Tre
ated
Met
al L
ines
14
Uni
ty C
urre
nt G
ain
Freq
uenc
y
fg
t=
++
m
gdC2π
C gsC gb
()
Spee
dD
ecre
ase
C’ s
Incr
ease
f t
Uni
ty P
ower
Gai
n Fr
eque
ncy
[]
f
f
fm
ax=
++
t
tg
gdds
gs
RC
RR
22π
g
RF
Gai
nD
ecre
ase
Rg
Incr
ease
f max
Min
imum
Noi
seM
icro
wav
e N
oise
Dec
reas
e R
gD
ecre
ase
F min
[]
Fk
gR
Rm
sg
min
=+
+1
f f t
FIG
UR
ES O
F M
ERIT
TO
QU
AN
TIFY
TH
E R
F PE
RFO
RM
AN
CE
15
Mod
elin
g of
Gat
e R
esis
tanc
e an
d So
urce
Res
ista
nce
Effe
cts
on F
t /Fm
ax
()
()
() ()
()(
)(
) ()()
()
()
()(
)()
()(
)()
poly
met
al
poly
gdg
ts
gds
tm
etal
gdgs
eff
met
alpo
lyt
sqpo
lyga
tesq
met
alga
te
sqsq
sour
ce
sqsh
gate
sqd
unsi
licid
es
sqsi
licid
edpo
lysi
squm
cmsp
acer
ssp
acer
sour
ce
VA
oxn
umfF
oxov
ff
GH
zfF
GH
zS
GH
zf
GH
zfF
GH
zS
GH
zC
RfR
Rg
ff
GH
zfF
fFm
SC
Cgmf
mm
Rm
mR
mmmm
R
RR
Rmcm
R
RR
RS
gds
mS
gmv
VC
Cm
lm
ml
max
,m
ax,
max
,
max
,
/,
,,
,,
,/
4
d)un
silic
ide
or
si
licid
ed(,
5.4
8.83
5.11
2042
2)
1020(
100
23.
42
8.37
95.
1167.0
422
)10
67.0(10
02
3.42
2)
(2
3.42
)5.
1175.
28(2
7.10
2
200.
255
325
3 ,
67.0
0.25
53
251.0
0.25
um),
x
5um
x
finge
rs
(5 M
etal
Gat
e
toPo
lyG
ate
C
ompa
rison
81gm1
10251
200
250.25
200
ca
seW
orst
1.0,
200
,3
,20
010
05.0001
.0 s,
resi
stan
ceSh
eet
100
,12
,1
,12
0,
6.4,
1.0 ,
0.25
/25
w/
Ass
ume,
22
=
=Ω
+Ω
+Ω
=
=Ω
+Ω
+Ω
=+
+≈
=+
=+
≈
Ω=
=Ω
==
Ω=
≤Ω
=+
=
==
==
Ω=
+=
==
=∆
==
==
ΩΩ
ΩΩ
ΩΩ
ΩΩ
πµ
πµ
πππ
µµ
µµ
µµµµµ
µµ
µµ
µµ
25um
/0.2
5um
QU
AN
TIFI
CA
TIO
N O
F TH
E M
ETA
L G
ATE
PR
OC
ESS
16
nMO
S R
ESU
LTS:
IV-C
urve
s
Fig.
7 Id
vs.
Vd
for (
L =
0.25
, W =
70)
nM
OS
Dev
ice
0.00
E+0
0
5.00
E-0
3
1.00
E-0
2
1.50
E-0
2
2.00
E-0
2
2.50
E-0
2
3.00
E-0
2 0.00
0.50
1.00
1.50
2.00
Vd (V
olts
)
Id (Amps)
Id (V
g=0.
00)
(Vg=
0.50
)(V
g=1.
00)
(Vg=
1.50
)(V
g=2.
00)
17
nMO
S R
ESU
LTS:
Ftan
d F m
ax
Fig.
8 F
tan
d F m
axfo
r (L
= 0.
25, W
= 7
0) n
MO
S D
evic
e
-10.
00
0.00
10.0
0
20.0
0
30.0
0
40.0
0
50.0
0
60.0
0
1.00
E+07
1.00
E+08
1.00
E+09
1.00
E+10
1.00
E+11
h21
MA
G/M
SG
F t=
23.3
GH
zF m
ax=
50 G
Hz
18
nMO
S R
ESU
LTS
Fig.
9 Id
vs.
Vd
for n
MO
S D
evic
e
0.00
E+0
0
5.00
E-0
3
1.00
E-0
2
1.50
E-0
2
2.00
E-0
2
2.50
E-0
2
3.00
E-0
2 0.00
0.50
1.00
1.50
2.00
2.50
Vd
(Vol
ts)
Id (Amps)
Id (V
g=0.
00)
(Vg=
0.50
)(V
g=1.
00)
(Vg=
1.50
)(V
g=2.
00)
19
nMO
S R
ESU
LTS:
F tan
d F m
ax
Fig.
10
F tan
d F m
axfo
r (L
= 0.
25, W
= 5
6) n
MO
S D
evic
e
-10.
00
0.00
10.0
0
20.0
0
30.0
0
40.0
0
50.0
0
60.0
0
1.00
E+07
1.00
E+08
1.00
E+09
1.00
E+10
1.00
E+11
h21
MA
G/M
SG
F t=
17.5
GH
zF m
ax=
44.2
GH
z
20
1.D
esig
ned
nMO
S SO
I dev
ices
with
alu
min
um g
ate.
2.C
hara
cter
ized
dop
ant p
rofil
e an
d ac
tivat
ion
leve
ls
usin
g Se
cond
ary
Ion
Mas
s Sp
ectr
omet
ry (S
IMS)
and
sp
read
ing
Res
ista
nce
Prof
iling
(SR
P), r
espe
ctiv
ely,
w
hich
dem
onst
rate
d hi
gh le
vels
of d
opan
t act
ivat
ion
usin
g la
ser a
nnea
ling.
3.D
emon
stra
ted
the
crea
tion
of v
ery
shal
low
junc
tions
, in
the
orde
r of 6
0 nm
, usi
ng la
ser a
nnea
ling.
4.C
reat
ed n
MO
S de
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Standard Form 298 (Rev. 8/98)Prescribed by ANSI Std. Z39.18
04–2005 Final
NANOSECOND THERMAL PROCESSING FOR SELF-ALIGNED SILICON- ON-INSULATOR TECHNOLOGY
A. D. Ramirez B. W. Offord J. D. Popp S. D. Russell J. F. Rowland
SSC San Diego San Diego, CA 92152–5001 TD 3195
ONR
Office of Naval Research 800 North Quincy Street Arlington, VA 22217–5660
Approved for public release; distribution is unlimited.
This is a work of the United States Government and therefore is not copyrighted. This work may be copied and disseminated without restriction. Many SSC San Diego public release documents are available in electronic format at http://www.spawar.navy.mil/sti/publications/pubs/index.html
Future radar and communications systems will have the need to use CMOS integrated circuits to provide increased analog and digital functions. Conventional CMOS technology has been locked into designing processes around polysilicon gate material because of the need for self-alignment. Low-resistance metal gates are superior for high-speed devices; however, their low melting point prevented their use in a self-aligned structure that experiences high-temperature processing (>700 oC). Silicon-on-Insulator (SOI) technology, non-refractory metal gates, and nanosecond laser processing were used to fabricate a self-aligned structure. These techniques will allow further scaling of CMOS devices and enable mixed-mode devices to be integrated on the same substrate. The laser is used to rapidly, on the order of nanoseconds, melt and redistribute the implanted dopants for the source and drain with minimal lateral diffusion, which lowers parasitic gate to drain and source overlap capacitance. Gate resistance can be lowered by at least an order of magnitude and optimal threshold control of pMOS and nMOS devices can be achieved by using an aluminum metal gate instead of a polysilicon gate. This process allows high-performance, low-power digital technology to be integrated with high Fmax, low-noise RF devices.
Mission Area: Microelectronics thermal processing excimer laser dopant activation n-channel Metal Oxide Semiconductor silicon-on-insulator laser annealing field-effect transistor
A. D. Ramirez
U U U UU 30 (619) 553–7561
INITIAL DISTRIBUTION 20012 Patent Counsel (1) 21511 J. Andrews (1) 21512 Library (2) 21513 Archive/Stock (3) 285 S. D. Russell (5) 2853 A. D. Ramirez (5) 2876 B. W. Offord (5) 2876 J. D. Popp (5) 2876 J. F. Rowland (5)
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