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Chapter 2
Nanometer Transistors and Their Models
Jan M. Rabaey
Nanometer Transistors and Their Models
Slide 2.1
Chapter Outline
Nanometer transistor behavior and modelsSub-threshold currents and leakageVariabilityDevice and technology innovations
Slide 2.2
Nanometer Transistors and Their Models
Emerging devices in the sub-100 nm regime post challenges to low-power design– Leakage– Variability– Reliability
Yet also offer some opportunities– Increased mobility– Improved control (?)
State-of-the-art low-power design should build on and exploit these properties– Requires clear understanding and good models
Slide 2.3
The Sub-100 nm Transistor
Velocity-saturated– Linear dependence between ID and VGS
Threshold voltage VTH strongly impacted by channel length L and VDS– Reduced threshold control through body
biasing
Leaky– Sub-threshold leakage– Gate leakage
→ Decreasing I on over I off ratio
Slide 2.4
ID versus VDS for 65 nm bulk NMOS transistor
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1× 10
–4
VDS
(V)
I D (
A)
ID is a linearfunction ofVGS
VGS = 0.8
VGS = 0.6
VGS = 0.4
VGS = 1.0
Early saturationDecreased outputresistance
Slide 2.5
[Ref: Taur-Ning, ‘98]
Drain Current Under Velocity Saturation
VGS − VTH + ECLWCvI oxSatDSat = (VGS − VTH)2
Good model, could be used in hand or MATLAB analysis
DSat L
WI ( THGSDSat VVV − )=
2
( ) LEVV CTHGSVDSat LEVV CTHGS +−−=with
oxeffCμ
Slide 2.6
[Ref: Rabaey, DigIC’03]
Models for Sub-100 nm CMOS Transistors
Further simplification:The unified model – useful for hand analysisAssumes VDSat constant
Slide 2.7
Models for Sub-100 nm CMOS Transistors
0
100
200
300
400
500
600
700
0 0.2 0.4 0.6 0.8 1 1.2
VDS [V]
0.4V
0.6V
0.8V
1.0V
1.2V
simulationunified model
linear
saturation
vel. saturation
VDSat
I DS
[μA
]
Slide 2.8
[Ref: Sakurai, JSSC’90]
Alpha Power Law Model
Alternate approach, useful for hand analysis of propagation delay
THGSoxDS VVCμL
W αI −=
2
Parameter α is between 1 and 2.In 65–180 nm CMOS technology α ~ 1.2–1.3
This is not a physical modelSimply empirical:– Can fit (in minimum mean
squares sense) to a variety of α’s, VTH
– Need to find one with minimum square error – fitted VTH can be different from physical
Slide 2.9
Output Resistance
Drain current keeps increasing beyond the saturation pointSlope in I–V characteristics caused by:– Channel-length modulation (CLM)
– Drain-induced barrier lowering (DIBL).
The simulationsshow approximatelylinear dependenceof IDS on VDS insaturation (modeled by λ factor)
(kΩ)
[Ref: BSIM 3v3 Manual]
Slide 2.10
Drain current vs. gate–source voltage
Thresholds and Sub-Threshold Current
0.0E+00
2.0E–04
4.0E–04
6.0E–04
8.0E–04
0 0.2 0.4 0.6 0.8 1 1.2
VGS
[V]
I DS [
A]
VTHZ
VDS = 1.2 V
Slide 2.11
Forward and Reverse Body Bias
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.50.25
0.3
0.35
0.4
0.45
0.5
VBS (V)
VT
H (
V)
Threshold value can be adjusted through the fourth terminal,the transistor body.
Forward biasReverse bias
Forward bias restrictedby SB and DB junctions
Slide 2.12
Evolution of Threshold Control
–0.5 0 0.5–0.1
–0.05
0
0.05
0.1
0.15
VBB (V)
ΔVT
H(V
)
130 nm
90 nm
65 nm
Body-biasing effect diminishes with technology scaling below 100 nm.No designer control at all in FD−SOI technology
210 mV
95 mV
55 mV
Slide 2.13
Impact of Channel Length on Threshold Voltages
L
Long-channel threshold
Lmin
VT
H
With halo implants
(for small values of VDS)
Partial depletion of channel dueto source and drain junctionslarger in short-channel devices
Simulated VTH of 90 nm technology
Channel Length [m]
VT
H [V
]
Slide 2.14
decreases leakage current by almost a factor of 20 for 90 nm technology
Impact of Channel Length on Threshold Voltages
50% increase in channel length
50 100 150 200 250 300 350 4000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Length (nm)
No
rma
lize
d le
aka
ge
cur
ren
t
Slide 2.15
Drain-Induced Barrier Lowering (DIBL)
In a short-channel device, source−drain distance is comparable to the depletion region widths,and the drain voltage can modulate thethresholdVTH = VTH0 – λdVDS
Channel
L (D)0 (S)
Long channel
Short channel
VDS = 0.2V
VT
H
VDS = 1.2V
Slide 2.16
MOS Transistor Leakage Components
G
DS
B(W)
Gate leakage
D−S leakageJunction leakage
Slide 2.17
Sub-threshold Leakage
–9
–8
–7
–6
–5
–4
–3
0 0.2 0.4 0.6 0.8 1 1.2
VGS [V]
log
I DS
[lo
g A
]
Sub-threshold slope S = kT/q ln10 (1+Cd /Ci)
Drain leakage current varies exponentially with VGSSub-threshold swing S is ~ 70−100 mV/decade
VDS = 1.2V
G
S D
Sub
C i
Cd
The transistor in “weak inversion”
Slide 2.18
Impact of Reduced Threshold Voltages on Leakagefo
ur o
rder
s of
mag
nitu
de
300 mV
Leakage: sub-threshold current for VGS = 0
Slide 2.19
Sub-threshold Current
Sub-threshold behavior can be modeled physically
⎟⎟⎠
⎞⎜⎜⎝
⎛−=⎟
⎟⎠
⎞⎜⎜⎝
⎛−⎟⎟⎠
⎞⎜⎜⎝
⎛=
−−−−qkT
V
qkTn
VV
SqkT
V
qkTn
VV
oxDS
DSTHGSDSTHGS
eeIeeq
kT
L
WCnμI 112
2
where n is the slope factor (≥1, typically around 1.5) and
2
2 ⎟⎟⎠
⎞⎜⎜⎝
⎛=
q
kT
L
WCnμI oxS
Very often expressed in base 10
⎟⎟⎠
⎞⎜⎜⎝
⎛−
−−S
nV
S
VV DSTHGS
IDS = IS 10 101
ln(10), the sub-threshold swing, ranging between 60 mV and 100 mV)(q
kTwhere S = n
1 for≈VDS > 100 mV
Slide 2.20
Sub-threshold Current - Revisited
� Drain-Induced Barrier Lowering (DIBL)– Threshold reduces approximately linearly with VDS
� Body-Biasing Effect– Threshold reduces approximately linearly with VBS
DSdTH 0TH VVV λ
γ
−=
BSdTH 0TH VVV −=
⎟⎟⎠
⎞⎜⎜⎝
⎛−=
−++−S
nV
S
VVVV
SDS
DSBSdDSdTHGS
II 101100
γλLeading to:
Leakage is an exponential function of drain and bulk voltages
Slide 2.21
Sub-threshold Current as a Function of VDS
ID versus VDS for minimum size 65 nm NMOS transistor(VGS = 0)
λd = 0.18S = 100 mV/dec
DIBL
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.5
1
1.5
2
2.5
3
3.5
4
4.5× 10
–9
VDS (V)
I D(A
)
Two effects:• diffusion current (like in
bipolar transistor)• exponential increase
with VDS (DIBL)
3−10x incurrenttechnologies
Slide 2.22
Gate-Induced Drain Leakage (GIDL)
Excess drain current is observed, when gate voltage is moved below VTH, and moves to negative values (for NMOS)
More pronounced for larger values of VDS
(or GIDL ~ VDG)
High electrical field between G and Dcauses tunneling and generation ofelectron–hole pairs
Causes current to flow between drain andbulk
Involves many effects such as band-to-band direct tunneling and trap-assistedtunneling
[Ref: J. Chen, TED’01]© IEEE 2001
Slide 2.23
Combining All Drain-Leakage Effects
–0.410–12
10–10
10–8
10–6
10–4
–0.2 0 0.2 0.4 0.6 0.8 1 1.2
VGS (V)
I D(A
)
VDS = 0.1 V
VDS = 1.0 V
VDS = 2.5 V
90 nm NMOS
GIDL
Slide 2.24
Gate Leakage
Silicon substrateSilicon substrate
1.2 nm SiO1.2 nm SiO22
GateGate
Scaling leads to gate-oxide thickness of a couple of molecules
MOS digital design has always been based on the assumption of infinite input resistance!Hence: Fundamental impact on design strategy!
Causes gates to leak!
Introduction of high-k dielectrics
[Ref: K. Mistry, IEDM’07]
Slide 2.25
Gate-Leakage Mechanisms
Direct-oxide tunneling dominates for lower Tox
1E–07
1E–08
1E–09
1E–10
1E–11
1E–12
1E–13
1E–14
1E–15© IEEE 2000
60–80 Å
<50 Å
Direct-oxide tunneling
FN tunneling
Iox/E2
A*cm2/MV2
0.1 0.15 0.21/E (MV/cm)–1
0.25
[Ref: Chandrakasan-Bowhill, Ch3, ‘00]
Slide 2.26
Direct-Oxide Tunneling Currents
VDD
J G(A
/cm
2)
0 0.3 0.6 0.9 1.2 1.5 1.8
10–9
10–6
10–3
10 0
10 3
10 6
10 9
Tox
0.6 nm0.8 nm
1.0 nm1.2 nm
1.5 nm
1.9 nm
VDD trend
Also - Gate tunneling a strong function of temperature- Larger impact for NMOS than PMOS
JG: exponential functionof oxide thickness andapplied voltage
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡Φ
−−
∝
αoxox
B
ox
TV
V
G eJ
/
)1(1 3/2
[Courtesy: S. Song, 01]
Slide 2.27
High-k Gate Dielectric
Equivalent Oxide Thickness = EOT = Tox = Tg * (3.9/εg), where 3.9 is relative permittivity of SiO2 and g is relative permittivity of high-k materialCurrently SiO2/Ni; Candidate materials: HfO2 ( eff ~15 –30); HfSiOx
( eff~12–16)– Often combined with metal gate
Electrode
Si substrate
Tox SiO2
Tg
High-k Material
Electrode
Si substrate
Reduced Gate Leakage for Similar Drive Current
εε
ε
Slide 2.28
High-k Dielectrics
Silicon substrateSilicon substrate
1.2 nm SiO1.2 nm SiO22
GateGate
Silicon substrate
Gate electrode
3.0nm High-k
Buys a few generations of technology scaling
High-k vs SiO2 Benefits
Gate capacitance
60% greater Faster transistors
Gate dielectric leakage
>100% reduction
Lower power
[Courtesy: Intel]
Slide 2.29
Gate Leakage Current Density Limit Versus Simulated Gate Leakage
[Ref: ITRS 2005]
Slide 2.30
Temperature Sensitivity
Increasing temperature– Reduces mobility– Reduces VTH
Ion decreases with temperatureIoff increases with temperature
0 10 20 30 40 50 60 70 80 90 1000
1
2
3
4
5
6
7
8
9
10× 10
4
Temp(°C)
I on/
I off
90 nm NMOS
IDS
VGs
increasingtemperature
Slide 2.31
Variability
Scaled device dimensions leading to increased impact of variations– Device physics
– Manufacturing
– Temporal and environmental
Impacts performance, power (mostly leakage) and manufacturing yield
More pronounced in low-power design dueto reduced supply/threshold voltage ratios
Slide 2.32
Variability Impacts Leakage
130 nm
30%
5X
0.90.9
1.01.0
1.11.1
1.21.2
1.31.3
1.41.4
11 22 33 44 55Normalized Leakage (Normalized Leakage (IsbIsb ))
No
rmal
ized
Fre
qu
ency
No
rmal
ized
Fre
qu
ency
Threshold variations have exponential impact on leakage[Ref: P. Gelsinger, DAC’04]
Slide 2.33
Variability Sources
Physical– Changes in characteristics of devices and wires.– Caused by IC manufacturing process, device
physics & wear-out (electro-migration).– Time scale: 109s (years).
Environmental– Changes in operational conditions (modes), VDD,
temperature, local coupling.– Caused by the specifics of the design
implementation.– Time scale: 10 to 10–9–6 s (clock tick).
Slide 2.34
Variability Sources and Their Time Scales
Slide 2.35
Process Variations
Percentage of total variation accounted for by within-die variation(device and interconnect)
[Courtesy: S. Nassif, IBM]Technology Node (nm)
0%
10%
20%
30%
40%
250 180 130 90 65
Leff
w, h, ρTox, VTH
3σ/m
ean
250 180 130 90 65 4520032
16%10.7%9.3%8.2%5.8%
L (nm)VTH (mV)σ(VTH) (mV)σ(VTH) /VTH
30280300330400450
21 23 27 284.7%
Slide 2.36
Threshold Variations Most Important for Power
10
100
1000
10000
1000 500 250 130 65 32Technology Node (nm)
Mea
n N
um
ber
of
Do
pan
t A
tom
s
Decrease of random dopants in channel increasesimpact of variations on threshold voltage
[Courtesy: S. Borkar, Intel]
Slide 2.37
Device and Technology Innovations
Power challenges introduced by nanometer MOS transistors can be partially addressed by new device structures and better materials– Higher mobility– Reduced leakage– Better control
However …– Most of these techniques provide only a one (or two)
technology generation boost– Need to be accompanied by circuit and system level
methodologies
Slide 2.38
Device and Technology Innovations
Strained siliconSilicon-on-InsulatorDual-gated devicesVery high mobility devicesMEMS – transistors
DG-SOI
FinFETGP-SOI
Slide 2.39
Strained Silicon
Improved ON-Current (10–25%) translates into:• 84–97% leakage current reduction• or 15% active power reduction
[Ref: P. Gelsinger, DAC’04]
Slide 2.40
Strained Silicon
Transistor Drive Current (mA/μm)
Tra
nsi
sto
r L
eaka
ge
Cu
rren
t(n
A/μ
m)
Improves Transistor Performance and/or Reduces Leakage
1000
100
10
10.2 0.4 0.80.6 1.0
[Ref: S. Chou, ISSCC’05]
1.2 1.4 1.6
Std Strain Std Strain
PMOS NMOS
+25% ION +10% ION
0.04 × IOFF
0.20 × IOFF
Slide 2.41
Beyond Straining
Hetero-junction devices allow for even larger carrier mobility
100
1000
10000
100000
5.2 5.4 5.6 5.8 6 6.2 6.4 6.6
Mob
ilit
y (c
m/s
)
Lattice Constant (Å)
ε Si
Ge, GaAs
InAs
InSbElectrons (intrinsic)Si + strain
Example: Si-Ge-Si hetero-structure channel
[Courtesy: G. Fitzgerald (MIT), K. Saraswat (Stanford)]
Slide 2.42
Silicon-on-Insulator (SOI)
Reduced capacitance (source and drain to bulk) results in lower dynamic powerFaster sub-threshold roll-off (close to 60 mV/decade)Random threshold fluctuations eliminated in fully-depleted SOIReduced impact of soft-errorsBut– More expensive– Secondary effects
Thin Oxide
Substrate
FD
S D
G
Thinsiliconlayer
[Courtesy: IBM]
Slide 2.43
[Ref: M. Yamaoka, VLSI’04, R. Tsuchiya, IEDM’04]
Example: Double-Gated Fully Depleted SOI
wellcontact
well
G (Ni silicide)
thin BOX(< 10nm)
thin SOI (< 20 nm)
wellSTI
sub
STI STI
sub
D S
VT control dopant(1018/cm3)
90 nm bulk
65 nm bulk
45 nm bulk
32 nm bulk
65 nm FD-SOI
45 nm FD-SOI
32 nm FD-SOI
Standard deviation (a.u.)210
σ (VT)σintσext
σintσextσ (VT )
0.5
0.4
0.3
0.5
High dose
Low dose
VDD = 1.0 V
w/o
tSOI = 20 nmtBOX = 10 nm
0.2
0.1
0.0
–0.11.00.0–0.5–1.0
0.6
Well-bias voltage Vwell (V)
Th
resh
old
vo
ltag
e V
TH
(V)
Buried gate provides accurate threshold control over wide range
© IEEE 2004
Slide 2.44
FinFETs – An Entirely New Device Architecture
UC Berkeley, 1999
S = 69 mV/decade• Suppressed short-channel effects• Higher on-current for reduced leakage• Undoped channel – No random dopant fluctuations
[Ref: X. Huang, IEDM’99]
© IEEE 1999
Slide 2.45
Drai
n
Sour
ce
Gate
Fin Height HFIN = W /2
Gate length = LG
TSi
Drai
n
ate
Sour
ce
Gate
Drai
nGate1
Sour
ce
SwitchingGate
Gate2Vth Control
Fin Height FIN
LG
nnnnnnnniiaaaaararrDDDDrai
n
Drai
n
Gate1
Sour
ce
HFIN =W
Back-gated (BG) MOSFETDouble-gated (DG) MOSFET
Independent front and back gatesOne switching gate and VTH control gate
Increased threshold control
Gate length =
Fin Width =
BackGated FinFET
Slide 2.46
Intel tri-gate
Berkeley PMOS FinFET
Manufacturability still an issue – may even cause more variations
GateDrain
Source
[Courtesy: T.J. King, UCB; Intel]
New Transistors: FinFETs
Slide 2.47
Some Futuristic Devices
FETs with sub-threshold swing < kT/q (I-MOS)
1.0E–11
1.0E–09
1.0E–07
1.0E–05
1.0E–03
0 0.2 0.4 0.6
VS = VD = 0V
5 mV/dec.I
ox
ON
OFF
I-MOS
MOS
VS = –1VVD = 0V
5 mV/dec.LI = 25 nmLG
Tox = 1 nmTsi = 25 nm
ON
OFF
I-MOS
MOS
N+P+ I-MOS
Buried-Oxide
Poly
Impact Ionization Region
N+P+ I-MOS
Buried Oxide
Poly
Impact Ionization Region
[Courtesy: J. Plummer, Stanford]
Zero off-current transistorUses MEMS technology to physically change gate control.Allows for zero-leakage sleeptransistors and advanced memories[Ref: Abele05, Kam05]
© IEEE 2005
= 25 nm
Slide 2.48
Summary
Plenty of opportunity for scaling in the nanometer age
Deep-submicron behavior of MOS transistors has substantial impact on design
Power dissipation mostly influenced by increased leakage (SD and gate) and increasing impact of process variations
Novel devices and materials will ensure scaling to a few nanometers
Slide 2.49
ReferencesBooks and Book Chapters
A. Chandrakasan, W. Bowhill, and F. Fox (eds.), “Design of High-Performance Microprocessor Circuits”, IEEE Press 2001.
J. Rabaey, A. Chandrakasan, and B. Nikolic, “Digital Integrated Circuits: A Design Perspective,”2nd ed, Prentice Hall 2003.Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998.
ArticlesN. Abele, R. Fritschi, K. Boucart, F. Casset, P. Ancey, and A.M. Ionescu, “Suspended-Gate MOSFET: Bringing New MEMSFunctionality into Solid-State MOS Transistor,” Proc. Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp.479–481, Dec. 2005
BSIM3V3 User Manual, http://www.eecs.berkeley.edu/Pubs/TechRpts/1998/3486.htmlJ.H. Chen et al., “An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET,” IEEE Trans. On Electron Devices, 48(7), pp. 1400–1405, July 2001.
S. Chou, “Innovation and Integration in the Nanoelectronics Era,” Digest ISSCC 2005, pp. 36–38, February 2005.P. Gelsinger, “Giga-scale Integration for Tera-Ops Performance,” 41st DAC Keynote, DAC, 2004, (www.dac.com)
X. Huang et al., "Sub 50-nm FinFET: PMOS,” International Electron Devices Meeting Technical Digest, p. 67. Dec. 5–8, 1999.
International Technology Roadmap for Semiconductors, http://www.itrs.net/
H. Kam et al., “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics, “IEDM Tech.Digest, pp. 463–466, Dec. 2005.K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nmDry Patterning, and 100% Pb-free Packaging,” Proceedings, IEDM, p. 247, Washington, Dec. 2007.
Predictive Technology Model (PTM), http://www.eas.asu.edu/~ptm/T. Sakurai and R. Newton. “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas.,” IEEE Journal of Solid-State Circuits, 25(2), 1990.
R. Tsuchiya et al., “Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control,” Proceedings IEDM 2004, pp. 631–634, Dec. 2004.
M. Yamaoka et al., “Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology,” Digest of Technical Papers VLSI Symposium, pp. 288–291, June 2004.W. Zhao, Y. Cao, “New generation of predictive technology model for sub-45nm early design exploration,” IEEE Transactions on Electron Devices, 53(11), pp. 2816–2823, November 2006
Slide 2.50
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