m ultiprocess synchronization algorithms (20225241)

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M ultiprocess Synchronization Algorithms (20225241). Global Computation. Lecturer: Danny Hendler. Model. P 1 : 17. P 3 : 46. P 0 : 4. P 2 : -6. Processes are represented by graph nodes, each node stores an input value Bi-directional communication links Asynchronous - PowerPoint PPT Presentation

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Multiprocess Synchronization

Algorithms (20225241)

Lecturer: Danny Hendler

Global Computation

2

ModelP0: 4

• Processes are represented by graph nodes, each node stores an input value

• Bi-directional communication links

• Asynchronous

• Links may fail-stop but connectivity is assured (safe network)

• Failures cannot be detected.

We let n, m respectively denote the number of nodes and links.

P1: 17

P2: -6

P3: 46

3

Global computation

We need to compute a global sensitive function of process inputs

P0: 4 P1: 17

P2: -6

P3: 46

Definition

An n-variate function F is global sensitive, if there is an n-tuple,v1, …, vn, such that the following holds:

i {1,…. n} ui: F(v1,…, vi,…vn) ≠ F(v1,…, ui,…vn)

To compute a global sensitive function, we need to see ALL inputs.

4

Global computation

We need to compute a global sensitive function of process inputsDefinition

An n-variate function F is global sensitive, if there is an n-tuple,v1, …, vn, such that the following holds:

i {1,…. n} ui: F(v1,…, vi,…vn) ≠ F(v1,…, ui,…vn)

Examples:Max, sum, xor, …

5

Global computation algorithm

Every process broadcasts its input to all other processes.

Worst-case message complexity:Ω(mn)

Can we do better (in all networks)?

6

A lower bound for a ring

Theorem

The worst-case message complexity of any non-uniform global computation algorithm on a safe ring is Ω(n log n).

77

Global Computation in a ring

p1 p2 p3 p4 Pn-1 Pn

p0

e1 e2 e3 en-1

Computation starts here

88

Global Computation in a ring (cont'd)

p0

Computation starts here

p1 p2 Pn-1 Pn

e1 en-1

pn/4 pn/4+1p3n/4 p3n/4+1

en/4e3n/4

BP1

UV1

99

el em er

BPi={el, er}

UVi

el em

Bpi+1={el, em} e

m

er

Bpi+1={em, er}

Execution Evolution

101010

Proof of Lemma 3

p0

p1 p2 Pn-1 Pn

e1 en-1

pl pl+1pr pr+1

eler

BPi

em

Execution Er involves these processes only

Execution El involves these processes only

111111

Proof of Lemma 3 (cont'd)

p0

p1 p2 Pn-1 Pn

e1 en-1

pl pl+1pr pr+1

eler

BPi

em

Execution ElEr results when we connect both el and er and block em

By failing em we prove the algorithm incorrect.

12

Generalizing to networks other than rings

Theorem

For every n, mO(n2), there exists a safe network with θ(n) nodes and θ(m) links, on which the worst-case message complexity of any global computation is Ω(m log n).

13

The graph G(n,m)

p1 p2 p3 p4 Pn-1 Pn

p0

bl1 bl2 bl3 blk

tl1 tl2 tl3 tlk

br1 br2 br3 brk

tr1 tr2 tr3 trk

k=√m

CutL CutR

Path

e1 e2 e3 en-1

14

Phase 0

p1 p2 Pn-1 Pn

p0

bl1 bl2 bl3 blk

tl1 tl2 tl3 tlk

br1 br2 br3 brk

tr1 tr2 tr3 trk

k=√m

CutL CutR

e1 en-1

pn/4 pn/4+1p3n/4 p3n/4+1

en/4e3n/4

BP1

UV0

15

Messages delay rule

p1 p2 Pn-1 Pn

p0

bl1 bl2 bl3 blk

tl1 tl2 tl3 tlk

br1 br2 br3 brk

tr1 tr2 tr3 trk

k=√m

CutL CutR

e1 en-1

pn/4 pn/4+1p3n/4 p3n/4+1

en/4e3n/4

BP1

UV0

Disable communication between p0 and path

until either CUTL or CUTR

is saturated

16

Messages delay rule (cont’d)

p1 p2 Pn-1 Pn

p0

bl1 bl2 bl3 blk

tl1 tl2 tl3 tlk

br1 br2 br3 brk

tr1 tr2 tr3 trk

k=√m

CutL CutR

e1 en-1

pn/4 pn/4+1p3n/4 p3n/4+1

en/4e3n/4

BP1

UV0

Disable communication between p0 and path

until either CUTL or CUTR

is saturated

17

Messages delay rule (cont’d)

p1 p2 Pn-1 Pn

p0

bl1 bl2 bl3 blk

tl1 tl2 tl3 tlk

br1 br2 br3 brk

tr1 tr2 tr3 trk

k=√m

CutL CutR

e1 en-1

pn/4 pn/4+1p3n/4 p3n/4+1

en/4e3n/4

BP1

UV0

Then unblock all edges except for BPi

1818

A lower bound for uniform global computation on a

ring

Theorem

The worst-case message complexity of any uniform global computation algorithm on a safe ring is Ω(n2).

19191919

Key Argument of Lemma 7: Since n is unknown, can’t distinguish between

thesep0

p1 p2 Pn-1 Pn

e1 en-1

pl pl+1pr pr+1

eler

p1 p2 Pn-1 Pn

e1 en-1

pl pl+1pr pr+1

eler

p1 p2 Pn-1 Pn

e1 en-1

pl pl+1pr pr+1

eler

p1 p2 Pn-1 Pn

e1 en-1

pl pl+1pr pr+1

eler

p1 p2 Pn-1 Pn

e1 en-1

pl pl+1pr pr+1

el er

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