lecture 2: limiting models of instruction obeying machine 虞台文 大同大學資工所...

Lecture 2:Limiting Models ofInstruction Obeying Machine

虞台文大同大學資工所智慧型多媒體研究室

Content Machine Simulation and Equivalence Unlimited-Register Machine

Lecture 2:Limiting Models ofInstruction Obeying Machine

Machine Simulation and Equivalence

大同大學資工所智慧型多媒體研究室

Computer as a Partial Function

M a machine an M-program:e X M:d M Y

an encoding function a decoding function

Me d

input output

Computer as a Partial Function

d eM

Me d

input output

A partial function

Machine Equivalence

Input(X)

Output(Y)

1Me d:f X Y 1d e M

Machine Equivalence

Input(X)

Output(Y)

1Me d:f X Y

2 M

g h

1 2h g M M

1d e M

2d eh g M :f X Y

Machine Equivalence

Input(X)

Output(Y)

1Me d:f X Y

2 M

g h

1 2h g M M

1d e M

2d eh g M :f X Y

e d

2d e M

Machine Equivalence

Input(X)

Output(Y)

e d:f X Y

2 M

g h

1 2h g M M

2d e M

e d

d d h e g e

Machine Equivalence

Input(X)

Output(Y)

:f X Y

2 M

1 2h g M M

e d

d d h e g e

2d e M

Machine Equivalence Defined

1 2, :M M

::

two machines

M1-programM2-program

1 2, :M M Memory sets of M1 and M2.

11 1: M MM

22 2: M M M g h

g, h such that1 2h g M M

Machine Equivalence Defined

11 1: M MM

22 2: M M M g h

g, h such that1 2h g M M

:f X YLet can be computed on M1 using , i.e., 1f d e M

2( ) ( )f d h g e M

f can be computed on M2 using ’, with

encoding function

decoding function2:e g e X M

2:d d h M Y

1f d e M

2f d e M

Machine Simulation Defined

A machine M2 simulates M1 if

1 2

2 1

:

:gh

M MM M

such that

we can specify an algorithm which given any program produces ’ satisfying

1 2h g M M

Machine Simulation Defined

A machine M2 simulates M1 if

1 2

2 1

:

:gh

M MM M

such that

we can specify an algorithm which given any program produces ’ satisfying

1 2h g M M

Problems: 1. What is the algorithm?2. How to find g and h?

TheoremA machine M2 simulates M1 if

1 2

2 1

:

:gh

M MM M

such that

we can specify an algorithm which given any program produces ’ satisfying

1 2h g M M

The memory encoder g has to be one to one.

M2 simulates M1

Theorem

ConsiderPf)

START HALT: Identity

1 ( ) ( )m m m M I

The memory encoder g has to be one to one.

M2 simulates M1

Suppose that g is not one to one.Then, g(m1) = g(m2) = M for some m1m2.

1 2h g M M M2 simulates M1

1 21 1( ) ( )m h g m M M 2 ( )h M M

1 1 21 12 , ( ) ( )m m m m M M

1 22 2( ) ( )m h g m M M 2 ( )h M M

Stepwise SimulationM2 stepwise simulates M1 if

1-to-1 encoding function g:M1M2 such that1) For each FF,

2) For each PP,

F: the set of operation functions of M1.P: the set of predicates of M1.

a program F in M2 such that 1 2 FFg gM M

a program P in M2 such that

1

2 1

1

( )P

P

P

P

true m trueg m false m false

m

MM M

M

and P doesn’t change M2.

Stepwise SimulationM2 stepwise simulates M1 if

1-to-1 encoding function g:M1M2 such that1) For each FF,

2) For each PP,

F: the set of operation functions of M1.P: the set of predicates of M1.

a program F in M2 such that 1 2 FFg gM M

a program P in M2 such that

1

2 1

1

( )P

P

P

P

true m trueg m false m false

m

MM M

M

and P doesn’t change M2.

FF 1 2 FFg gM M

g

gF F

m m

1 ( )F mM2 ( )

Fm M

Stepwise SimulationM2 stepwise simulates M1 if

1-to-1 encoding function g:M1M2 such that1) For each FF,

2) For each PP,

F: the set of operation functions of M1.P: the set of predicates of M1.

a program F in M2 such that 1 2 FFg gM M

a program P in M2 such that

1

2 1

1

( )P

P

P

P

true m trueg m false m false

m

MM M

M

and P doesn’t change M2.

PP P truefalse truefalse P

m ( )g m

m ( )g mm ( )g m

Stepwise Simulation

M2 stepwise simulates M1

M2 simulates M1

SR4

Memory set4SRM

4SRM N N N N

4 registers (x1, x2, x3, x4)

Operations4SRF

Predicates4SRP

1i ix x 1i ix x

for i = 1, 2, 3, 4.

0?ix for i = 1, 2, 3, 4.

Review PC

Memory set PCM

PCM N N

2 registers (x, y)

Operations PCF

Predicates PCP

1x x 1x x

0?x

1y y 1y y

0?y ?x y

y x y y x y

Does PC Simulates SR4?Does SR4 Simulates PC?

Prove PC Simulates SR4

Step 1:

Step 2:

Step 3:

Define a 1-to-1 encoding function 4: SR PCg M M

For each FFSR4, find a F on PC such that …

For each PPSR4, find a P on PC such that …

: , , , 2 3 5 7 ,0i j k lg i j k l

To be shown

Exercise

FSR4 PC

F

1i ix x 1i ix x

1i ix x 1i ix x

FF

11i ii i x xx x

FF 1 11 1 11 x xx x

START

0?x

1x x

1y y

1y y

0?y

1y y

1x x

false

truefalse

HALTtrue

20

y xx

0x y

y

11i ii i x xx x

FF 1 11 1 11 x xx x

2 22 2 11 x xx x

3 33 3 11 x xx x

4 44 4 11 x xx x Exercise

11i ii i x xx x

FF 1 11 1 11 x xx x

HALT

START

2 | x?yxx0

/ 2x y 0x y

y

true false

START

0?x

1x x

1y y

false

true

0?x

1x x

1y y

true

false

FALSEHALT

TRUEHALT

2 | x?

Prove PC Simulates SR4

Step 1:

Step 2:

Step 3:

Define a 1-to-1 encoding function 4: SR PCg M M

For each FFSR4, find a F on PC such that …

For each PPSR4, find a P on PC such that …

: , , , 2 3 5 7 ,0i j k lg i j k l

To be shown

Exercise

In fact, SR2 also simulates SR4.Why?

Discussion

PC SR4

SR2

SR

Is SR more powerful than SR2? No.Is SR more powerful than PC? Not sure, now.

Lecture 2:Limiting Models ofInstruction Obeying Machine

Unlimited-Register Machine

大同大學資工所智慧型多媒體研究室

The Unlimited-Register Machine

Unlimited number of registers. Unbounded capacity of every register. Powerful instructions

The Machine RMemory set

Operations RF Predicates RP

10, 0R i i ii

M n n n

except fi nite many

That is, for some, k 1, ni = 0 for all i k(finite memory are used).

ix m

i jx x m

i jx x m

i jx x m

i jx x m

i jx x

i j kx x x

i j kx x x

i j kx x x

i j kx x x

?ix m

?ix m

?i jx x

?i jx x

Input & Output Registers of R

1 1 22,, , ,, ,, ,, kR lw wu wuM u

k inputregisters

l outputregisters

Other registers can be working registers if necessary.

Running R1 1 22,, , ,, ,, ,, kR lw wu wuM u

: a program in Re : encoder

d : decoder11 1: , , 0, ,0, , , ,0,k kkue x x xux

1 1 1: , , , , , ,l l ld y w yw y y

: -tuple -tupled e k lR

SR

Memory set SRM

The same as R

Operations & Predicates 1i ix x

1i ix x i = 1, 2, …

0?ix

Machine Simulations

SRRSimulates?

Simulates?

Of course.

Not sure, now.

Prove SR Simulates R

Step 1:

Step 2:Step 3:

?g

1 1 1: , , 0, , 0, , , ,0,k w kg x x y y x x

FF PP

w working registers

ix m

i jx x m

i jx x m

i jx x m

i jx x m

i jx x

i j kx x x

i j kx x x

i j kx x x

i j kx x x

?ix m

?ix m

?i jx x

?i jx x

Prove SR Simulates R

Step 1:

Step 2:Step 3:

?g

1 1 1: , , 0, , 0, , , ,0,k w kg x x y y x x

FF PP

w working registers

ix m

i jx x m

i jx x m

i jx x m

i jx x m

i jx x

i j kx x x

i j kx x x

i j kx x x

i j kx x x

?ix m

?ix m

?i jx x

?i jx x

Converted to register-mode operation by using a working

register.

Prove SR Simulates R

i ji j x x mx x m

START

y m

i jx x y

0y

HALT

??ii x mx m

>=START

y m

0y

TRUEHALT

?ix y

0y

FALSEHALT

true false

Prove SR Simulates Ri j kx x x i j kx x x

HALT

START

y xk

y>0 ?

xi 0

xi xi + xj

true

false

y y 1

HALT

START

y xj

xk>0 ?

xi 0

y y xk

true

false

xk>y ?

y 0

true

false

xi xi + 1

Prove SR Simulates Ri j kx x x i j kx x x

HALT

START

y xk

y>0 ?

xi xj

true

false

xi xi + 1

y y 1

HALT

START

y xk

y>0 ?

xi xj

true

false

xi xi 1

y y 1

Prove SR Simulates Ri jx x

HALT

START

y 0

xj>0?

xi 0

true

false

xj xj 1

xi xi + 1

y y + 1

y>0?true

xj xj + 1

y y 1

false

i i jx x x

HALT

START

y xi + xj

xi y

y 0

Prove SR Simulates R

?i jx x ?i jx x

START

y xi xj

y>0 ?true

TRUEHALT

FALSEHALT

false

START

false

TRUEHALT

FALSEHALT

truexj > xi?

xi > xj?false

Exercise

Using SR to Simulate R, at least how many working registers are required?

Discussion

PC SR4

SR2

SR R

Discussion Machine equivalence is reflexive, symmetric,

and transitive, i.e., an equivalence relation. SR2 is the same powerful as R. To study computation, considering PC, SR2, SR4,

SR or R is equally well. The above machines are register machines.

Register FunctionsUse x1, …, xk as input registers of R.Let fi: Nk N be the function computed by an R-program using xi as the output register.We call the k functions f1, …, fk the (k-adic) register functions of .We will considered register functions (the class of all k-adic, k1, register functions) to be functions that are computable by R.

Examples

START

x1 x3 5

x2 x1 + x3

HALT

1 2 3 4 5, , , ,x x x x x

3 2 3 4 55 , , , ,x x x x x

3 3 3 4 55 ,6 , , ,x x x x x

1 2 3 4 5 31 : , , , , 5x x x xf x x

1 2 3 4 5 32 : , , , , 6x x x xf x x

1 2 3 43 5 3: , , , ,x x x x xf x

1 2 3 44 5 4: , , , ,x x x x xf x

1 2 3 45 5 5: , , , ,x x x x xf x