lecture 10 processor microarchitecture (part 1)

Xuan ‘Silvia’ Zhang Washington University in St. Louis

http://classes.engineering.wustl.edu/ese566/

Lecture 10 Processor Microarchitecture (Part 1)

Key Concepts in Computer Architecture

•  Transaction latency –  the time to complete a single transaction

•  Execution time/total latency –  the time to complete a sequence of transactions

•  Throughput –  the number of transaction executed per unit time

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Analyzing Processor Performance

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Analyzing Processor Performance

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Transactions and Steps

•  Each instruction as a transaction •  Executing a transaction involves a sequence of steps

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Microarchitecture: Control/Datapath Split

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PARCv1 Single-Cycle Processor

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High-level Idea for Single-Cycle Processors

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Single-Cycle Datapath

•  Implement ADDU instruction •  Implement ADDIU instruction

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Single-Cycle Datapath

•  Implement ADDU instruction •  Implement ADDIU instruction

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Adding MUL Instruction

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Adding LW and SW Instructions

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Adding J Instruction

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Adding JAL and JR Instructions

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Adding BNE Instruction

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Quiz: Adding a New Auto-Incrementing Load Instruction

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Single-Cycle Processor Control Unit

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Estimating Cycle Time—Longest Critical Path

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PARCv1 FSM Processor

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FSM Processor Datapath

•  Implement fetch sequence

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FSM Processor Datapath

•  Implement ADDU sequence

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Full Datapath for PARCv1 FSM Processor

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Adding a Complex Instruction

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Quiz: Adding a New Auto-Incrementing Load Instruction

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Questions?

Comments?

Discussion?

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Acknowledgement

Cornell University, ECE 4750

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