iedm 32nm soc with rf presentation - intel · c.-h. jan, dec/10 iedm ’10, san francisco m1 m2 m3...
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RF CMOS Technology Scaling in High-k/Metal Gate Era
for RF SoC (System-on-Chip) Applications
Chia-Hong Jan
M. Agostinelli, H. Deshpande, M.A. El-Tanani, W. Hafez, U.
Jalan, L. Janbay, M. Kang, H. Lakdawala*, Y-L Lu, S. Mudanai, J. Park, A. Rahman, J. Rizk, W.-K. Shin, K. Soumyanath*, H. Tashiro, C. Tsai, P. Vandervoorn, J.-Y. Yeh, P. Bai
Logic Technology Development (LTD), TMG*Radio Integration Research (RIR), Intel Labs
Hillsboro, Oregon, USA
Intel Corporation
Metal Gate
High - k
SiGe
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Introduction - RF SoC and RF CMOS
CMOS Scaling Trend
RF CMOS Scaling
RF CMOS Designs – PA, LNA, Wireless Transceivers
Conclusions
Outline
2
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
SoC and RF SoC (Radio Frequency System-on-Chip)
Nettop/Netbook
MID
DTV
Embedded Pocket Device
Server
Desktop
Laptop
CPU SoC RF SoC
SatelliteTerrestialBroadcast
RF SoC SoC derivatives with integrated RF and communication IPs
60 GHz
Blue Tooth
3
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
RF SoC - RF Systems Integration
RX Mixer
TX Mixer
ADC
DAC
MA
C/B
ase
ba
nd
PLLRFSynth
LNA
PA
T/RSwitch
(RF Front End) (RF IC) (MAC/BB)
Ap
ps
Pro
cess
or
Antennas
Front EndModule (III-V)
•Switches/PA
•Filters
Baseband (PHY)/MAC
RFIC (RFCMOS /BiCMOS)
•VCO
•LNA
Integration of RF subsystem into an advanced CMOS platform
Is CMOS scaling capable of meeting RF system requirements ?
4
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
M1
M2
M3
M4
M5
M6
M7
M8
Thick Metal
V0
V2
V1
V3
V4
V5
V6
V7
V8
Transistor
SubstrateWell
Transistor:
− Logic, low power, I/O
− JFET, BJT
Well: Triple Well/Deep Nwell
Substrate: High Resistivity
HV PA Transistor
TM1 Inductor: high Q and density
Deep Nwell
High k/Metal Gate
Pwell
P- epi
Passives:
Precision Resistor
High Q Inductor
High Density Decap
RF Transistor: Templates/Modeling
32 nm RF CMOS Technology
Vcc
HV PA
5
NFmin
RF Models
Basic 32 nm CMOS technology is expanded with many more
mixed signals/RF features to meet RF SoC requirements
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Introduction - RF SoC and RF CMOS
CMOS Scaling Trend
RF CMOS Scaling
RF CMOS Designs – PA, LNA, Wireless Transceivers
Conclusions
Outline
6
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Intel CMOS Transistor Architecture Evolution in the Last Decade
.13 um and before 90nm/65 nm 45 nm/32 nm
Traditional Strained Silicon High k/Metal Gate +Strained Silicon
CMOS scaling has evolved from classical dimensional scaling to modern scaling with innovations in structures and materials
7
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
CMOS Scaling Challenges - Cox
8
1
10
0.55
um
0.35
um
0.25
um
0.18
um
0.13
um
90 nm 65 nm 45 nm 32 nm
Ele
ctri
cal (
Inv
) To
x (
nm
)
Technology Node
20 )VV(L
W)
T
k(
2
1I tg
ef finvef fdsat
High-k
Metal GateStrained Si
Strained silicon implementation at 90 nm compensated the lack of Tox scaling
Metal Gate
High - k
SiGe
Non-strained
Oxide/Poly
Tox = 0.7x/gen
Strained Si
Oxide/Poly
High k/Metal Gate
Hi-k/metal gate implementation at 45 nm recovered Tox scaling
Constant field oxide scaling not sustainable beyond .13 um (high gate leakage)
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
100
1000
1995 2000 2005 2010
Gate
Pitch
(nm)0.7x every
2 years
32nm
65nm
45nm
112.5 nm
PitchPitchPitch
Moore’s Law Continues on CMOS ……
0
0.5
1
1.5
2
1001000
Idsa
t (m
A/u
m)
and
Rel
ativ
e G
m
Gate Pitch ( nm )
Relative Gm
NMOS Idsat
Idsat @ 1V,
100nA/um Ioff
Hi-k/Metal Gate
Strained Silicon
Oxide/Poly Gate
Strained SiliconOxide/Poly Gate
Non-Strained Si
0.13 um
90 nm65 nm
45 nm
32nm
Innovations of strained silicon and high k/metal gates enabled Moore’s law scaling with continuous ~ 30% /gen. performance/gm enhancement
9
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Introduction - RF SoC and RF CMOS
CMOS Scaling Trend
RF CMOS Scaling
RF CMOS Designs – PA, LNA, Wireless Transceivers
Conclusions
Outline
10
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
RF CMOS Technology Performance Metrics
11
RF CMOS scaling
focuses on a
different set of
performance metrics
(fT, noise, Q factor
and so on) from basic
CMOS technology
RF Devices RF CircuitsKey Device
Characteristics
Logic TransistorMAC/BB, ADC, DAC
Idsat, Idlin, Vt, Ioff
Analog TransistorADC, DAC, MAC/BB
Gm, Rout, Matching, Linearity, Noise, NFmin
RF TransistorPA, Mixer, T/R Switch
fT, fmax, 1/f Noise, NFmin
PA Transistors PARon, Linearity, fT, fMAX, Efficiency, Breakdwn V,
Precision ResistorsADC, DAC, BB Filter, others
R, R/R, Matching
Linear Capacitors PLL, VCO C, Q, Matching
Varactors PLL, VCO Tuning Ratio, Q, Kvco,
Inductor/Transformer/Balun
PA, LNA, Mixer L, Q
What are the impacts of CMOS scaling on these metrics ?
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
32 nm RF CMOS Cut-off Frequency fT – 445 GHz !
0
10
20
30
40
50
60
1 10 100 1000
Ma
son
's U
, H2
1 (d
B)
Frequency (GHz)
26nm x 0.6um x 50VGS=0.6V, VDS=1V
fMAX=230 GHz
fT=445 GHz
DUT Open Short
De-embeding Structures
12
NMOS
De-embedded to M1 (inlcuded)
7% faster than previous result from gm improvement
A new 32 nm NMOS RF CMOS record 445 GHz fT achieved
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
0
100
200
300
400
500
0.01 0.1 1
Cu
t-o
ff F
req
ue
ncy
, fT
(G
Hz)
Ids (mA/um)
90 nm(peak fT= 209 GHz)
0
100
200
300
400
500
0.01 0.1 1
Cu
t-o
ff F
req
ue
ncy
, fT
(G
Hz)
Ids (mA/um)
90 nm(peak fT= 209 GHz)
65 nm(peak fT= 360 GHz)
Cut-off frequency fT started from 200 GHz at 90 nm,
0
100
200
300
400
500
0.01 0.1 1
Cu
t-o
ff F
req
ue
ncy
, fT
(G
Hz)
Ids (mA/um)
90 nm(peak fT= 209 GHz)
65 nm(peak fT= 360 GHz)
45 nm(peak fT= 395 GHz)
0
100
200
300
400
500
0.01 0.1 1
Cu
t-o
ff F
req
ue
ncy
, fT
(G
Hz)
Ids (mA/um)
90 nm(peak fT= 209 GHz)
65 nm(peak fT= 360 GHz)
45 nm(peak fT= 395 GHz)
32 nm (peak fT= 445 GHz)
to 360 GHz at 65 nm,
to 395 GHz at 45 nm (HK/MG), to the new record of 445 GHz at 32 nm HK/MG
RF Cut-off Frequency fT Scaling Trend
13
2x
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
CMOS Scaling on RF - Cut-off Frequency fT
gg
mT
C2
gf
p
[2] K. Kuhn et al., VLSI Technology Symp., p. 224 (2004)[5] I. Post et al, IEDM Tech Dig., pp. 1-3 (2006)[8] C.-H. Jan et al, IEDM Tech. Dig., pp. 637-640 (2008)[11] P. VanDerVoorn et al, VLSI Tech. Symp., p. 137 (2010)
S D
G
0
100
200
300
400
500
0 0.02 0.04
Cu
t-o
ff F
req
ue
ncy
, fT
(GH
z)
1/Lg (nm-1)
'07 ITRS
'09 ITRS
90 nm [2]
65 nm [5]
45 nm [8]
32 nm [11]
32 nm (this work)
Record fT 445 GHz, closing gaps to SiGe HBT and III-V devices
fT improvement ~ 20-30% per gen
gm improvement dominating (thanks to CMOS technology scaling !)
Cgg effects somewhat mixed
Parasitics and layout optimization critical for future scaling
14
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
CMOS Scaling on RF - 1/f Flicker Noise
10x 1/f flicker noise improvement over five nodes
Enabled by Cox scaling from high-k
Interface engineering to stabilize
process factor K
2ox
2m
id
C
1
f
KLW
g
SLWSvg
<Id2>
S D
G
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
10 100 1000 10000 100000
Svg
*W*L
(V
2/u
m2
/Hz)
Frequency (Hz)
32 nm, Vds=0.9V
45 nm, Vds=1.0V
65 nm, Vds=1.1V
90 nm, Vds=1.0 V
0.13 um, Vds = 1.3 V
0.13 um
90 nm
65 nm
45 nm
32 nm
10
x
2ox
2m2
2d
CLW
g
f
K)fnE(tN)N
1(LWf
ITkIdS
15
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
1.E-11
1.E-10
1.E-09
1.E-08
Svg
*W*L
(V
2-u
m2
/Hz)
@ 1
Hz
Technology Node
this
work
High-k/
Metal Gate
RF 1/f Flicker Noise Scaling Trend
1/f flicker noise scaling, 10x reduction from 0.13 um to 32 nm, enabled by HK/MG Tox scaling and interface engineering
16
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
0
1
2
3
0 10 20
NF
min
(dB
)
Frequency (GHz)
0.18 um [2]
90 nm [2]
32 nm [11]
45 nm
CMOS Scaling on RF - Noise Figures
[2] K. Kuhn et al., VLSI Technology Symp., p. 224 (2004)[5] I. Post et al, IEDM Tech Dig., pp. 1-3 (2006)[8] C.-H. Jan et al, IEDM Tech. Dig., pp. 637-640 (2008)[11] P. VanDerVoorn et al, VLSI Tech. Symp., p. 137 (2010)[12] C.-H. Jan et al, IEDM Tech Dig., (2010)
NFmin improved to < 1 dB level after 45 nm node
gm improvement needs to balance gate cap and gate resistance increase
Layout optimization becomes critical for future scaling
)RR(g
Cf2K1)RR(g
f
fK1NF sg
m
ggsgm
Tmin
p
17
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
RF Noise Figure Scaling Trend
0.1
1
0 0.01 0.02 0.03 0.04
NF
min
(dB
)
1/Lgate (nm-1)
Literature
this work
Noise figure NFmin scaling to a low level after 45 nm node
18
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
CMOS Scaling on RF – Deep Nwell
N+ N+
N+
P+ P+
P+
p-epi
n-well p-well
P-well in CMOS twin-well architecture
N+ N+
N+
P+ P+
P+
p-epi
n-well p-well
Deep n-well
Deep n-well in triple-well architecture with MeV implants at older technology
19
1.E+14
1.E+15
1.E+16
1.E+17
1.E+18
0 1 2 3 4D
op
an
t C
on
c. (
arb
. un
it)
Junction Depth (um)
0.13 um Pwell
0.13 um Pwell
1.E+14
1.E+15
1.E+16
1.E+17
1.E+18
0 1 2 3 4D
op
an
t C
on
c. (
arb
. un
it)
Junction Depth (um)
0.13 um Pwell / Deep_Nwell
0.13 um Deep Nwell
0.13 um Pwell
1.E+14
1.E+15
1.E+16
1.E+17
1.E+18
0 1 2 3 4D
op
an
t C
on
c. (
arb
. un
it)
Junction Depth (um)
Pwell / Deep_Nwell Scaling
0.13 um Deep Nwell
0.13 um Pwell
32 nm Deep Nwell
32 nm Pwell
Deep n-well depth scaled by 2.5x from 0.13 um to 32 nm. Deep n-well integration is now more manufaturable with sub-MeV implants
Junction Depth (arb. unit)
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Deep Nwell Applications for M/S RF
-100
-80
-60
-40
-20
0
20
0.1 1 10
Iso
lati
on
(d
B)
Freq (GHz)
No Deep Nwell
Deep Nwell
- 50 dB
Substrate noise isolation ( ~ 50dB)
0
0.1
0.2
0.3
0.4
0.5
0 1 2 3
Co
lle
cto
r C
urr
en
t, I C
(mA
)
Collector-Emitter Voltge, VCE (V)
IB =
50uA
40uA
30uA
20uA
10uA
CMOS p-JFET0
0.05
0.1
0 1 2 3 4 5
I D(m
A)
VDS (V)
VBS = -5 V
- 4 V
- 3 V
- 2 V
- 1 V
CMOS Parasitic NPN BJT
P+N+ N+
Deep n-well
p-epi
N+
p-well
G DS
N+
N+
BDNW
P+ P+N+ N+
Deep n-well
p-epi
N+
p-well
G DS
P+ P+N+ N+
Deep n-well
p-epi
N+
p-well
E B C
20
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
1/f Flicker Noise Reduction by BJT (via Deep Nwell)
1E-22
1E-21
1E-20
1E-19
1E-18
1E-17
1E-16
1E-15
10 100 1000 10000 100000
Sid
Freq (Hz)
Id=Ic=0.
32 nm CMOS
32 nm BJT via
CMOS/Deep Nwell
Id = Ic = 0.3mA
10
0 x
BJT immune to oxide interface charge trapping/de-trapping (source of 1/f flicker noise)
100x flicker noise reduction measured on BJT (via CMOS/Deep Nwell)
Applications in RF mixer circuits requiring very low flicker noise
P+ P+N+ N+
Deep n-well
p-epi
N+
p-well
E B C
21
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
CMOS Scaling on RF – Voltage Scaling
0
1
2
3
4
5
Vcc
(Vo
lt)
Technology Node
Intel Core and I/O Vcc Scaling Trend
Core Vcc
0
1
2
3
4
5
Vcc
(Vo
lt)
Technology Node
Intel Core and I/O Vcc Scaling Trend
Core Vcc
Vcc
HV PA
-1.5
-1
-0.5
0
0.5
1
1.5
0 1200
-1.5
-1
-0.5
0
0.5
1
1.5
0 1200
Vp > Vcc
RLo
ad
RFC
BFC
Transformer Matching Network
PoutPin
Pdc
dc
inout
in
out
P
PPPAE
P
PGain
X
0
0.5
1
1.5
2
2.5
0 2 4 6 8 10
ID [
mA
/um
]
VDS [V]
3.3 V I/O
Transistor
HV PA
Transistor
CMOS voltage scaling not favored for high voltage needs of RF (PA)
New high voltage PA transistors are developed to support HV needs
[11] P. VanDerVoorn et al, VLSI Tech. Symp., p. 137 (2010)
22
3.3 V
Vcc
HV PA
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Cu
4.5 umTM
(Thick Metal)
M1 – M8Interconnects
Polymer0.13 um 6 layers
32 nm 8 layers
CMOS Interconnect Scaling
Interconnect scaling adversely impacts quality factor of RF Passives.Thick metal (TM) solves the dilemma. Inductor Q of 25 achieved
23
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Metal spiral Inductor Q progressively degraded with the scaling of interconnect pitch and metal thickness (Q = wL/R)
0
10
20
30
0
500
1000
1500
.13 um 90 nm 65 nm 45 nm 32 nm
Ind
uct
or
Q (
pe
ak
)
Top
In
terc
on
ne
ct P
itch
(n
m)
Technology Node
inductors by top metal layers (excluding Thick Metal)
24
CMOS Interconnect Scaling on RF
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
0
10
20
30
0
500
1000
1500
.13 um 90 nm 65 nm 45 nm 32 nm
Ind
uct
or
Q (
pe
ak
)
Top
In
terc
on
ne
ct P
itch
(n
m)
Technology Node
Thick Metal
inductors by top metal layers (excluding Thick Metal)
25
CMOS Interconnect Scaling on RF with TM
Spiral Inductors by TM recover and improve the quality factor to achieve Q~25
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
32 nm High Q RF Spiral Inductor Family
0
10
20
30
0 5 10 15
Q (
Qu
ality
Fa
cto
r)
Inductance (nH)
Literature
This work
Single End Inductor
DifferentialInductor
Transformer/Spliter
Power Combiner
Balun
Complex high Q monolithic silicon spiral inductors were developed using TM for 32 nm RF designs, including PA, LNA, and VCO
26
C.-H. Jan, Dec/10 IEDM ’10, San Francisco
Conclusions
Moore’s Law alive and well for RF CMOS, enabled by the
innovations in transistors architectures and interconnects
Continuous improvement in CMOS gm and Cox keys to the
RF CMOS cut-off frequency and noise performance scaling
RF passives scaling needs creative solutions in
interconnect architectures scaling
32 nm wireless transceiver demonstrated with state of
the art 32 nm RF CMOS technology
27
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