george mason university ece 448 – fpga and asic design with vhdl simple testbenches behavioral...

George Mason UniversityECE 448 – FPGA and ASIC Design with VHDL

Simple Testbenches

Behavioral Modeling of Combinational Logic

ECE 448Lecture 4

2ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design

Chapter 6.6, VHDL for Combinational Circuits

• P. Chu, FPGA Prototyping by VHDL Examples

Section 1.4, Testbench

Section 3.4, Modeling with a process

Section 3.5, Routing circuit with if and case

statements

3ECE 448 – FPGA and ASIC Design with VHDL

Testbenches

4ECE 448 – FPGA and ASIC Design with VHDL

Testbench Defined

• Testbench = VHDL entity that applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs.

• The results can be viewed in a waveform window or written to a file.

• Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability).

• The same Testbench can be easily adapted to test different implementations (i.e. different architectures) of the same design.

5ECE 448 – FPGA and ASIC Design with VHDL

Simple Testbench

Processes

Generating

Stimuli

Design Under Test (DUT)

Observed Outputs

6ECE 448 – FPGA and ASIC Design with VHDL

Representative

Inputs

VHDL Design

Manual Calculations

or

Reference Software

Implementation(C, Java, Matlab )

expected results

Testbench

actual results= ?

Possible sources of expected results used for comparison

7ECE 448 – FPGA and ASIC Design with VHDL

Testbench

testbench

design entity

Architecture 1 Architecture 2 Architecture N. . . .

The same testbench can be used to test multiple implementations of the same circuit

(multiple architectures)

8ECE 448 – FPGA and ASIC Design with VHDL

Testbench Anatomy

ENTITY my_entity_tb IS --TB entity has no ports

END my_entity_tb;

ARCHITECTURE behavioral OF tb IS

--Local signals and constants

COMPONENT TestComp --All Design Under Test component declarations PORT ( ); END COMPONENT;-----------------------------------------------------BEGIN DUT:TestComp PORT MAP( -- Instantiations of DUTs ); testSequence: PROCESS -- Input stimuli END PROCESS;

END behavioral;

9ECE 448 – FPGA and ASIC Design with VHDL

Testbench for XOR3 (1)

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY xor3_tb ISEND xor3_tb;

ARCHITECTURE behavioral OF xor3_tb IS-- Component declaration of the tested unitCOMPONENT xor3PORT(A : IN STD_LOGIC;B : IN STD_LOGIC;C : IN STD_LOGIC;Result : OUT STD_LOGIC );

END COMPONENT;

-- Stimulus signals - signals mapped to the input and inout ports of tested entitySIGNAL test_vector: STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL test_result : STD_LOGIC;

10ECE 448 – FPGA and ASIC Design with VHDL

Testbench for XOR3 (2)

BEGINUUT : xor3

PORT MAP (A => test_vector(2),B => test_vector(1),C => test_vector(0),Result => test_result);

); Testing: PROCESS BEGIN test_vector <= "000";

WAIT FOR 10 ns; test_vector <= "001"; WAIT FOR 10 ns; test_vector <= "010"; WAIT FOR 10 ns;

test_vector <= "011"; WAIT FOR 10 ns; test_vector <= "100"; WAIT FOR 10 ns; test_vector <= "101"; WAIT FOR 10 ns; test_vector <= "110"; WAIT FOR 10 ns; test_vector <= "111";

WAIT FOR 10 ns; END PROCESS;END behavioral;

11ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral

• Testbenches

Sequential statements

12ECE 448 – FPGA and ASIC Design with VHDL

Process without Sensitivity List

and its use in Testbenches

13ECE 448 – FPGA and ASIC Design with VHDL

• A process can be given a unique name using an optional LABEL

• This is followed by the keyword PROCESS

• The keyword BEGIN is used to indicate the start of the process

• All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important.

• A process must end with the keywords END PROCESS.

Testing: PROCESS BEGIN

test_vector<=“00”;WAIT FOR 10 ns;

test_vector<=“01”;WAIT FOR 10 ns;

test_vector<=“10”;WAIT FOR 10 ns;

test_vector<=“11”;WAIT FOR 10 ns;

END PROCESS;

• A process is a sequence of instructions referred to as sequential statements.

What is a PROCESS?

The keyword PROCESS

14ECE 448 – FPGA and ASIC Design with VHDL

Execution of statements in a PROCESS

• The execution of statements continues sequentially till the last statement in the process.

• After execution of the last statement, the control is again passed to the beginning of the process.

Testing: PROCESS BEGIN

test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT FOR 10 ns;

END PROCESS;O

rde

r o

f exe

cutio

n

Program control is passed to the first statement after BEGIN

15ECE 448 – FPGA and ASIC Design with VHDL

PROCESS with a WAIT Statement

• The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns.

• This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed.

• This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated.

Testing: PROCESSBEGIN

test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT;

END PROCESS;

Program execution stops here

Ord

er

of e

xecu

tion

16ECE 448 – FPGA and ASIC Design with VHDL

WAIT FOR vs. WAIT

WAIT FOR: waveform will keep repeating itself forever

WAIT : waveform will keep its state after the last wait instruction.

0 1 2 3

…

0 1 2 3 …

17ECE 448 – FPGA and ASIC Design with VHDL

Specifying time in VHDL

18ECE 448 – FPGA and ASIC Design with VHDL

Time values (physical literals) - Examples

7 ns

1 min

min

10.65 us

10.65 fs

Unit of time Space

(required)

Numeric value

unit of time

most commonly

used in simulation

19ECE 448 – FPGA and ASIC Design with VHDL

Units of time

Unit Definition

Base Unit

fs femtoseconds (10-15 seconds)

Derived Units

ps picoseconds (10-12 seconds)

ns nanoseconds (10-9 seconds)

us microseconds (10-6 seconds)

ms miliseconds (10-3 seconds)

sec seconds

min minutes (60 seconds)

hr hours (3600 seconds)

20ECE 448 – FPGA and ASIC Design with VHDL

Simple Testbenches

21ECE 448 – FPGA and ASIC Design with VHDL

Generating selected values of one input

SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);

BEGIN

.......testing: PROCESS

BEGIN

test_vector <= "000";

WAIT FOR 10 ns;

test_vector <= "001";

WAIT FOR 10 ns;

test_vector <= "010";

WAIT FOR 10 ns;

test_vector <= "011";

WAIT FOR 10 ns;

test_vector <= "100";

WAIT FOR 10 ns;

END PROCESS;

........

END behavioral;

22ECE 448 – FPGA and ASIC Design with VHDL

Generating all values of one input

SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000";

BEGIN

.......

testing: PROCESS

BEGIN

WAIT FOR 10 ns;

test_vector <= test_vector + 1;

end process TESTING;

........

END behavioral;

23ECE 448 – FPGA and ASIC Design with VHDL

Arithmetic Operators in VHDL (1)

To use basic arithmetic operations involving std_logic_vectors you need to include thefollowing library packages:

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;orUSE ieee.std_logic_signed.all;

24ECE 448 – FPGA and ASIC Design with VHDL

Arithmetic Operators in VHDL (2)

You can use standard +, - operatorsto perform addition and subtraction:

signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0);

…… C <= A + B;

25ECE 448 – FPGA and ASIC Design with VHDL

Different ways of performing the same operation

signal count: std_logic_vector(7 downto 0);

You can use:

count <= count + “00000001”;

or

count <= count + 1;

or

count <= count + ‘1’;

26ECE 448 – FPGA and ASIC Design with VHDL

Different declarations for the same operator

Declarations in the package ieee.std_logic_unsigned:

function “+” ( L: std_logic_vector; R:std_logic_vector)

return std_logic_vector;

function “+” ( L: std_logic_vector; R: integer)

return std_logic_vector;

function “+” ( L: std_logic_vector; R:std_logic)

return std_logic_vector;

27ECE 448 – FPGA and ASIC Design with VHDL

Operator overloading

• Operator overloading allows different argument types for a given operation (function)

• The VHDL tools resolve which of these functions to select based on the types of the inputs

• This selection is transparent to the user as long as the function has been defined for the given argument types.

28ECE 448 – FPGA and ASIC Design with VHDL

SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0);

SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0);

BEGIN

.......

double_loop: PROCESSBEGIN

test_ab <="00";test_sel <="00";for I in 0 to 3 loop for J in 0 to 3 loop

wait for 10 ns;test_ab <= test_ab + 1;

end loop; test_sel <= test_sel + 1;end loop;

END PROCESS;

........

END behavioral;

Generating all possible values of two inputs

29ECE 448 – FPGA and ASIC Design with VHDL

Generating periodical signals, such as clocks

CONSTANT clk1_period : TIME := 20 ns;

CONSTANT clk2_period : TIME := 200 ns;

SIGNAL clk1 : STD_LOGIC;

SIGNAL clk2 : STD_LOGIC := ‘0’;

BEGIN

.......

clk1_generator: PROCESS

clk1 <= ‘0’;

WAIT FOR clk1_period/2;

clk1 <= ‘1’;

WAIT FOR clk1_period/2;

END PROCESS;

clk2 <= not clk2 after clk2_period/2;

.......

END behavioral;

30ECE 448 – FPGA and ASIC Design with VHDL

Generating one-time signals, such as resets

CONSTANT reset1_width : TIME := 100 ns;

CONSTANT reset2_width : TIME := 150 ns;

SIGNAL reset1 : STD_LOGIC;

SIGNAL reset2 : STD_LOGIC := ‘1’;

BEGIN

.......

reset1_generator: PROCESS

reset1 <= ‘1’;

WAIT FOR reset_width;

reset1 <= ‘0’;

WAIT;

END PROCESS;

reset2_generator: PROCESS

WAIT FOR reset_width;

reset2 <= ‘0’;

WAIT;

END PROCESS;

.......

END behavioral;

31ECE 448 – FPGA and ASIC Design with VHDL

Typical error

SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);

SIGNAL reset : STD_LOGIC;

BEGIN

.......

generator1: PROCESS

reset <= ‘1’;

WAIT FOR 100 ns

reset <= ‘0’;

test_vector <="000";

WAIT;

END PROCESS;

generator2: PROCESS

WAIT FOR 200 ns

test_vector <="001";

WAIT FOR 600 ns

test_vector <="011";

END PROCESS;

.......

END behavioral;

32ECE 448 – FPGA and ASIC Design with VHDL

Combinational Logic Synthesis

for

Beginners

33ECE 448 – FPGA and ASIC Design with VHDL

• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)

Simple rules for beginners

For combinational logic,

use only concurrent statements

34ECE 448 – FPGA and ASIC Design with VHDL

• concurrent signal assignment ()

Simple rules for beginners

For circuits composed of

- simple logic operations (logic gates)

- simple arithmetic operations (addition,

subtraction, multiplication)

- shifts/rotations by a constant

use

35ECE 448 – FPGA and ASIC Design with VHDL

Simple rules for beginners

For circuits composed of

- multiplexers

- decoders, encoders

- tri-state buffers

use

• conditional concurrent signal assignment

(when-else)• selected concurrent signal assignment

(with-select-when)

36ECE 448 – FPGA and ASIC Design with VHDL

Combinational Logic Synthesis

for

Intermediates

37ECE 448 – FPGA and ASIC Design with VHDL

PROCESS with a SENSITIVITY LIST

• List of signals to which the process is sensitive.

• Whenever there is an event on any of the signals in the sensitivity list, the process fires.

• Every time the process fires, it will run in its entirety.

• WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.

label: process (sensitivity list) declaration part begin

statement part end process;

38ECE 448 – FPGA and ASIC Design with VHDL

Anatomy of a Process

[label:] PROCESS [(sensitivity list)] [declaration part]BEGIN statement partEND PROCESS [label];

OPTIONAL

39ECE 448 – FPGA and ASIC Design with VHDL

Processes in VHDL

• Processes Describe Sequential Behavior

• Processes in VHDL Are Very Powerful Statements• Allow to define an arbitrary behavior that may

be difficult to represent by a real circuit• Not every process can be synthesized

• Use Processes with Caution in the Code to Be Synthesized

• Use Processes Freely in Testbenches

40ECE 448 – FPGA and ASIC Design with VHDL

Describing combinational logic using processes

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY dec2to4 IS

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 ISBEGIN

PROCESS ( w, En )BEGIN

IF En = '1' THENCASE w IS

WHEN "00" => y <= "1000" ;WHEN "01" => y <= "0100" ;WHEN "10" => y <= "0010" ;WHEN OTHERS => y <= "0001" ;

END CASE ;ELSE

y <= "0000" ;END IF ;

END PROCESS ;END Behavior ;

41ECE 448 – FPGA and ASIC Design with VHDL

Describing combinational logic using processes

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY seg7 IS

PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;

END seg7 ;ARCHITECTURE Behavior OF seg7 ISBEGIN

PROCESS ( bcd )BEGIN

CASE bcd IS -- abcdefgWHEN "0000" => leds <= "1111110" ;WHEN "0001" => leds <= "0110000" ;WHEN "0010" => leds <= "1101101" ;WHEN "0011" => leds <= "1111001" ;WHEN "0100" => leds <= "0110011" ;WHEN "0101" => leds <= "1011011" ;WHEN "0110" => leds <= "1011111" ;WHEN "0111" => leds <= "1110000" ;WHEN "1000" => leds <= "1111111" ;WHEN "1001" => leds <= "1110011" ;WHEN OTHERS => leds <= "-------" ;

END CASE ;END PROCESS ;

END Behavior ;

42ECE 448 – FPGA and ASIC Design with VHDL

Describing combinational logic using processes

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY compare1 ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END compare1 ;

ARCHITECTURE Behavior OF compare1 ISBEGIN

PROCESS ( A, B )BEGIN

AeqB <= '0' ;IF A = B THEN

AeqB <= '1' ;END IF ;

END PROCESS ;END Behavior ;

43ECE 448 – FPGA and ASIC Design with VHDL

Incorrect code for combinational logic- Implied latch (1)

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY implied ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END implied ;

ARCHITECTURE Behavior OF implied ISBEGIN

PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;

END IF ;END PROCESS ;

END Behavior ;

44ECE 448 – FPGA and ASIC Design with VHDL

Incorrect code for combinational logic- Implied latch (2)

A B AeqB

45ECE 448 – FPGA and ASIC Design with VHDL

Describing combinational logic using processes

Rules that need to be followed:

1. All inputs to the combinational circuit should be included

in the sensitivity list

2. No other signals should be included

in the sensitivity list

3. None of the statements within the process

should be sensitive to rising or falling edges

4. All possible cases need to be covered in the internal

IF and CASE statements in order to avoid

implied latches

46ECE 448 – FPGA and ASIC Design with VHDL

Covering all cases in the IF statement

Using ELSE

Using default values

AeqB <= '0' ;

IF A = B THEN

AeqB <= '1' ;

IF A = B THEN

AeqB <= '1' ;

ELSE

AeqB <= '0' ;

47ECE 448 – FPGA and ASIC Design with VHDL

Covering all cases in the CASE statement

Using WHEN OTHERS

CASE y IS

WHEN S1 => Z <= "10";

WHEN S2 => Z <= "01";

WHEN OTHERS => Z <= "00";

END CASE;

CASE y IS

WHEN S1 => Z <= "10";

WHEN S2 => Z <= "01";

WHEN S3 => Z <= "00";

WHEN OTHERS => Z <= „--";

END CASE;

48ECE 448 – FPGA and ASIC Design with VHDL

Covering all cases in the CASE statement

Using default values

Z <= "00";

CASE y IS

WHEN S1 => Z <= "10";

WHEN S2 => Z <= “01";

END CASE;

Z <= "00";

CASE y IS

WHEN S1 => Z <= "10";

WHEN S2 => Z <= “01";

when others =>

null;

END CASE;

49ECE 448 – FPGA and ASIC Design with VHDL

Decoders described using

behavioral description

50ECE 448 – FPGA and ASIC Design with VHDL

Decode Table

Instruction Active output signals

(15 downto 0) (asserted with 1)

8xxx Op1

3xx4 Op2

3xx6 Op3

x – stands for don’t care

51ECE 448 – FPGA and ASIC Design with VHDL

Instruction Decoder (main process)

decode: process (Instruction)

begin

Op1 <= ‘0';

Op2 <= ‘0';

Op3 <= ‘0';

case Instruction(15 downto 12) is

when X"8" =>

Op1 <= ‘1';

when X"3" =>

case Instruction (3 downto 0) is

when X"4" =>

Op2 <= '1';

when X"6" =>

Op3 <= '1';

when others =>

null;

end case;

when others =>

null;

end case;

end process decode;

Optional.

Added for increased

readability.