fundamentals of clocks and frequency synthesis filefive types of clocking chips analog plls uses an...
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DAVID KRESS
Director of Technical Marketing
Fundamentals of Clocks and
Frequency Synthesis
03/23/2017
Today’s Agenda
► Applications areas for clocks and frequency synthesis
► Design and application of phase-locked loops (PLLs)
► Design and application of direct digital synthesis (DDS)
► Issues of clocking data converters
► Clock generation and distribution
2
Five types of clocking chips
► Analog PLLs Uses an analog multiplier as the phase detector
Not in Wide Use
► Digital PLLs Use a digital phase frequency detector (PFD), analog loop filter, voltage controlled oscillator (VCO)
Simple architecture
Very high performance and low noise
► All-Digital PLLs Use a digital phase frequency detector (PFD), digital loop filter, NCO
Excellent jitter cleaning
Extremely flexible
► Direct Digital Synthesis Extremely flexible frequency generation
Very fast frequency sweeping and hopping
Very popular in military and instrumentation applications
► General oscillators Crystal oscillators
Voltage-controlled oscillators (VCO)
3
What is a clock and what are the common frequencies?
► Unlike a data waveform, a clock signal is a square wave whose frequency is usually constant.
► Common frequencies include:
1 pps (pulse per second) used by GPS
8 kHz (commonly used in wired communcations) and is commonly referred to as a BITS clock
19.44 MHz is a common reference clock in synchronous optical (SONET) networks, and is still used in OTU
(Optical Transport Unit) networks that are replacing SONET
122.88/245.75/491.52… MHz are commonly used in wireless communications
125 and 156.25 MHz are common Ethernet reference clocks
32.768 kHz is the common watch crystal oscillator
4
PLL vs. DDS block diagrams
Phase/F
DetectorR
Charge
Pump VCOLoop
Filter
NPLL
REFIN
Digital Enginep bits of resolution
Reference Clock signal: Frequency = FSAM
‘Reconstruction’
FilterDAC
FOUT = FSAM x (FTW/2p)Basic DDS frequency equation:
FOUT = REFIN x (N/R)Basic PLL frequency equation:
5
Basic Phase Locked Loop (PLL) Model
(B) STANDARD NEGATIVE FEEDBACK
CONTROL SYSTEM MODEL
(A) PLL MODEL
ERROR DETECTOR LOOP FILTER VCO
FEEDBACK DIVIDERPHASE
DETECTOR
CHARGE
PUMP FO = N FREF
6
/2REFA /R1
Phase
Freq
Det
(PFD)
32 MHz< FPFD <44 MHz
Charge
Pump
Loop Filter
(External)
VCO
/4 or 5/B
OUT
Feedback Divider
(N Divider)
/P/2 /R2
Reference
Monitor and
control Logic
REFB
REF
FLAG
VCO
div
Digital PLL Block Diagram
7
Phase/Frequency Detector (PFD)
Driving a Charge Pump (CP)
D1 Q1
CLR1
CLR2D2 Q2
V+
V−
HI
HI
+IN
−IN
DELAY
UP
DOWN
CP OUT
I
I
U1
U2
U3
PFD
CP
D1 Q1
CLR1
CLR2D2 Q2
V+
V−
HI
HI
+IN
−IN
DELAY
UP
DOWN
CP OUT
I
I
U1
U2
U3
PFD
CP
(A) OUT OF FREQUENCY LOCK AND PHASE LOCK
(B) IN FREQUENCY LOCK, BUT
SLIGHTLY OUT OF PHASE LOCK
0
+I
+I
0
(A) OUT OF FREQUENCY LOCK AND PHASE LOCK
(B) IN FREQUENCY LOCK, BUT
SLIGHTLY OUT OF PHASE LOCK
0
+I
+I
0
UP
1
0
0
DOWN
0
1
0
CP OUT
+ I
−I
0
UP
1
0
0
DOWN
0
1
0
CP OUT
+ I
−I
0 (C) IN FREQUENCY LOCK AND PHASE LOCK
8
Adding an Input Reference Divider
and a Prescaler to the Basic PLL
(A)
(B)
REFERENCE
DIVIDER
R
REFERENCE
DIVIDER
R
PRESCALER
P
9
All-Digital PLL Detailed Block Diagram
(AD9557 Shown)
SPI/I2CSERIAL PORT
EEPROM
REF MONITORINGAUTOMATICSWITCHING
÷N1 ÷N2
÷N3
÷2 ÷M0OUT0
OUT0
OUT1
OUT1
10-BITINTEGERDIVIDERS
MAX 1.25GHz
÷M1
×2
×2
LF
PFD/CP
RF DIVIDER 1÷3 TO ÷11
XO OR XTAL XO FREQUENCIES10MHz TO 180MHz
XTAL: 10MHz TO 50MHz
RF DIVIDER 2÷3 TO ÷11
FOUT = 360kHz TO 1.25GHz
INTEGER DIVIDER
OUTPUT PLL (APLL)
FRAC1/MOD1
17-BITINTEGER
24b/24bRESOLUTION DIGITAL PLL (DPLL)
÷2
REGISTERSPACE
2kH
zT
O1.2
5G
Hz
R DIVIDER (20-BIT)
SYNC RESET PINCONTROL M0 M1 M2 M3 IRQ
SPI/I2C
DIGITALLOOP
FILTER
TUNINGWORD
CLAMP ANDHISTORY
FREERUNTW
PLL2STATUS
LF CAP
PFD/CP LF
3.34GHzTO
4.05GHz
DP
FD
30-B
ITN
CO
ROMANDFSM
MULTI-FUNCTION I/O PINS(CONTROL AND STATUS
READ BACK)
SYSTEMCLOCK
MULTIPLIER
÷2
AD9557
REFA
REFA
REFB
REFB
09
19
7-1
35
Digital PLL Core
Analog
PLL
10
Key PLL Specifications
► Input Frequency (Minimum/Maximum)
► Loop Bandwidth and Phase Margin
► Frequency Lock Time
► Phase Lock Time
► Output Frequency Error
► Output Phase Error
► Phase Noise and Phase Jitter
► Reference Spurs
11
Integer-N Compared to
Fractional-N Synthesizer
REF
DIVIDER
R
PFD FILTER VCO
N COUNTER
FREF
F1
FOUT
10MHz
R =50
0.2MHz
N = 4501
900.2MHz
REF
DIVIDER
R
PFD FILTER VCO
"N" COUNTER
FREF
F1
FOUT
10MHz
R =10
1MHz
900.2MHz
N =900.2
"N" = NINTEGER + NFRACTION
NMODULUS= 900 +
NFRACTION
5
FOUT = FREF(N/R)
(A) INTEGER N
(B) FRACTIONAL N
12
Common Uses for PLLs
► Frequency translation
► Jitter Cleanup
► Redundant clocking
► Holdover
► Clock Distribution
13
/2
REFA
19.44
MHz
/R1
Phase
Freq
Det
(PFD)
10 kHz< FPFD < 50MHz
Charge
Pump
Loop Filter
(External)
VCO
/4 or 5/B
156.25
MHz
Feedback Divider
(N Divider)
/P/2 /R2
Reference
Monitor and
control Logic
REFB
REF
FLAG
VCO
div
Frequency Translation Example:
► 19.44 MHz (SONET) to 156.25 MHz (10 Gb/s Ethernet):
R divider=162, B=15625, VCO divider = 3, P divider = 4
Phase detector frequency: 120 kHz
VCO frequency: 1875 MHz
14
Jitter Clean-up
Clean signal from main
clock board
Backplane
has lots of
noise
sources Clock received by line
card is contaminated
Clock received from back plane is
used to establish phase and
frequency of the output
Signal purity of the output is
dependent upon the Local
oscillator (Crystal, TCXO, or
OCXO) used HOW?
Digital PLL w/ a
Programmable
Digital loop
Filter capable of
<1 Hz BW
15
Switchover and Holdover
Holdover:
Holdover is the ability to provide output signals even when the reference input disappears. Holdover can be initiated either
as directed by controller/processor elements in a system, or via a provided monitoring function which will automatically
switch into holdover mode when the reference input goes quiet.
Switchover:
Switchover provides additional security beyond the holdover function. If one of the references fails, the clock device will use
one of the alternate references instead. An important aspect of all the switchover functions provided in ADI clock devices is
that no runt pulses and no extra long pulses result from this change. Downstream PLLs will not lose lock as a result, of or
during, switchover - even when no predefined relationship exists between the phases of the various reference input signals.
Switchover can be initiated either as directed by controller/processor elements in a system, or via a provided monitoring
function which will automatically implement switchover when the active reference input goes quiet.
16
Switchover, Synchronization, and Holdover
NOTE
output is synchronized to primary
referenceBut what happens when the
primary reference disappears?
The PLL will maintain the output clock in holdover until another
reference input is available. The output phase may or may not slew
(depending on the application) so that either the input-output phase
is the maintained or there is no output clock phase slewing.
AD9548
17
TOOLS – Design, Simulation, Evaluation
► ADIsimCLK
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and
clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband,
ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate
and optimize your design.
► ADIsimPLL
The ADIsimPLL design tool is a comprehensive and easy-to-use PLL synthesizer design and simulation tool. All key non-
linear effects that can impact PLL performance can be simulated, including phase noise, Fractional-N spurs, and anti-
backlash pulse. This tool eliminates time-consuming iterations from the PLL/synthesizer development process.
► ADIsimDDS (Direct Digital Synthesis)
ADIsimDDS uses mathematical equations to model and illustrate the overall performance of the selected device. This tool
calculates the required FTW, given the reference clock frequency and desired output frequency.
18
PLL Design Software
VERSION 4.2
www.analog.com/adisimpll19
Set up Configuration and Frequency Requirements
20
Choose and configure the chip and loop filter
21
A detailed design report is provided
22
Frequency Domain Performance Report
23
Completely Configured Schematic for ADF4158
24
Applications for
Phase-locked Loops (PLLs)
26
Clock Distribution Example
Delay 1-10ns
1:5 Fanout
Buffer
Divide by 1-32LVPECL to
CMOS
LVPECL to
LVDS
225 fs RMS
225 fs RMS
350 fs RMS
1-3 ps RMS
A
RMS Jitter added
to signal at AExample: AD9512
225 fs RMS
Divide by 1-32
Divide by 1-32
Divide by 1-32
Divide by 1-32LVPECL
Buffer
LVPECL
Buffer
LVPECL
Buffer
26
AD9516 Family 1.5 -3.0 GHz, 8/5-Channel Clock Distribution ICs
Clock Outputs
1.2 GHz LVPECL
800 MHz LVDS
250 MHz CMOS
PLL Core
250 MHz REFIN
1.6 GHz PLL
Jitter Clean-up
Programmable Dividers
Any integer 1 to 32
Phase offset control
Each divider independent
Programmable Delay Adjust
Fullscale from 1ns to 10ns
32 delay steps
64-LFCSP
typically replaces
Five(5) discrete ICs
AD9510 Shown Below, Broadband RMS Jitter <1ps
27
Application – Wireless Transceiver Card
ADC
ADC
ADC
ADC
DDC or
ASIC
DAC
DUC or
FPGA
DAC
User’s
Reference
Clock
Clock to A-D Converters
Clock to D-A Converters
Clock to
Digital Chips
Critical Clock Functions on Transceiver Card:
• clean-up jitter on user’s input reference
• up-convert user reference frequency to highest frequency
needed, usually driven by DAC clock requirements
• generate multiple frequencies for RX & TX
• provide low jitter clocks for converters
• generate mix of LVPECL, LVDS, CMOS clocks
• adjust phase or delay between clock channels
• offer isolation between clock channels
TRX CardsTRX
Clock Distribution IC
28
Digital
Cross
Point
Clock
Generation/
Distribution
Power
Sequencing
Line Card
Switch Card
XCVRCDR
SERDES
Backplane
Switch
& EQ
Digital
Engine
Optical Transceiver
TIA
LDD
PIN
Laser
Limiting
AMP
Signal
Conditioner
Application – Line Card
Switch Card
Line Card
Backplane
New ADI clock products such
as the AD9557 and AD9548 are
tailored for network
applications.
Specific AD9548 example on
next page
29
SyncE / IEEE1588 Hybrid
(with Hooks for Pure IEEE1588)
Ba
ck
pla
ne
Line Card
AD9557
AD9547
TCXO /
OCXO Recovered clocks
from Line cards
BITS
GPS
Timing Card
XO AD9553/7(Optional)
Tx
Rx
CPU / FPGA / DSPIEEE1588
Protocol / Algorithm
SP
I / I 2C
MAC/PHY
SyncE Clock Recovering
+
IEEE1588 Time Stamp
Time Stamps
Frequency
Synchronization
1 PPS
Timing Card 2Line Card n
Time of Day Offset Adjustment
1 PPS
Time of Day
Clock/Frequency Control
AD9548
30
Generating Clocks using DDS
Limiter
Reconstruction
Filter
Fsysclock(fc) DAC out Filter out
Clock out
Ideal Time
Domain
Response
Ideal
Frequency
Domain
Response
"Real World"
Frequency
Response
t
0
1 1 3 5 7
Odd harmonic series
1 3 5 7
t t
f ff
ffffc
fc 2fc
2fc
DDS
The DDS chip can synchronize to a user’s reference. An on-chip clock multiplier can generate the fast clock needed to clock the NCO/DAC. A frequency tuning word may be written to set the output clock rate.
External filtering removes unwanted images. A squaring function then converts sine wave to square wave.32
Basic DDS System – p-bit DDS with N-bit DAC
1
fOut
p-bit Phase
Register
“M”
p-bit
phase
resolution
(p=6)
01
23
4
63
024
3129…
…
N-bit
amplitude
resolution
(N=5)
raw DDS-DAC output
M = round(2p
• )fOut
fClk
p-bit Phase
Accumulator
θ(t ) = 2π• • INTM
2p (t·fClk)
p N + 2~4
θM
θ(t )
Phase →
Amplitude
Conversion
Clock
N-bit
DAC
N
sin(θ)
Clocking
Comparator
To HSC
Clock
filtered outputcompared output
vector data
To Mixer,
Mod/Demod,
etc.
1
fClk
6~8 Order
OR
33
Signal Flow Through the DDS Architecture
REFERENCE
CLOCK
PHASE
ACCUMULATOR
(n-BITS)
PHASE-TO-AMPLITUDE
CONVERTERDAC
M
TUNING WORD SPECIFIES
OUTPUT FREQUENCY AS A
FRACTION OF REFERENCE
CLOCK FREQUENCY
IN DIGITAL DOMAIN ANALOG
N
DDS CIRCUITRY (NCO)TO
FILTER
2n=fo
M • fc
2n=fo
M • fc
fc
2n=fo
M • fc
M = JUMP SIZE
34
AD9858 1GSPS DDS with Phase Detector and Analog Multiplier
35
AD9914 3.5 GSPS DDS with 12-bit DAC
36
DDS Single Loop Upconversion
Using the AD9858
DDS
1GHzDAC
1032
LPFDIVIDER
1/2/4
PHASE/
FREQUENCY
DETECTOR
150MHz
CHARGE PUMP
0.5mA-2mA
0.5mA STEPS
LOOP
FILTER ~
DIVIDER
K
DC - 400MHz
VCO
f = K fREF
DDS/DAC
CLOCK
FREQUENCY
TUNING WORD
PART OF
AD9858:
fREFDC - 150MHz
37
DDS On-Line Interactive Design Tool (ADIsimDDS)
38
ADIsimDDS Design Tool Main Screen
39
DDS Design Tool: Tabular Display of Spurs
40
DDS Forum in EngineerZone
Get fast
answers to
new
questions
Search existing
content for
immediate
answers
41
Direct Digital Synthesis Portfolio/Roadmap
42
Availability
Released
100M 1G
DA
C R
eso
luti
on
(B
its
)
Max Sample Rate (samples/sec)
12
10
<50
50 to 55
>55
14
–43 dBc
AD9851
–54 dBc
AD9850
10G
SFDR @ 40% of sample rate
–48 dBc
AD9852/AD9854
–62 dBc
AD9858–50 dBc
AD9849
–52 dBcAD9951/AD9952/
AD9953/AD9954
–55 dBc
AD9956
–53 dBc
AD9911
–53 dBc
AD9958/AD9959
–58 dBc
AD9912
–53 dBc
AD9910
–58 dBc
AD9913
–60 dBc
AD9915
–52 dBc
AD9914
–55 dBc
AD9832
–49 dBc
AD9835
–45 dBc
AD9830
–50 dBc
AD9831
10M
–64 dBc
AD9833
–48 dBc
AD9834
–65 dBc
AD916416
DDS Advantages
► Frequency resolution as fine as µHertz
► 0.022 degree phase offset resolution over 360 degree range
► Very fast frequency transitions…<5 ns to change from one
frequency to another
► All digital control = no manual system “tweaking”
► Easily synchronized allowing quadrature and other exact
signal phase relationships to be obtained
► Unparalleled matching of I & Q outputs
► Highly accurate , high speed PSK and FSK
43
PLL Advantages
► Very Low Phase Noise and Jitter
► Very High Frequency Capability (13GHz)
► Low Spurious Content
► Versatile: Trade Off Phase Noise/Spurs versus Settling Time
► Low Power Consumption
44
DDS vs. PLL
Comparing: Advantage The rest of the story
Freq. Resolution DDS Fractional N PLLs shrink the gap, Programmable Modulus
improves DDS precision
Freq. Agility DDS Fast hopping PLLs shrink the gap
Phase Resolution &
AgilityDDS Digital PLLs can provide some level of phase control.
Amplitude Resolution
& AgilityDDS
Power Consumption PLL Gap shrinks with geometry; interleaved cores
Price PLL* Gap shrinks with geometry; in no small part this is due to
the breadth of adoption of PLL technology,
Broad Spectral Purity PLL
Ancillary circuitry PLL
Freq. Up-conversion PLL Super Nyquist operation and hybrids
45
Hybrid configurations
DDSRefCLK PLL Up converting PLL
DDSRefCLK PLL RefCLK multiplying PLL
PLL
DDSRefCLK DDS in feedback path
PLL
DDSRefCLK DDS as a DCO
46
Clocking Data Converters
Effective Aperture Delay Time Measured with Respect to ADC Input
SAMPLING
CLOCK
ANALOG INPUT
SINEWAVE
ZERO CROSSING
+FS
-FS
0V
+te–te
te
' '
'
47
Absolute accuracy needed for reproduction
CD sound output would be off-tune
Clock jitter leads to distortion
Jitter – common noise source introduced at SHA in A-D Converter
► Clock jitter is the sample to sample variation in the encode clock (both the external jitter as well as the
internal jitter).
► Fullscale SNR is jitter-limited by:
► See AN-501 and AN-756
SHA = Sample & Hold Amplifier
SNR = Signal to Noise Ratio
jitterrms
rmsjitter
ftN
SSNR
2
1log20log20
Jump to Products
48
45.0
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
100 1000
50 fs
100 fs
200 fs
400 fs
800 fs
Fullscale Analog Input (sinewave)
84dB
78dB
AIN = 200 MHz
Each line shows
constant RMS
clock jitter in
femtoseconds (fs)
72dB
66dB
60dB
300
MHz
400
MHz
500
MHz
SNR of ADC @ 200 MHz
AIN varies with clock jitter
Sig
nal to
Nois
e R
atio (
SN
R)
in d
B
ADC
Analog
Input
Sampling Clock
SNR
Digital
Output
As analog signal increases, clock jitter limits SNR
jitter
jitft
SNR2
1log20
49
Additive RMS Jitter of Logic Gates/Drivers
► FPGA (driver gates only) 33-50 ps**
► 74LS00 4.94 ps *
► 74HCT00 2.20 ps *
► 74ACT00 0.99 ps *
► MC100EL16 PECL 0.7 ps **
► AD951x family 0.22 ps **
► NBSG16, Reduced Swing ECL (0.4V) 0.2 ps **
► ADCLK9xx, ECL Clock Driver Family <0.1 ps**
* Calculated values based on degradation in ADC SNR
** Manufacturers' specification
50
By Architecture & Performance
Non
-PLL
PLL E
xt
VC
OP
LL Int
VC
O
Wideband RMS jitter
ADCLK944
ADCLK905
ADCLK907
ADCLK925
ADCLK946
ADCLK948
ADCLK950
ADCLK954
ADCLK914
ADCLK846
ADCLK854
AD9512
AD9514
AD9515
AD9513
AD9508
AD9510
AD9511
AD9516-5
AD9520-5
AD9522-5
AD9516-0:4
AD9517-0:4
AD9518-0:4
AD9520-0:4
AD9522-0:4
AD9523
AD9524
AD9525
50 fs 150 fs100 fs 200 fs 250 fs 300 fs
Additiv
e J
itter
Absolu
te
Jitte
r
AD9523-1
6810
12
6
6
8
10
12
12
8
14
14
12
12
10
5
5
6124
9
332
22
1 1
8
Indicates # of outputs
Front end loop of AD9523/4
Uses external Oscillator
Absolute jitter includes
oscillator performance and
reference quality
Additive jitter excludes
oscillator performance and
reference quality
ADF4351
ADF4360
ADF4002, ADF4106
Stand-Alone PLL
+ Ext VCXO
1 ps
AD9530
51
Voltage-controlled Oscillators
► Provide simplicity and versatility
► Simple RC-adjustable oscillators for undemanding applications
► Higher frequencies require specialized design
52
Voltage-controlled Oscillator
HMC512
53
LOOP
FILTER
VCXO
System Clock Distribution Examples
ADC FIFO
122.88 MHz122.88 MHz
LVPECL CMOS
DELAY = 4.3ns
HIGH SPEED MEASUREMENT SUBSYSTEM
REFCLK
491.52 MHz
LVPECL
30.72 MHz
DAC
DACFPGALVDS
CMOS
CMOS
QUADRATURE TRANSMIT SOURCE
61.44 MHz
61.44 MHz
PHASE = 90°
DELAY = 10ns
122.88MHz
LVPECL
491.52 MHz
CLEAN_REFCLK30.72 MHz
CALIBRATION
15.36 MHz
Clock ICs simplify board design
by integrating phase control,
delay adjust, frequency dividers,
and logic translationPHASE = 0°
TOYOCOM
491.52 MHz
AD9513/AD9514/AD9515 are easy to use. Require only a +3.3V supply. All functionality selected by tying input pins to VS, GND, VREF, or NC
54
ADI’s Complete Clock Portfolio
► Digital and All-Digital PLLs
Used for frequency multiplication/translation
Redundant Clocking and Holdover
► Synthesizers
Used for clock generation
► Clock Distribution
Used for sending the identical clock to multiple chips
Also used for logic level translation (i.e., LVPECL to LVDS)
May include frequency dividers (/2, /4, etc.)
May include skew adjustment
► Voltage-controlled oscillators
55
Discrete Phase Locked Loop (PLL) Product Roadmap
56
6 GHz
Availability
Released
Development
13 GHz 18 GHz 26 GHz 32 GHz
ADF4106/7/8
6/7/8 GHz Int-N PLL
Low power consumption
Simple but highly effective
-223 dBc/Hz FOM
ADF4159
13 GHz Frac-N PLL
Integrated sweep engine
25-bit modulus
110 MHz fPFD
Phase control
ADF41020
18 GHz Int-N PLL
-221 dBc/Hz FOM
ADF4106 with integrated
prescaler
ADF41513
26.5 GHz Frac-N PLL
-234 dBc/Hz FOM
200 MHz fPFD
Integrated sweep engine
Samples: now; Release July 2017
HMC703
8 GHz Frac-N
Integrated sweep engine
Very low spurs
-233 dBc/Hz FOM
ADF4153A
4 GHz Frac-N PLL
-223 dBc/Hz FOM
Extended temp: +125 °C
• High frequency operation
• Low VCO phase noise, PLL FOM,
and spurs for improved functionality
• Low power
• Extended temperature operations
• Variety of parts means there is an
optimum part for every application
ADF4158
6.1 GHz Frac-N PLL
25-bit modulus
Integrated sweep engine
-216 dBc/Hz FOM
ADF4193/ 6
3.5/6 GHz Frac-N PLL
-216 dBc/Hz FOM
Very fast switching (5 µs)
ADF4169
13.5 GHz Frac-N PLL
Higher frequency ADF4159: 130 MHz fPFD
ADF4002
400 MHz Int-N PLL
-222 dBc/Hz FOM
N divider ≥ 1
ADF4007
7 GHz Int-N PLL
-219 dBc/Hz FOM
All hardware programmable. No SPI
ADF4152HV
5 GHz Frac-N PLL
-213 dBc/Hz FOM
Up to 29 V charge pump
ADF4156
6.2 GHz Frac-N PLL
-220 dBc/Hz FOM
Simple fractional-N PLL
Phase control
ADF41512
18 GHz Frac-N PLL
-234 dBc/Hz FOM
200 MHz fPFD
Integrated sweep engine
Samples: now; Release April 2017
RF Integrated PLL/VCO Synthesizer Product Roadmap:
57
6 GHz 13 GHz 18 GHz 26 GHz 32 GHz
ADF4355
0.05 - 6.8 GHz PLL/VCO
5 V Operation
-138 dBc/Hz @ 1 MHz at 3.4
GHz
Dual output to 6.8 GHz
ADF4350
0.035 – 4.4 GHz PLL/VCO
Int-N and Frac-N operation
-134 dBc/Hz @ 1 MHz at 3.4 GHz
Medium-low power
ADF4356
0.05 - 6.8 GHz PLLVCO
Improved FOM, spurs
HMC832A
0.02 – 3 GHz PLL/VCO
All 3.3 V supplies
-139 dBc/Hz @ 1 MHz at 2
GHz
Low power
ADF4360-X
0.001 - 2.7 GHz PLL/VCO
Low power: <100 mW
Ten separate devices
Simple, int-N PLL/VCOs
ADF4355-3
0.05 - 6.8 GHz PLLVCO
3.3 V (low power)
-141 dBc/Hz @ 1 MHz at 3.4
GHz
Dual output to 6.8 GHz
• High and low frequency operation
• Best spurs for integrated PLL/VCO
• Best FOM for integrated PLL/VCO
• Best VCO phase noise
• Low power
• Variety of int-N and frac-N, and variety
of high and low power devices.
• Integrated VCO and wide band reduces
inventory, design work, software work
and more for customers.
• Variety of parts means there is an
optimum part for every application
HMC830
0.025 – 3 GHz PLL/VCO
5 V and 3.3 V operation
-141 dBc/Hz @ 1 MHz at 2 GHz
Very low spurs
ADF4351
0.035 – 4.4 GHz PLL/VCO
Improved ADF4350
Phase control
Availability
Released
Development
ADF4355-2
0.05 – 4.4 GHz
PLLVCO
5 V (low power)
-141 dBc/Hz @ 1 MHz at
3.4 GHz
Dual output to 4.4 GHz
HMC833
0.025 – 6 GHz PLL/VCO
5 V and 3.3 V operation
-141 dBc/Hz @ 1 MHz at 2 GHz
Very low spurs
Concept
Direct Digital Synthesis Portfolio/Roadmap
58
Availability
Released
100M 1G
DA
C R
eso
luti
on
(B
its
)
Max Sample Rate (samples/sec)
12
10
<50
50 to 55
>55
14
–43 dBc
AD9851
–54 dBc
AD9850
10G
SFDR @ 40% of sample rate
–48 dBc
AD9852/AD9854
–62 dBc
AD9858–50 dBc
AD9849
–52 dBcAD9951/AD9952/
AD9953/AD9954
–55 dBc
AD9956
–53 dBc
AD9911
–53 dBc
AD9958/AD9959
–58 dBc
AD9912
–53 dBc
AD9910
–58 dBc
AD9913
–60 dBc
AD9915
–52 dBc
AD9914
–55 dBc
AD9832
–49 dBc
AD9835
–45 dBc
AD9830
–50 dBc
AD9831
10M
–64 dBc
AD9833
–48 dBc
AD9834
–65 dBc
AD916416
What we covered
► As system complexity and performance demands increase, frequency synthesis devices have had
to keep pace with greater performance and versatility
► Design and application of phase-locked loops (PLLs)
► Design and application of direct digital synthesis (DDS)
► Software tools greatly simplify design and set-up of complex frequency synthesis devices
► Clocks for data converters need to have low jitter to keep distortion at a minimum
► Specialized clock generation and distribution allows precise frequency tuning and phase control
59
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