frequency limits of bipolar integrated circuits rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax...
Post on 20-Jan-2016
219 Views
Preview:
TRANSCRIPT
Frequency Limits of Bipolar Integrated Circuits
rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax
Mark Rodwell University of California, Santa Barbara
Collaborators
Z. Griffith, E. Lind, V. Paidi, N. Parthasarathy, U. SingisettiECE Dept., University of California, Santa Barbara
M. Urteaga, R. Pierson , P. Rowell, B. BrarRockwell Scientific Company
IEEE MTT-S Symposium, June 13, 2006
Sponsors
J. Zolper, S. Pappert, M. RoskerDARPA (TFAST, ABCS, SMART)
I. Mack, D. Purdy, Office of Naval Research
THz Transistors:What does this mean ?What are they for ?How do we make them ?
High-Resolution Microwave ADCs and DACs
What could we do with a THz Transistor ?
340 GHz imaging systems
mm-wave radio: 40+ Gb/s on 250 GHz carrier
320 Gb/s fiber optics
Why develop transistors for mm-wave & sub-mm-wave applications ? → compact ICs supporting complex high-frequency systems.
THz Transistors: What does this mean ?
A 1 THz current-gain cutoff frequency (f) alone has little valuea transistor with 1000 GHz f and 100 GHz fmax
cannot amplify a 101 GHz signal
RF-ICs & MIMICs need high power-gain cutoff frequency (fmax )also need high breakdown & high safe operating area (power density)
100+ GHz digital also needslow (Cdepletion V / I ) and low (I*Rparasitic /V )
So, how do we make a transistor with>1 THz f>1 THz fmax
<50 fs CV / I charging delays and < 100 mV (I*Rparasitic) parasitic voltage drops ?
THz Transistors:How do we make them ?
Present Status of Fast III-V Transistors
)(
),/(
),/(
),/(
hence ,
:digital
gain, associated ,F
:amplifiers noise low
mW/
gain, associated PAE,
:amplifierspower
)11(
2/) (
alone or
min
1max
max
max
max
cb
cbb
cex
ccb
clock
ττ
VIR
VIR
IVC
f
m
ff
ff
ff
ff
:metrics better much
:metrics popular
0
100
200
300
400
500
600
700
800
0 100 200 300 400 500 600 700 800
RSC
UIUC_SHBT
NTT_fmax
Fujitsu HEMT
SFU
UIUC_DHBT
UCSB 500 nm
NGST
Pohang
HRL
IBM SiGe
Vitesse
UCSB 250 nm
f ma
x (G
Hz)
ft (GHz)
500 GHz400 GHz300 GHz200 GHz maxff
Updated July 5 2006
250 nm
Red = manufacturable technology for 10,000- transistor ICs
500 nm
Bipolar Transistor Scaling Laws
key device parameter required change
collector depletion layer thickness decrease 2:1
base thickness decrease 1.414:1
emitter junction width decrease 4:1
collector junction width decrease 4:1
emitter resistance per unit emitter area decrease 4:1
current density increase 4:1
base contact resistivity (if contacts lie above collector junction)
decrease 4:1
base contact resistivity (if contacts do not lie above collector junction)
unchanged
Design changes required to double transistor bandwidth
InP HBT Scaling Roadmaps
Key scaling challengesemitter & base contact resistivitycurrent density→ device heatingcollector-base junction width scaling & Yield !
key figures of merit
for logic speed
2005: InP DHBTs @ 500 nm Scaling Generation
Target Performance:400 GHz f 500 GHz fmax
150 GHz digital clock rate (static dividers)250 GHz power amplifiers
collector: 150 nm thick, 5 mA/m2 current density10 mW/m2 power density @ 2V
InGaAs base
BC grade
collector
N+ sub collector
S.I. InP substrate
emitter
emitter contact
base contact
N- drift collector
emitter: 500 nm width, 15 m2 contact resistivity
base contact: 300 nm width, 20 m2 contact resistivity
2006: 250 nm Scaling Generation, 1.414:1 faster
Target Performance:500 GHz f 700 GHz fmax
230 GHz digital clock rate (static dividers)400 GHz power amplifiers
collector: 100 nm thick, 10 mA/m2 current density20 mW/m2 power density @ 2V
InGaAs base
BC grade
collector
N+ sub collector
S.I. InP substrate
emitter
emitter contact
base contact
N- drift collector
emitter: 250 nm width, 7.5 m2 contact resistivity
base contact: 150 nm width, 10 m2 contact resistivity
125 nm Scaling Generation→ almost-THz HBT
Target Performance:700 GHz f ~1000 GHz fmax
330 GHz digital clock rate (static dividers)600 GHz power amplifiers
collector: 75 nm thick, 20 mA/m2 current density40 mW/m2 power density @ 2V
~3-4 V breakdown (BVCEO)
InGaAs base
BC grade
collector
N+ sub collector
S.I. InP substrate
emitter
emitter contact
base contact
N- drift collector
emitter: 125 nm width, 5 m2 contact resistivity
base contact: 75 nm width, 5 m2 contact resistivity
65 nm Scaling Generation→beyond 1-THz HBT
Target Performance:1.0 THz f 1.7 GHz fmax
450 GHz digital clock rate (static dividers)1 THz power amplifiers
collector: 53 nm thick, 35 mA/m2 current density70 mW/m2 power density @ 2V→ 2-3 V breakdown (BVCEO)
InGaAs base
BC grade
collector
N+ sub collector
S.I. InP substrate
emitter
emitter contact
base contact
N- drift collector
emitter: 62.5 nm width, 2.5 m2 contact resistivity
base contact: 70 nm width, 5 m2 contact resistivity
THz Transistors:addressing the keyscaling challenges
Wafer first cleaned in reducing
Pd & Pt react with III-V semiconductor
Penetrate surface oxide
Today provide 5 -m2 resistivity (base)
→ investigate better cleaning, alternative
reaction metals
Our HBT Base Contacts Today Use Pd or Pt to Penetrate Oxides
Reacted region
Pt
InGaAs
Au
Pt
Reacted region
InGaAs
Pt Contact after 4hr 260C Anneal
Pt/Au Contact after 4hr 260C Anneal
TEM : Lysczek, Robinson, & Mohney, Penn State Sample: Urteaga, RSC
Chor, E.F.; Zhang, D.; Gong, H.; Chong, W.K.; Ong, S.Y. Electrical characterization, metallurgical investigation, and thermal stability studies of (Pd, Ti, Au)-based ohmic contacts. Journal of Applied Physics, vol.87, (no.5), AIP, 1 March 2000. p.2437-44.
Reducing Emitter Resistance: ErAs Emitter Contacts
Epitaxial semimetal similar crystal structure to III-V semiconductors can be grown by MBE
Material Lattice constant
mismatch to ErAs
mismatch to ErSb
ErAs 5.7427Å
ErSb 6.108Å
GaAs 5.6532Å -1.6% -8.0%
InP 5.8687Å 2.1% -4.0%
GaSb 6.0959Å 5.8% -0.2%
III Er AsQ. G. Sheng, J. Appl. Phys. (1993)
A Guivarc’h, J. Appl. Phys. (1994)
ErAs: Rocksalt structure
III-V: Zinc blend structure
*A. Guivarc’h, Electron. Lett.(1989)**C.J.Palmstrøm Appl. Phys. Lett. (1990)
Zimmerman, Gossard & Brown, UCSB
In-situ contacts → no oxides, no contaminants Lattice matched → few defect states → no surface Fermi pinningThermodynamically stable → little intermixingWell-controlled (atomic precision) interface
Temperature Rise Within Transistor & Substrate
e
e
EInPInP W
L
LK
PT ln
increase re temperatulogarithic scaling HBT
1,
1:2 decreases spacing HBT
1:4 decreases dth emitter wi
rateclock digitalin doublingeach For
D
We
0
20
40
60
80
100
120
140
100 200 300 400 500 600 700
tem
pe
ratu
re r
ise
in s
ub
stra
te, K
elvi
n
master-slave D-Flip-Flop clock frequency, GHz
clocksub fT GHz/ 160 m 15
rateclock digital GHz 300at even
rise re temperatusubstrate acceptable
allowsly aggressive substrate theThinning
Temperature Rise Within Package
chipCu
chippackage WK
PT
2
2
Rise eTemperatur Package Total
0
50
100
150
200
100 200 300 400 500 600
pa
cka
ge t
em
pe
ratu
re r
ise
, K
elv
in
fclock,
GHz
12 mA per transistor (25 logic load resistor)
3 mA per transistor (100 logic load resistor)
n)dissipatior transisto( 1.5 power IC
rs/IC transisto1000
bias V 2
)GHz/ (150 m 20 :spacing Transistor
:sAssumption
ce
clock
V
f
rate.clock digital GHz 300at even
IC / rs transisto1000 with
rise re temperatupackage acceptable
loading) (100stor per transi mA 3At
1:2 decrease dimensions chip
1:2 decreases spacing HBT
1:4 decreases dth emitter wi
rateclock digitalin doublingeach For
chip
e
W
D
W
UCSB DHBTs: 500-600 nm Scaling Generation
1.3 m base-collector mesa1.7 m base-collector mesa
Zach Griffith
600 nm emitter width
40, VBR,CEO = 3.9 V.
Emitter contact Rcont < 10 m2
Base : Rsheet = 610 /sq, Rcont = 4.6 m2
Collector : Rsheet = 12.1 /sq, Rcont = 8.4 m2
Vcb
= -0.3 V
0
2
4
6
8
10
0 2.5 5 7.5 10 12.50
5
10
15
20
25
Ccb
/Ae (
fF/
m2 )
Je (mA/m2)
Ccb (fF
)
-0.2 V
0.0 V
0.2 V
Vcb
= 0.6 V
Ajbc
= 1.3 x 6.5 m2
Ccb
/Ic=0.2 ps/V
0.4 ps/V
0.6 ps/V
0.8 ps/V
1.0 ps/V1.5ps/V
Ajbe
= 0.6 x 4.3 m2
Zach Griffith
0
5
10
15
20
25
30
35
109 1010 1011 1012
Gai
ns (
dB
)
Frequency (Hz)
U
Ajbe
= 0.6 x 4.3 um2
Ic = 20.6 mA, V
ce = 1.53 V
Je = 8.0 mA/um2, V
cb= 0.6 V
ft = 450 GHz, f
max = 490 GHz
h21
10-12
10-10
10-8
10-6
10-4
0.01
0 0.25 0.5 0.75 1
I b, Ic (
A)
Vbe
(V)
VCB
= 0.0 V (dashed)
VCB
= 0.3 V (solid)
Ic
Ib
nc = 1.12
nb = 1.41
Gummel characteristics
InP DHBT: 600 nm lithography, 120 nm thick collector, 30 nm thick base
Average 50, BVCEO = 3.2 V, BVCBO = 3.4 V (Ic = 50 A)
Emitter contact (from RF extraction), Rcont 8.6 m2
Base (from TLM) : Rsheet = 805 /sq, Rcont = 16 m2
Collector (from TLM) : Rsheet = 12.0 /sq, Rcont = 4.7 m2
InP DHBT: 600 nm lithography, 75 nm collector, 20 nm base
Peak f
Peak fmax
DC characteristics
RF characteristics
Aje = 0.65 4.3 m2 , Ib,step = 175 A
unitsdata
current steering
data emitter
followers
clock current steering
clock emitter
followerssize m2 0.5 x 3.5 0.5 x 4.5 0.5 x 4.5 0.5 x 5.5
currentdensity
mA/m2 6.9 4.4 4.4 4.4
Ccb/Ic psec / V 0.59 0.99 0.74 0.86
Vcb V 0.6 0 0.6 1.7
f GHz 301 260 301 280
fmax GHz 358 268 358 280
UCSB / RSC / GCS 150 GHz Static Frequency Dividers
-40
-30
-20
-10
0
10
20
0 20 40 60 80 100 120 140 160
Min
imu
m in
put
pow
er (
dBm
)
frequency (GHz)
IC design: Z. Griffith, UCSBHBT design: RSC / UCSB / GCSIC Process / Fabrication: GCSTest: UCSB / RSC / Mayo
-80
-70
-60
-50
-40
-30
74.9975 74.9987 75.0000 75.0012 75.0025
Out
put
Pow
er (
dB
m)
frequency (GHz)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0.00 19.00 38.00 57.00 76.00
Out
put
Pow
er (
dB
m)
frequency (GHz)
probe station chuck @ 25C
PDC,total = 659.8 mWdivider core without output buffer 594.7 mW
7.5 mW output power
175 GHz Amplifiers with 300 GHz fmax Mesa DHBTs
7 dB gain measured @ 175 GHz
2 fingers x 0.8 um x 12 um, ~250 GHz f, 300 GHz fmax , Vbr ~ 7V, ~ 3 mA/um2 current density
V. Paidi, Z. Griffith, M. Dahlström
-10
-5
0
5
10
15
140 150 160 170 180 190 200
S2
1, S1
1, S
22 d
B
Frequency, GHz
S21
S11
S22
7-dB small-signal gain at 176 GHz8.1 dBm output power at 6.3 dB gain
250 nm scaling generation DHBTs
• 100 % I-line lithography
• Emitter contact resistance reduced 40%: from 8.5 to 5 m2
• Base contact resistance is < 5 m2 --hard to measure
• Recall, 1/8 m scaling generation needs 5 m2 emitter c
0.30 µm emitter junction, Wc/We ~ 1.6
First mm-wave results with 250 nm InP DHBTs
150 nm material
250 nm emitter width
f = 420 GHzfmax = 650 GHz~6 V breakdown30 mW/um2 power handling
results submitted postdeadline to 2006 DRC, E. Lind et al
330 GHz Cascode Power Amplifiers In Design
Thin-film microstrip lines Output Psat = 50 mW (17 dBm) 10-dB associated power gain use the 650 GHz fmax transistors
-5
0
5
10
15
20
0
0.05
0.1
0.15
0.2
0.25
-15 -10 -5 0 5 10
Gai
n (d
B),
Out
put P
ower
(dB
m)
PA
E (%
)
Input Power, dBm
PAE
Gain
Output Power
-10
-5
0
5
10
15
260 280 300 320 340 360
S21
, S
11,
S22
( d
B )
Frequency, GHz
S21
S11
S22
Frequency Limits of Bipolar Integrated Ciruits
Done: ~475 GHz ft & fmax 150 GHz static dividers 160 Gb/s MUX & DMUX (Chalmers/Vitesse)
250 nm results coming very soon. expect ~200 GHz digital clock rate, 340 GHz amplifiers
THz transistors will come The approach is scaling. The limits are contact and thermal resistance.
Performance Parameters for Fast Logic & Mixed-Signal
clock clock clock clock
inin
out
out
cexLOGIC
LOGIC
Ccb
becbi
becbC
LOGIC
IRq
kTV
V
IR
CCR
CCI
V
4
leastat bemust swing logic The
resistance base the through
charge stored
collector base Supplying
resistance base the through
charging ecapacitanc on Depleti
swing logic the through
charging ecapacitanc on Depleti
:by ermined Delay DetGate
bb
depletion,bb
depletion,
JVR
CI
CCIV
f
ex
cbC
becbCLOGIC
cb
high at lowfor low very bemust
objective.design HBTkey a is /High
total.of 80%-55% is
with correlated not wellDelay
delay; totalof 25%-10y typicall)(
logic
depl,
Design HBTs for fast logic, not for high ft & fmax
Performance Parameters for mm-wave Power
0
5
10
15
20
25
30
10 100
MS
G/M
AG
, dB
Frequency, GHz
Common base
Common Collector
Common emitter
U
Gain.....under large-signal conditions
...gain is less than MAG/MSG...
0
2
4
6
8
10
0 1 2 3 4 5 6 7 8
J e (m
A/
m2 )
Vce
(V)
6.8 V BVCEO
10 mW/um2
20 mW/um2
maxminmaxmax 81 IVVP
Breakdown AND power density
top related