floorplanning, placement, pin assignment and routing
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INDIAN INSTITUTE OF TECHNOLOGY ROORKEE
Floorplanning, Placement, Pin Assignment and Routing
Bishnu Prasad Das
Assistant Professor,
Department of Electronics and Communication Engineering,
IIT Roorkee
Email: bpdasfec@iitr.ac.in
2IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Output of Partitioning
• Partitioning leads to :
– Blocks with well defined areas and shapes (Fixed blocks)
– Blocks with approximated areas and no particular shape(Flexible
blocks)
– A netlist specifying connections between the blocks
• Objectives:
– Find locations for all blocks
– Shapes of flexible blocks
– Pin locations for all the blocks
3IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplanning
• Input to the floorplanning problem:
– A set of blocks, both fixed and flexible
– Pin locations of fixed blocks
– A netlist
• Objectives:
– Minimize area
– Determine shapes of flexible blocks
– Reduce netlength for critical nets
4IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Placement
• Input to the placement problem:
– A set of blocks with well defined shapes
– Pin locations
– A netlist
• Objectives:
– Minimize area
– Reduce netlength for critical nets
5IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Pin Assignment
• Input to the Pin assignment problem:
– A placement of blocks
– Number of pins on each block, possibly an ordering
– A netlist
• Objectives:
– To determine the pin locations on the blocks to reduce netlength
6IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplanning Algorithms
• Floorplanning Algorithms
– Floorplan Sizing
– Cluster Growth
– Simulated Annealing
– Integrated Floorplanning Algorithms
7IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplanning Algorithms
Common Goals
To minimize the total length of interconnect, subject to an upper bound on
the floorplan area
or
To simultaneously optimize both wire length and area
8IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing
Legal shapes Legal shapes
w
h
w
h
Block with minimum width and
height restrictions
ha*aw A
Shape Functions
9IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing
Shape functions
w
h
Hard library block
w
h
Discrete (h,w) values
10IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing
Corner points
5
2
2
5
2 5
2
5
w
h
11IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing
Algorithm
This algorithm finds the minimum floorplan area for a given slicing floorplan in
polynomial time. For non-slicing floorplans, the problem is NP-hard.
Construct the shape functions of all individual blocks
Bottom up: Determine the shape function of the top-level floorplan
from the shape functions of the individual blocks
Top down: From the corner point that corresponds to the minimum top-level
floorplan area, trace back to each block’s shape function to find that block’s
dimensions and location.
12IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
4
2
2
4
Block B:
Block A:
5
5
3
3
Step 1: Construct the shape functions of the blocks
13IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
4
2
2
4
Block B:
Block A:
5
5
3
3
Step 1: Construct the shape functions of the blocks
2
4
h
6
w2 64
5
3
14IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
4
2
2
4
Block B:
Block A:
5
5
3
3
Step 1: Construct the shape functions of the blocks
2
4
h
w2 64
6
3
5
15IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
4
2
2
4
Block B:
Block A:
5
5
3
3
w2 6
2
4
h
4
6
hA(w)
Step 1: Construct the shape functions of the blocks
16IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
4
2
2
4
Block B:
Block A:
5
5
3
3
hB(w)
w2 6
2
4
h
4
6
hA(w)
Step 1: Construct the shape functions of the blocks
17IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
hB(w)
hA(w)
8
Step 2: Determine the shape function of the top-level floorplan (vertical)
18IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
hB(w)
hA(w)
8
Step 2: Determine the shape function of the top-level floorplan (vertical)
19IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
w2 6
2
4
h
4
6
hB(w)
hA(w)
hB(w)
hA(w)
hC(w)
88
Step 2: Determine the shape function of the top-level floorplan (vertical)
20IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
w2 6
2
4
h
4
6
hB(w)
hA(w)
hB(w)
hA(w)
hC(w)
5 x 5
88
Step 2: Determine the shape function of the top-level floorplan (vertical)
21IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
w2 6
2
4
h
4
6
hB(w)
hA(w)
hB(w)
hA(w)
hC(w)
3 x 9
4 x 7
5 x 5
88
Step 2: Determine the shape function of the top-level floorplan (vertical)
22IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
w2 6
2
4
h
4
6
hB(w)
hA(w)
hB(w)
hA(w)
hC(w)
3 x 9
4 x 7
5 x 5
88
Minimimum top-level floorplan
with vertical composition
Step 2: Determine the shape function of the top-level floorplan (vertical)
23IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
w2 6
2
4
h
4
6
hA(w)hB(w) hC(w)hA(w)hB(w)
9 x 3
7 x 4
5 x 5
88
Step 2: Determine the shape function of the top-level floorplan (horizontal)
Minimimum top-level floorplan
with horizontal composition
24IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
Step 3: Find the individual blocks’ dimensions and locations
w2 6
2
4
h
4
6
8
(1) Minimum area floorplan: 5 x 5
Horizontal composition
25IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
w2 6
2
4
h
4
6
(1) Minimum area floorplan: 5 x 5
(2) Derived block dimensions : 2 x 4 and 3 x 5
8
Step 3: Find the individual blocks’ dimensions and locations
Horizontal composition
26IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
2 x 4 3 x 5
5 x 5
Step 3: Find the individual blocks’ dimensions and locations
w2 6
2
4
h
4
6
(1) Minimum area floorplan: 5 x 5
(2) Derived block dimensions : 2 x 4 and 3 x 5
8
Horizontal composition
27IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Floorplan Sizing – Example
2 x 4 3 x 5
5 x 5
Resulting slicing tree
B
V
AB A
28IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Placement
29IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Introduction
ENTITY test is
port a: in bit;
end ENTITY test;
DRC
LVS
ERC
Circuit Design
Functional Design
and Logic Design
Physical Design
Physical Verification
and Signoff
Fabrication
System Specification
Architectural Design
Chip
Packaging and Testing
Chip Planning
Placement
Signal Routing
Partitioning
Timing Closure
Clock Tree Synthesis
30IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Introduction
© 2
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ger
Verla
g
c
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f
b
a
gd
e
a c b hg d ef
eh
g f
d a
c b
GND
VDD
Linear Placement
2D Placement Placement and Routing with Standard Cells
h e d a
g f c b
31IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Introduction
Global
Placement
Detailed
Placement
32IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Optimization Objectives
Total
Wirelength
Number of
Cut Nets
Wire
CongestionSignal
Delay
© 2
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Verla
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33IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Optimization Objectives – Total Wirelength
Wirelength estimation for a given placement
Half-perimeter
wirelength
(HPWL)
HPWL = 9
4
5
Complete
graph
(clique)
8
6
5
33
4
Clique Length =
(2/p)e cliquedM(e) = 14.5
Monotone
chain
Chain Length = 12
63
3
Star model
Star Length = 15
83
4
Sait, S
. M
., Y
oussef,
H.:
VLS
I P
hysic
al D
esig
n A
uto
matio
n, W
orld
Scie
ntific
34IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Optimization Objectives – Total Wirelength
Sait, S
. M
., Y
oussef,
H.:
VLS
I P
hysic
al D
esig
n A
uto
matio
n, W
orld
Scie
ntific
Wirelength estimation for a given placement (cont‘d.)
Rectilinear
minimum
spanning
tree (RMST)
RMST Length = 11
3
3
5
Rectilinear
Steiner
minimum
tree (RSMT)
RSMT Length = 10
3
1
6
Rectilinear
Steiner
arborescence
model (RSA)
RSA Length = 10
+5
3 +2
Single-trunk
Steiner
tree (STST)
STST Length = 10
3
12
4
35IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Optimization Objectives – Total Wirelength
Preferred method: Half-perimeter wirelength (HPWL)
Fast (order of magnitude faster than RSMT)
Equal to length of RSMT for 2- and 3-pin nets
Margin of error for real circuits approx. 8% [Chu, ICCAD 04]
hwL HPWL
RSMT Length = 10
3
1
6
HPWL = 9
4
5
w
h
Wirelength estimation for a given placement (cont‘d.)
36IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Simulated Annealing
Time
Cost
Analogous to the physical annealing process
Melt metal and then slowly cool it
Result: energy-minimal crystal structure
Modification of an initial configuration (placement) by moving/exchanging
of randomly selected cells
Accept the new placement if it improves the objective function
If no improvement: Move/exchange is accepted with temperature-dependent
(i.e., decreasing) probability
37IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Simulated Annealing
Input: set of all cells V
Output: placement P
T = T0 // set initial temperature
P = PLACE(V) // arbitrary initial placement
while (T > Tmin)
while (!STOP()) // not yet in equilibrium at T
new_P = PERTURB(P)
Δcost = COST(new_P) – COST(P)
if (Δcost < 0) // cost improvement
P = new_P // accept new placement
else // no cost improvement
r = RANDOM(0,1) // random number [0,1)
if (r < e -Δcost/T) // probabilistically accept
P = new_P
T = α ∙ T // reduce T, 0 < α < 1
38IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Simulated Annealing
Advantages:
Can find global optimum (given sufficient time)
Well-suited for detailed placement
Disadvantages:
Very slow
To achieve high-quality implementation, laborious parameter tuning is necessary
Randomized, chaotic algorithms - small changes in the input
lead to large changes in the output
Practical applications of SA:
Very small placement instances with complicated constraints
Detailed placement, where SA can be applied in small windows
(not common anymore)
FPGA layout, where complicated constraints are becoming a norm
39IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Simulated Annealing
Time
Cost
Analogous to the physical annealing process
Melt metal and then slowly cool it
Result: energy-minimal crystal structure
Modification of an initial configuration (placement) by moving/exchanging
of randomly selected cells
Accept the new placement if it improves the objective function
If no improvement: Move/exchange is accepted with temperature-dependent
(i.e., decreasing) probability
40IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Routing
41IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Introduction
ENTITY test isport a: in bit;
end ENTITY test;
DRCLVSERC
Circuit Design
Functional Designand Logic Design
Physical Design
Physical Verificationand Signoff
Fabrication
System Specification
Architectural Design
Chip
Packaging and Testing
Chip Planning
Placement
Signal Routing
Partitioning
Timing Closure
Clock Tree Synthesis
42IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Introduction
Given a placement, a netlist and technology information,
determine the necessary wiring, e.g., net topologies and specific routing
segments, to connect these cells
while respecting constraints, e.g., design rules and routing resource
capacities, and
optimizing routing objectives, e.g., minimizing total wirelength and
maximizing timing slack.
43IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Introduction
Terminology:
Net: Set of two or more pins that have the same electric potential
Netlist: Set of all nets.
Congestion: Where the shortest routes of several nets are incompatible
because they traverse the same tracks.
Fixed-die routing: Chip outline and routing resources are fixed.
Variable-die routing: New routing tracks can be added as needed.
44IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Introduction: General Routing Problem
C
D
A
B
43
21
4
3
4
1
1
654
Netlist:
N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4}N3 = {C2, D5}N4 = {B1, A1, C3}
Technology Information (Design Rules)
Placement result
45IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
Technology Information (Design Rules)
C
D
A
B
43
21
4
3
4
1
1
654
N1
Introduction: General Routing Problem
46IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
Technology Information (Design Rules)
C
D
A
B
43
21
4
3
4
1
1
654
N2 N3N4 N1
Introduction: General Routing Problem
47IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Types of Routing
Timing-Driven
Routing
Global
Routing
Detailed
Routing
Large
Single- Net
RoutingCoarse-grain
assignment of
routes to
routing regions
Fine-grain
assignment
of routes to
routing tracks
Net topology
optimization
and resource
allocation to
critical nets
Power (VDD)
and Ground
(GND)
routing
Routing
Geometric
Techniques
Non-Manhattan
and
clock routing
Multi-Stage Routing
of Signal Nets
48IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Global versus Detailed Routing
N3
N3
N1 N2N1
N3
N1N2
N3
N3
N1 N2N1
N3
N1N2
Horizontal
SegmentVia
Vertical
Segment
Detailed RoutingGlobal Routing
49IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
References
1. Sherwani, N.A., “Algorithm for VLSI Physical Design
Automation”, 2nd Ed., Kluwer, 1999.
2. Kahng, A.B., Lienig, J., Markov, I.L., Hu, J., “VLSI Physical
Design: From Graph Partitioning to Timing Closure”,
Springer, 2011.
Slides from this website
http://vlsicad.eecs.umich.edu/KLMH/presentations.html
50
THANKS
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