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Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 1
Fermilab PAC Meeting April 12, 2001
Marcel DemarteauFermilab
‘‘Status and Scope Status and Scope DDØ Ø Run 2b Silicon Tracker’Run 2b Silicon Tracker’
For the Run 2b Silicon GroupFor the Run 2b Silicon Group
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 2
OutlineOutline
Brief reminder of design No change in overall layout of the detector Changes in sub-components
» Advancement of design cooling layer 0 hybrids
» Better performance details of stave design
» Easier design Eliminated fingers on hybrid
Schedule Completion May-June ‘05
Scope
Picture based on Geant Model
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 3
Basic LayoutBasic Layout
Six layer silicon tracker, divided in two radial groups Inner layers: Layers 0 and 1
» Axial readout only» Mounted on integrated support» Assembled into one unit
» Designed for Vbias up to 700 V Outer layers: Layers 2-5
» Axial and stereo readout» Stave support structure
» Designed for Vbias up to 300 V
Employ single sided silicon only, 3 sensor types
2-chip wide for Layer 0 3-chip wide for Layer 1 5-chip wide for Layers 2-5
No element supported from the beampipe Drilled Be Beampipe with ID of 0.96”, 500m wall thickness
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 4
Layer 0Layer 0
Support Structure 12-fold crenellated geometry carbon fiber support possible use of pyrolitic graphite sensors cooled to T=-10 oC Rin = 18.5 mm
Silicon
Analogue cable
Hybrid
Assembly 2-chip wide sensors 25 mm pitch, 50 mm readout Analogue cables for readout Hybrids off-board Staggered in z for 6 readouts per end
per phi-sector Space is extremely tight !
Outside tracking volume
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 5
Layer 0 Support StructureLayer 0 Support Structure
Prototype support structure made by University of Washington Crenellated mandrel
» Stacking sequences Cylindrical Shell: 3 ply 0º, 90º, 0º laminate Castellated Shell: 6 ply [0º, +20º, -20º]s laminate
RTV pressure strips, vacuum bag Pressured to 85 psi Cured in autoclave at 275 °F
castellated shell
Measurements and comparisons of elastic properties of prepreg. laminates
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 6
Layer 1Layer 1
Support Structure 12-fold crenellated geometry carbon fiber support Integrated cooling Rin = 34.8 mm
Assembly 3-chip wide sensors,
58 m pitch, axial readout Hybrids on-board 6-chip double-ended hybrid
readout
Cooling lines
Silicon
Hybrid
Digital cable
L0
Full view layer 1
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 7
Layers 2-5Layers 2-5
12, 18, 24 and 30-fold geometry All layers:
5-chip wide sensors, 30 m pitch, 60 m readout
Hybrids on-board 10-chip hybrid readout Stereo and axial readout Stereo angle obtained by rotating
sensor Support
Modules are assembled into staves Staves are positioned with carbon-
fiber bulkheads Steady progress on stave design
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 8
Silicon ReadoutSilicon Readout
SVX4 Submitted (finally) to TSMC on March 28 SVX4 Test cards to qualify chip, design finished
Analogue cable for Layer 0 Low mass, fine pitch cables to bring analogue signals
outside of tracking volume Technically challenging
» Trace width ~ 10 m, pitch 100 m» C ~ 0.4 pF/cm
Two vendors» Dyconex (2nd prototype) » Compunetics
Hybrids Common technology with CDF First hybrids delivered
Digital Cable (KSU) Two vendors: Honeywell, Basic Electronics
Adapter Cards (KSU) Design nearing completion
Digital cable
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 9
ProgressProgress
Expect to have full scale prototype of all elements by this fall
Ordered Delivered Ordered Delivered
ELMA
HPK
ELMA
HPK
L2 Sensors
Dycx
Comp
L0 Hybrid
L1 Hybrid
L2A Hybrid
L2S Hybrid
Honey
Basic
J unction Card
Twisted Pr. Cable
Adapter Card
L0 Sensors
L1 Sensors
Analogue Cable
Digital Cable
First Prototype Second Prototype
Component Vendor Design
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 10
Alternate Designs with Reduced ScopeAlternate Designs with Reduced Scope
Given that many elements are already in prototype stage, reduced scope obtained by omitting various element
No re-optimization consideredWould set project back by at least 6-9 months
Variation of radii, width of sensors different type of sensors …
Options considered for reduced scope Omission of Layer 4 Omission of Layer 1 Omission of sensors at large |z|
Folding in realism
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 11
Reference: TDR DesignReference: TDR Design
Fiber tracker has full coverage up to || < ~1.6 Require silicon stand-alone tracking for || > ~1.6 Studies based on full Geant simulation
b-tag: signed impact parameter, Eb > 20 GeV
» Track selection within cone R < 0.5 of b-jet pT > 0.5 GeV/c, good 2, hits in silicon 2
» Impact parameter significance 2 tracks: d0/(d0) > 3
3 tracks: d0/(d0) > 2
Based on WH-events, with b’s falling within acceptance
TDR
P(nb1) 76%
P(nb2) 29%
Mistag Rate < 1.5 %
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 12
Omission of Layer 4Omission of Layer 4
Consider CFT+SMT tracking One stereo measurement less Tracking efficiency and b-tagging eff.
degraded But double number of tracks with poor
quality (pattern recognition)
4 Si hits
5 Si hits
2
In addition lose 2% in lepton id.
TDR - L4 Rel. Loss
P(nb1) 73% 3.2%
P(nb2) 26% 10.3%
Mistag Rate < 1.5 %
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 13
Omission of Layer 4Omission of Layer 4
Consider Silicon Stand-Alone tracking Important in forward region with no full coverage of CFT Important in lepton identification Important tool for consistency checks
Tracking efficiency and fake rate Fake rate: factor 10 larger for tracks with 4/5 (TDR-L4) compared to 5/6
hits At same fake rate
» Central region reduction of: track finding eff. by 10%, b-tag eff. by 20%» Forward region reduction of: track finding eff. by 22%, b-tag eff. by
40%
TDR - L4 (SA) Rel. Loss
P(nb1) 61% 19.3%
P(nb2) 18% 38.0%
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 14
Omission of Layer 1Omission of Layer 1
A priori undesirable Layer 1 also a contingency in case problems encountered with layer 0
» Deterioration of impact parameter resolution by ~10% for L2-L3 system
Mistag rate doubles if layer 1 removed. Compare using same mistag rate
TDR - L1 Rel. Loss
P(nb1) 66% 12.2%
P(nb2) 22% 24.0%
Mistag Rate < 1.5 %
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 15
Folding in Realism Folding in Realism
So far assumed detectors are perfect; reality, however, is different Example: Run2a silicon detector
» Barrels / F-disks / H-disks: 93%, 96%, 89% functioning devices Assume certain fraction of Si ladders dead, 30% inefficiency in CFT
lyr 1 effect on b-tagging efficiency
Fraction of non-working devices
Rela
tive in
cre
ase in
in
effi
cie
ncy
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 16
Reduced CoverageReduced Coverage
Remove sensors at large |z|, reduced || acceptance Studied at generator level for WH events
23% decrease in acceptance for both b-quarks 8% decrease in acceptance for lepton from W-decay Overall loss in acceptance of 27%
Probability for muon to be within cut
| |<2.0 93% 74% 67%
| |<1.5 86% 57% 49%
Acceptance Loss
8% 23% 27%
cut Probability for two b-jets to be within cut
Probability for two b-jets and lepton to be within cut
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 17
Summary on ScopeSummary on Scope
TDR design: b tagging efficiency of ~65% Higgs working group simulations
assume even higher b-tag efficiencies Omission of any element would significantly affect
physics reach and diverge from the basis of justification for Run 2b
b-tagging efficiencies would fall below 50%, especially if analyses would require tighter tagging algorithm
20% loss in luminosity on 15 fb-1, 5 GeV reduction in reach on mH (115-135 GeV)
Assuming 12 fb-1 /3yrs
Lumi (double b-tag)
Running time(months)
-24% (w/o ineff.)-44% (w/ ineff.)
8.615.9
Global Tracking-12% (w/o ineff.)-14 % (w/ ineff.)
4.45.0
SMT stand-alone
-38% 13.7
-27% 9.7TDR - z
Alternative Design
TDR - L1
TDR - L4
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 18
SummarySummary
Project is well into prototyping phase; significant progress has been made over the last 5 months
Results from our studies indicate that all baseline elements are necessary to address physics opportunities of Run 2b
Given the narrow window of opportunity, any reduction in scope would adversely affect the justification for Run 2b
Project is well positioned to present Current full scale design Schedule Resource estimates Project cost estimate
to the review committees to get this silicon detector baselined.
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 19
Outer Layer ModulesOuter Layer Modules
Staves are assembled from readout modules Readout modules:
6 types » 10-10 (axial, stereo)» 10-20 (axial, stereo)» 20-20 (axial, stereo)
Stereo angle determined by mechanical constraints
» 10cm readout: = 2.5o
» 20cm readout: = 1.25o
» For 10-20 readout module, there will be a small gap at the transition Ganged sensors will have traces aligned
Module configuration
Layer 4-5
Layer 2-3
10-10 10-20
20-20
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 20
Stave StructureStave Structure
Stave is doublet structureof four readout modules
Two layers of silicon » Axial and stereo» Two readout modules each
separated by PEEK cooling lines Total of 168 staves
Stave has carbon fiber cover Protect wirebonds Provide path for digital cables
Staves are mounted in end carbon fiber bulkheads
Cooling manifold similar to bulkhead design
Layer 4-5 stave
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 21
Stave Readout SchematicStave Readout Schematic
Hybrid Digitizes Si analogue signal, launches the digital signal on the …
Digital cable Flex circuit which brings signals to the …
Junction card Passive element which transfers signals to high quality twisted pair signal
cable which brings the signal to the … Adapter card
Active element that provides the differential drive for the svx4 chip
Hybrids Digital Cables
Twisted Pair CableLow Mass Jumper Cable
Junction Card
Layer 4-5
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 22
HybridsHybrids
Characteristics: Layer 0
» 2-chip hybrids; each hybrid reads out one sensor Layers 1-5
» Hybrids are double-ended 6-chip hybrids for layer 1 10-chip hybrids for layers 2-5
Design of Layer 1 hybrid complete » Ceramic hybrid (BeO) » 6 layers » Connector pinout frozen
Hybrids carry the bias voltage for layers 2-5 (300 V)
One HV feed / hybrid; HV is split between up to 4 sensors
Prototype hybrids for Layer 1 ready to be ordered
6-chip hybrid
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 23
Overall Plan ViewOverall Plan View
Junction cards
Cooling bulkheads
Positioning bulkhead
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 24
ParametersParameters
Comparing channel count: 2a: 792576 channels 2b: 952320 channels
Cable plant is slightly smaller than in Run2a
# Sensorsin z
# SensorsTotal
SensorWidth
Readout Pitch
# Readout in z
# Chips perReadout Total Chips
# HybridsTotal
Layer NphiR (mm)Axial
R (mm)Stereo (mm) (m)
0A 12 17.80 --- 12 72 15.50 50 12 2 144 720B 12 24.65 --- 12 72 15.50 50 12 2 144 721A 12 34.80 --- 12 72 24.97 58 12 3 216 361B 12 38.85 --- 12 72 24.97 58 12 3 216 362A 12 53.57 50.45 10 120 41.10 60 8 5 480 482B 12 69.93 66.81 10 120 41.10 60 8 5 480 483A 18 88.10 84.98 10 180 41.10 60 8 5 720 723B 18 102.30 99.18 10 180 41.10 60 8 5 720 724A 24 119.69 116.57 12 288 41.10 60 8 5 960 964B 24 133.19 130.07 12 288 41.10 60 8 5 960 965A 30 150.36 147.25 12 360 41.10 60 8 5 1200 1205B 30 163.59 160.47 12 360 41.10 60 8 5 1200 120
Total 2184 7440 888
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 25
PerformancePerformance
Expected performance of new tracker compared with 2a tracker
Z bbar
WH l bbar
Mistag rate 1-2%
Single muons
Run2b Run2a
P(nb >= 1) 80% 68%
P(nb >= 2) 35% 21%
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 26
CostCost
Total M&S Project cost of $8.1 M, without contingency Cost estimate carried out down to WBS level 5 Estimate has changed very little since first estimate
» $6.8M ($10.0M) April ‘01 Cost drivers
» Silicon sensors» Cables, analogue, digital and twisted pair in near equal amounts» Hybrids
WBS 1.1 SILICON TRACKER WBS ITEM MATERIALS & SERVICES (M&S) CO NTINGENCY
1.1 SILICO N TRACKER Unit # Unit M&S TO TAL
Cost TO TAL % Cost Cost
1.1.1 Silicon Sensors 2,244,400 31 703,320 2,947,720
1.1.2 Readout System 3,637,520 47 1,692,004 5,329,524
1.1.3 Mechanical Design and Fabrication 1,649,700 50 830,445 2,480,145
1.1.4 Detector Assembly and Testing 429,000 32 138,050 567,050
1.1.5 Installation 90,000 47 42,500 132,500
1.1.6 Software 51,000 22 11,400 62,400
1.1 SILICO N TRACKER 8,101,620 42 3,417,719 11,519,339
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 27
Near Term Start DatesNear Term Start Dates
Selected near- term start dates Start Dates
Produce L0 sensor prototypes 9/ 11/ 01
Procure L1 hybrid prototypes 11/ 29/ 01
Prepare adapter card prototypes 11/ 29/ 01
Prototype support cylinder 11/ 29/ 01
Order L1 preproduction sensors 12/ 12/ 01
Order L2-L5 preproduction sensors 12/ 12/ 01
Beam Tube Order Placed 12/ 19/ 01
Perf orm L0 sensor irradiation testing 1/ 14/ 02
Fabricate prototype stave cores 1/ 16/ 02
Prepare digital jumper cable prototypes 1/ 21/ 02
Produce L2-L5 preproduction sensors 1/ 25/ 02
Produce pre-production analog cables 3/ 27/ 02
Complete resource loaded schedule being prepared Some near term start dates / milestones
Submitted to ELMA
Ready for submission
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 28
FallbackFallback
The design adequately addresses the physics goals of Run2b Emphasis on impact parameter measurement at small radii Minimum of four stereo measurements needed for efficient pattern
recognition The design is a conservative, not overextended design As such, any descoping would adversely affect physics performance We believe we can build this device within the time frame proposed,
given adequate support Considered ‘what if’ scenarios
Modularity » Inner and outer barrel, north and south tracker built as independent
units Branch points
» Assess viability of various design choices» Assess impact of delivery schedule for various components
Branch points will have to be developed in the near future
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 29
Summary and ConclusionsSummary and Conclusions
The design of the Run2b silicon detector is solid Adequately addresses the physics issues Design not overextended
Schedule is aggressive, but achievable we believe
We are in a position to start ordering prototypes for various elements Delay in procurement will result in linear delay of project The collaboration is committed to building the new detector; if the
project is endorsed, we are looking for a similar commitment from the laboratory
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 30
Boundary Conditions: spatialBoundary Conditions: spatial
Silicon tracker to be installed within existing fiber tracker, with inner radius of 180 mm
Full tracking coverage Fiber tracker up to || < 1.6 Silicon stand-alone up to || <
2.0 Installation in collision hall
Tracker will be split at z=0 Two independent half-modules Reproducible mount at z=0 Alignment verified at SiDet Installation of beampipe
after tracker installation There will be a 3mm gap from
sensor to sensor at z=0
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 31
Luminous RegionLuminous Region
Addresses uncertainty on evolution of beam size over the course of a store Assumed beam crossing centered at z=0; no uncertainties folded in
Coverage of inner layers of 100 cm results in loss of < ~2% of integrated luminosity
Length of inner layer set at 96 cm
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
0 50 100 150 200
Silicon Fiducial Length (cm)
Lu
min
osi
ty A
ccep
tan
ce
3 eV-s40E10/hr
2 eV-s40E10/hr
3 eV-s60E10/hr
2 eV-s60E10/hr
From M. Church
Luminosity acceptance of detector in Run2b running conditions
Longitudinal emittance 2, 3 eV-sec
Stacking rate 40, 60 E10/hr Assumptions:
* = 35 cm Trans. .mm.mrad
0.5 crossing angle 136 rad
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 32
Boundary Condition: DAQBoundary Condition: DAQ
Retain readout system downstream of adapter card Cable plant allows for 912 low mass / high mass cables
Central silicon: 720 H disks: 192
Total number of readout modules cannot exceed 912
3/6/8/9 Chip HDI
Sensor
8’ Low Mass Cable
~19’-30’ High Mass Cable (3M/80 conductor)
HV / LV
Adapter Card
KSU
Interface Board
CLKs CLKs
retain
Some changes to voltage distribution will have to be made
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 33
Irradiation StudiesIrradiation Studies
Irradiation studies carried out with ELMA sensors and CDF layer 00 sensors from Hamamatsu and Micron
Measured Ileak, Vdepl
Measurements agree well with other measurements Calculate Ileak, Vdepl and ENC for various Si temperatures to determine
Si running temperature during operation
T = -10C
R(mm) Mrad Vdep(V) IL/strip(nA) ENCL e-
15 19.98 677.90 883.5 900.020 12.32 425.18 544.9 706.830 6.24 224.29 275.7 502.840 3.85 145.42 170.1 394.850 2.64 105.74 116.9 327.460 1.95 82.72 86.1 280.975 1.34 62.65 59.2 232.9
100 0.83 45.78 36.5 182.9145 0.44 35.60 19.5 133.8165 0.36 36.15 15.7 120.1
Conclude that the design value for Silicon operating temperature at the inner layer should be T= -10 oC
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 34
Comparison 2a and 2bComparison 2a and 2b
2a:» Innermost radius 25.7 mm» Outermost radius 94.3 mm
2b:» Innermost radius 17.5 mm » Outermost radius 163.6 mm
End views drawn to scale
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 35
Design ChoicesDesign Choices
Si temperature of inner layer should be kept at T=-10 oC Heat Load
» ~30 Watts ambient» ~20 Watts at 15 fb-1 at innermost layer (T= -10 oC)» ~0.5 Watts per readout chip
Cooling will use 40%-60% water/ethylene-glycol mixture Tclnt = -15 oC
Option to go to Tclnt = -20 oC with second chiller for inner layers
Heat load too high to allow for readout chips to be mounted on silicon: analogue cables, off-board electronics for innermost layer
Detector HybridAnalogue
cableDigital cable DØ L0
CDF layer 00Analogue cables
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 36
Inner LayersInner Layers
Inner two layers have 12-fold crenellated geometry with carbon fiber lined, carbon foam support structure
Layer 0 2-chip wide sensors,
25 m pitch, 50 m readout Analogue cables for readout Hybrids off-board Rin = 17.8 mm
Layer 1 3-chip wide sensors,
58 m pitch, axial readout Hybrids on-board 6-chip hybrid readout Rin = 34.8 mm
Cooling channelSilicon sensor
Analogue cablestack
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 37
SVX4 ChipSVX4 Chip
Nov ’00 decision to employ common readout chip for CDF and DØ SVX4 in deep sub-micron, 0.25 m technology, intrinsically rad-
hard » Brand new chip with own personality/features
Commercial foundries used That CDF and DØ will use the exact same chip is now very likely
Recently decided to use the same padring Test chip submitted to MOSIS 06/04/01
16 channels LBL design preamp + pipeline 48 channels FNAL design preamp + pipeline
» Common bias preamp+pipeline as in SVX3» 12 different input transistor sizes used to
optimize noise Results:
» Some problems with the chip but they are all understood
» ENC = 450e + 43.0e/pF (optimum)» Pipeline works
LBL Pre-amp
FNAL Pre-amp
Pip
elin
e
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 38
SVX4 ChipSVX4 Chip
Progress this week: Fermilab pre-amp will be implemented in final version of chip Fermilab has full responsibility for the entire FE
Issues: There still remains some concern by LBL about the on-chip bypassing Work on the BE still remains A lot of integration work still remains Schedule has slipped by about 2 months since last year
Schedule: Anticipated submission of the full chip by the end of October Should have full production chips by end of the year
Recall, DØ uses the chip in SVX2 mode Uses single clock for FE and BE, incurs deadtime SVX2 signals single-ended Decided to drive the chip differential
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 39
Inner Layers: layer 0Inner Layers: layer 0
Hybrids are off board 2-chip hybrids Staggered in z for 6 readouts
per end per phi-sector Space is extremely tight !
Analogue cables
Cooling lines
Hybrids
Digital cable stack
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 40
ScheduleSchedule
Complete resource loaded schedule being prepared
Year Milestone Date
1st L0 Sensor Delivered 9/ 11/ 02
All L0 Sensors Delivered And Tested 12/ 6/ 02
L1 Hybrid Production Complete 12/ 17/ 02
L2-L5 Hybrid Production Complete 1/ 30/ 03
1st L1 Sensor Delivered 2/ 11/ 03
L0 Flex Cable Production And Testing Complete 2/ 13/ 03
L0 Hybrid Production Complete 3/ 20/ 03
L1 Module Production Complete 5/ 29/ 03
Beam Tube Accepted 6/ 4/ 03
All L1 Sensors Delivered And Tested 7/ 31/ 03
L0 Module Production Complete 11/ 11/ 03
L0-L1 South Complete 12/ 5/ 03
All L2-L5 Sensors Delivered And Tested 12/ 8/ 03
Layer 2-5 South Complete 12/ 9/ 03
South Silicon Complete 2/ 11/ 04
L0-L1 North Complete 2/ 17/ 04
Shutdown f or I nstallation Begins 5/ 11/ 04
North Silicon Complete 7/ 30/ 04
Silicon Ready To Move To DAB 8/ 6/ 04
Detector I nstalled I n Fiber Tracker 8/ 24/ 04
2002
2003
2004
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 41
Why no 90-degree StereoWhy no 90-degree Stereo
Issues: Due to multiplexing of signals more difficult pattern recognition; more fakes Large incident angles, large number of strips hit
» Preferentially use thinner silicon to partially compensate
Fraction of tracks that have a close neighbor is rather high
» Need to resort to splitting shared clusters Requires double-metal layer; HPK no experience with
dm layers on 6” wafers No definitive answer yet from Run2a data
We have confidence that we can achieve our physics goals with the current design
Of course, 3d-vertex gives additional information, but has to be compared to additional requirements
Complicates design, more sensor types, more testing, probing, more manpower, … DØ made conscientious decision not to adopt 90-degree stereo readout given
manpower and time constraints
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 42
Layer 0Layer 0
Hybrids are off board Analogue cables carry signals 2-chip hybrids Staggered in z for 6 readouts per end per phi-sector
Space is extremely tight !
Hybrid
Digital cable
Stiffening ribs
Six support rings Holds hybrids Provides heat flow
path Six stiffening ribs
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 43
Sensor lengths Inner layers: 79.4 mm, 6 sensors per half-module Outer layers: 100 mm, 5 or 6 sensors per half-module
Longitudinal segmentation
Indicating readout by length of readout segment: » L0, L1: each sensor readout» L2, L3: 10-10-10-20 readout» L4, L5: 10-10-20-20 readout
Governed by: » Number of allowed readout cables» Occupancy, cluster sharing
Hybrids are double-ended, i.e service out two readout segments, indicated by the length of the respective readout segments: 10-10, 10-20, 20-20
Design ChoicesDesign Choices
Z=0 Z (mm)0 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600
Layer 0 S S S S S SLayer 1 1/2D 1/2D 1/2D 1/2D 1/2D 1/2D
Layer 2 1/2D 1/2D 1/2D 1/2D
Layer 3 1/2D 1/2D 1/2D 1/2D
Layer 4 1/2D 1/2D 1/2D 1/2D
Layer 5 1/2D 1/2D 1/2D 1/2D
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 44
Analogue Flex CablesAnalogue Flex Cables
Low mass, fine pitch cables to bring analogue signals outside of tracking volume
Technically challenging» Feature size ~ 3-4 m
» C ~ 0.4 pF/cm Dyconex (Switzerland)
Delivered 2 pre-prototype cables» 128 channels, trace width 6-7 m
» 13.7 mm of 50 m pitch traces » 26.0 mm of 100 m pitch traces» fan-in and fan-out region (1.7-2.9
mm) » total trace length including
fan-in/out between 41.4 – 42.6 mm » 2 rows of bond pads on each side» No gold plating yet
Results so far are very encouraging
» Only 3 opens, no shorts» Uniform characteristics across cable
Detector HybridAnalogue
cableDigital cable DØ L0
Dyconex Pre-prototype Analogue Cable
0
50
100
150
200
250
300
0 20 40 60 80 100 120 140
Trace number
Tra
ce
Re
sis
tan
ce
(W
)
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 45
Design ConsiderationsDesign Considerations
Do not compromise on the performance of the Run2a silicon tracker Choose design adequate to achieve physics goals (no 90-degree
stereo), but do not over-design Provide stand-alone tracking up to || < 2.0 Modular design, minimize the number of different elements Use established technologies Divide tracker in two radial groups:
Inner layers» Design to withstand integrated luminosity
of 15 fb-1, with adequate margin » Provide path for possible replacement of only
innermost or both inner layers Outer layers
» Design to last a long time
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 46
Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 47
Layer 0 Support Structure AnalysisLayer 0 Support Structure Analysis
Measurements and Comparisons of elastic properties of prepreg. laminates
Strength of a variety of lay-ups, compared to theoretical predictions FEA analysis on prototype
L0 structuresimple supports at z = 0 and z =630 mm
Maximum sagitta = 4.63 m
C-fiber properties from UW test data 2/2/02Inner tube: 0/90/0 lay-up
Outer castellation: 0/+20/-20/-20/+20/0 lay-up
Good agreement between measurement and prediction
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