ele408 section 1. cont’d cortex m4 highly efficient 1qyang/ele408/syllabus/lecture2.pdf · dsp...
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Introduction to ARM Cortex-M4 Architecture
ELE408 Section 1. Cont’d Cortex M4 Highly efficient 1
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Cortex M4 Highly efficient 2
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SIMD(Single instruction Multiple data) Operations
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Cortex™-M4 Single Cycle MAC
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Cortex™-M4 SIMD arithmetic
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DSP Example: Cortex™-M4 FIR
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Cortex™-M4 Single Precision Floating Point
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Cortex™-M4 Floating Point Unit
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Kinetis Cortex-M4 Core Enhancements
• Up to 32-channel DMA – Reduced CPU loading – Faster system throughput
• Cross bar switch – Concurrent multi-master bus accesses
• Up to 8KB of instruction and 8KB of data cache – Optimized bus bandwidth and flash execution performance
• Independent flash banks – Concurrent code execution and firmware updating – No performance degradation or complex coding routines
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K70 Block Diagram
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Kinetis Bus Structure
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Cross Bar Switch Configuration
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XBS Example
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