efficient memory repair using cache based redundancy
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EFFICIENT MEMORY REPAIR USING
CACHE
-
BASED REDUNDANCY
Presented by
HEMALATHA MARDI
B090162EC
ECE A- batch
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Introduction
Escalate 90% of the die by 2014
Problems to be addressed asap
Susceptible to spot defects than logic
Moores law
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Background Work
Repair Processes
Automated test equipment (ATE)
Captures response
Applied externally or via bist circuitry
Processes data
Allocates spare resources
Built-in self-repair (BISR) techniques
Timely in socs
-Limited I/O bandwidth
- costly
Repair process on-chip
Redundancy concept
Intervenes decoding operation
Reroutes requests to reservoir cells
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Characterizing Memory Repair Architecture
Allocation scheme
Remaps process and the associated routing circuitry that redirects the
read/write requests from the faulty parts to the spare resources.
Spares usage ratio
It concerns how much of the redundant resources could potentially be expendedon repairing a faulty part i.e. the efficiency
Background Work
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Memory : A Yield Limiter Component
Yield limiter??Associated with defect density and critical area
Variability
Common denominator of continuous scaling beyond 90 nm era and
processing complexity required to attend this trend within givenspecifications
Symmetrical back-to-back inverter structure
Functional errors (e.g., the cell flips on word line activation during a read
access or over time, inability to write)
Parametric errors (e.g., unable to develop the required bitline differential
voltage in given wordline activation time)
Eg :- 6T SRAM cell
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SRAM cell probability of failure for Vtdeviations of 10-70 mV
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr.
(VLSI) Syst.,, vol. 20, no. 12, Dec 2012
SRAM 1- L=32nm, pull-up and access transistors at W=64, drivers at W=80 nm
SRAM 2- L=32nm, pull-up and access transistors at W=48, drivers at W=64 nm
Memory : A Yield Limiter Component
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Proposed cache-based memory repair architecture
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr.(VLSI) Syst.,, vol. 20, no. 12, Dec 2012 8
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Repair Analysis
Random Faults- mathematical analysis
Mapping process of the proposed memory repair scheme
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr. (VLSI)Syst.,, vol. 20, no. 12, Dec 2012 9
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Probability of fault free 64 Mbit cell array with random fault spread, a) without any repair
features, and b) with the proposed scheme. a) no redundancy (Pnr) b) with PR(64) P7
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr.(VLSI) Syst.,, vol. 20, no. 12, Dec 2012
Repair Analysis
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Repair process using (a) 6LSBs from A, failing to repair most faults and (b) the proposed index but
allocation scheme ( 3LSBs from Ar and 3LSBs from Ac) repairing the majority of faults
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst.,, vol. 20, no. 12, Dec 2012
Repair Analysis
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Clustered faults
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testing and fault mapping
call Test_Memory {Assemble faulty address list}B
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Overheads
The cache banks and the MURs have been modeled at 32 nm process using
CACTI
BIST circuitry_ March C- algorithm to support ABS circuitry
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Power (dynamic and static) and area overheads
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst.,, vol. 20, no. 12, Dec 2012 16
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Penalty of 1 MUX delay
find the faulty rows
repair faulty rows
March c- test requires 10N time to run
Final testing time ~ 2k x 10N ; k-no of cache banks
redundancy in multiple cache banks
power off the unnecessary modules
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Fault-tolerant memories utilizes
A spare row/columns scheme with a BIRA algorithm (optimizes
spare allocation)
CAM memory (replace the faulty words/bits of the MUR array)
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Conclusion
Set of small cache banks for repairing faulty words on memory cores
Optimized statistical and mathematical probability analysis to increase
Reparability and reduce overheads
Fault clustering and index bit allocation scheme_immune to clustering effect
Very high repair coverage for high defect densities at low area and
Static power dissipation overhead
32mb memory under repair , average of 512 faulty words
95%repairability
1.65%dynamic power
0.06% static power
0.07% area overhead
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