eeng449b/savvides lec 2.1 1/15/04 january 15, 2004 prof. andreas savvides spring 2004 eeng...
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EENG449b/SavvidesLec 2.1
1/15/04
January 15, 2004
Prof. Andreas Savvides
Spring 2004
EENG 449bG/CPSC 439bG Computer Systems
Lecture 2
Instruction Set Architectures
EENG449b/SavvidesLec 2.2
1/15/04
Updated Course Roadmap
Introduction and Performance Evaluation Instruction Set Architectures (Ch.2)Pipelining (Appendix A)2-3 Lectures in networked embedded systems and project related topics
Instruction Level Parallelism – ILP (Ch.3)Exploiting ILP in Software (Ch. 4)Memory Hierachies (Ch. 5)
Special Topics and Project Presentations
Keep looking at the course website updated information
HW1 & 2
Midterm I
Midterm II
HW3 & 4
EENG449b/SavvidesLec 2.3
1/15/04
The Instruction Set: a Critical Interface
instruction set
software
hardware
The instruction set is what theProgrammer sees about
the architecture
EENG449b/SavvidesLec 2.4
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Instruction Set Aspects(Sections 2.1 – 2.12 of text)
• Classes of Instruction Set Architectures
• Memory Addressing Issues• Addressing Modes• Instruction Operators• Instruction Set Encoding• Role of Compilers
EENG449b/SavvidesLec 2.5
1/15/04
Organization
Logic Designer's View
ISA Level
FUs & Interconnect
•Capabilities & Performance Characteristics of Principal Functional Units
– (e.g., Registers, ALU, Shifters, Logic Units, ...)
•Ways in which these components are interconnected
•Information flows between components
•Logic and means by which such information flow is controlled.
•Choreography of FUs to realize the ISA
•Register Transfer Level (RTL) Description
EENG449b/SavvidesLec 2.6
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Memory-Memory ISA Classes
• StackPush APush BAddPop C
No registers => less hardware but slow, cannot pipeline
• Accumulator – one operand is implicitly the accumulator (special purpose register e.g 6502 microntroller)
Load AAdd BStore C
No registers => less hardware, high memory traffic, slow/bottleneck
EENG449b/SavvidesLec 2.7
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Register based ISA Classes
• Register-MemoryLoad R1, AAdd R1, BStore C, R1
• Load-StoreLoad R1, ALoad R2, BAdd R3, R1, R2Store C, R3
» Registers are faster than memory» Registers are more efficient for
compilers» Compiler writers prefer all registers to
be equivalent
EENG449b/SavvidesLec 2.8
1/15/04
Instruction Sets in Modern Computers
• Most modern computers have 16 or more general purpose registers
• Specialized processors such as DSP processors still have several special purpose registers
• New ISAs are register based BUT there are still tradeoffs
– The ideal number of operands depends on the type of processor and application
– Fewer decisions on instruction formats easier for compiler writers
EENG449b/SavvidesLec 2.9
1/15/04
Memory Interpretation: Endianess
• Byte ordering becomes an issue when exchanging data between computers
– Little Endian – least significant bit to the right
7 6 5 4 3 2 1 0Intel 80x86, ARM, some 8-bit microcontollers (e.g Atmel’s AVR series)
– Big Endian – least significant bit to the left 0 1 2 3 4 5 6 7IBM 370, Motorola 68K, MIPS, Sparc, HP
EENG449b/SavvidesLec 2.10
1/15/04
Memory Interpretation: Alignment
• Objects larger than 1 byte must be aligned
• Misaligned memory accesses take multiple aligned memory references
• What do we mean by “aligned”
An object of size s bytes at byte address A is aligned IF
A mod s = 0
EENG449b/SavvidesLec 2.11
1/15/04
Addressing Modes
Register Add R3, R4 R3<- R3+R4Immediate Add R4, #3 R4<- R4+3Displacement Add R4, 100(R1) R4<- R4+Mem[100+R1] Register Indirect Add R4, (R1) R4<- Mem[R1]Indexed Add R3, (R1+R2) R3<- Mem[R1+R2]Direct or absolute Add R1, (1001) R1<- R1+Mem[1001]Memory indirect Add R1, @(R3) R1<- R1+Mem[Mem[R3]]Autoincrement Add R1, (R2)+ R1<-R1+Mem[R2]; R2<-
R2+dAutodecrement Add R1, -(R2) R2<-R2-d;R1<-R1+Mem[R2]Scaled Add R1, 100(R2)[R3] R1<-
R1+Mem[100+R2+R3xd]Modes 1-4 account for 93% of all VAX operands
EENG449b/SavvidesLec 2.12
1/15/04
Special Addressing Modes in DSP Processors
• Modulo or circular addressing– For reading buffers
• Bit reverse addressing- Address 100 becomes 001 - Special feature for DSPs
- Although DSP processors used to require customized programming, DSP programmers are coming closer to traditional compilers
- Automatic code-generation is also becoming a reality (e.g DSP algorithms in MATLAB can be automatically converted to DSP native code)
EENG449b/SavvidesLec 2.13
1/15/04
Instruction Operations
Arithmetic and logical- add, subtract, and, or multiply, divide
Data transfer - load-storesControl - Branch, jump, procedure call, return
trapsSystem – OS call, virtual memory management
instructionsFloating point – add, multiply, divide, compareDecimal – add, multiply, decimal to character
conversionString – move,compare, searchGraphics – Pixel and vector operations,
compress/decompress operations
EENG449b/SavvidesLec 2.14
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Control Flow Instructions
4 basic types• Conditional branches• Jumps• Procedure calls• Procedure returns
EENG449b/SavvidesLec 2.15
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Instruction Encoding
• How are instructions encoded in a binary representation to be executed by the processor
– Need to tell the processor the type of operation, and the addressing modes
• Many competing forces– Desire to have as many registers and addressing
modes as possible– Register sizes and addressing modes impact
instruction and program size– Instruction encoding should facilitate pipelining
» Instruction sizes multiple of bytes» Fixed length instructions may yield better
performance but result in larger average code sizes
EENG449b/SavvidesLec 2.16
1/15/04
Instruction Formats
Variable:
Fixed:
Hybrid:
…
•Addressing modes–each operand requires addess specifier => variable format
•code size => variable length instructions
•performance => fixed length instructions–simple decoding, predictable operations
•With load/store instruction arch, only one memory address and few addressing modes
•=> simple format, address mode given by opcode
EENG449b/SavvidesLec 2.17
1/15/04
Encoding the Instruction Set
EENG449b/SavvidesLec 2.18
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Role of Compilers
• ISA is a compiler target• Architectural decisions affect the
quality of code generated by the compiler
• Compiler goals– Priority– Correctness – Speed
• Fast compilation, debugging support & interoperability among languages
EENG449b/SavvidesLec 2.19
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Role of Compilers
EENG449b/SavvidesLec 2.20
1/15/04
Register Allocation
• Probably the most important optimization in compilers why?
• Most register allocation algorithms are based on graph coloring
– An optimization method– Construct a graph with the possible candidates for
allocation– Use a limited number of colors so that no two adjacent
nodes have the same color (so registers are represented by colors)
• Why is register allocation important?– You tell me…
• Why do compiler writers want lots of registers?– Register allocation with methods like graph coloring work
better when more registers are available.
• Refer to Figure 2.25 of text for a list of the major types of compiler optimizations
EENG449b/SavvidesLec 2.21
1/15/04
DSPs and Media Processors
• Both typically used in embedded applications
• Main difference from other microprocessors is real-time performance
– Worst case performance vs. average performance– Infinite, continuous streams of data vs. fixed data
set
• Small number of key kernels is critical, often supplied by manufacturer
– Libraries are important, widely used– Include tricks to improve performance for
targetted kernels but no compiler will generate
EENG449b/SavvidesLec 2.22
1/15/04
DSP Introduction
• Digital Signal Processing: Application of mathematical operations to digitally represented signals
• Signals represented as sequences of samples• Digital signals obtained from physical signals
via transducers (e.g microphones, accelerometers, seismic sensors) and analog-to-digital converters(ADC)
• Digital signals converted back to physical signals via digital-to-analog converters (DAC)
• Digital Signal Processor (DSP):electronic system that provides digital signals
Interaction with the physical world is becoming one of the most exciting fields for computer engineering!!!
EENG449b/SavvidesLec 2.23
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Common DSP Algorithms and Applications
• Applications – Instrumentation and measurement
– Communications– Audio and video processing– Graphics, image enhancement, 3-D rendering– Navigation, radar, GPS– Control – robotics, machine vision, guidance
• Algorithms– Frequency domain filtering – FIR and IIR– Frequency – time transformations– Correlation
EENG449b/SavvidesLec 2.24
1/15/04
Some Project Ideas…
• Embedded Operating Systems– Implement a small embedded operating system on a
microcontroller– Implement a specialized protocol or driver inside an
embedded operating system (e.g a protocol for node localization, or a time synchronization protocol)
– Develop a power saving scheme inside an embedded OS to utilize the power saving features of the specific processor
• Hardware/Software Interfacing– Experiments with acoustic data collection– Design & develop interfaces and/or instructions for
different sensors, control external entities for mobile nodes (e.g wheels or stepper motor gears)
• Algorithmic Oriented Projects– Develop a protocol for a new sensor network
application
EENG449b/SavvidesLec 2.25
1/15/04
Next Lecture
• MIPS architecture (starting Section 2.12 in textbook)
• HW1 will be distributed in class next week
– Due in 2 weeks from the day it is handed out
• Also next week– Project groups and project meetings
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